cpu.c revision 1.13
1 /* $NetBSD: cpu.c,v 1.13 2007/12/15 09:18:59 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999 Stefan Grefen 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by the NetBSD 53 * Foundation, Inc. and its contributors. 54 * 4. Neither the name of The NetBSD Foundation nor the names of its 55 * contributors may be used to endorse or promote products derived 56 * from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 59 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 66 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 68 * SUCH DAMAGE. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.13 2007/12/15 09:18:59 joerg Exp $"); 73 74 #include "opt_ddb.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_mpbios.h" /* for MPDEBUG */ 77 #include "opt_mtrr.h" 78 79 #include "lapic.h" 80 #include "ioapic.h" 81 82 #include <sys/param.h> 83 #include <sys/proc.h> 84 #include <sys/user.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/cpu.h> 89 #include <sys/atomic.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #ifdef i386 106 #include <machine/tlog.h> 107 #endif 108 109 #if NLAPIC > 0 110 #include <machine/apicvar.h> 111 #include <machine/i82489reg.h> 112 #include <machine/i82489var.h> 113 #endif 114 115 #if NIOAPIC > 0 116 #include <machine/i82093var.h> 117 #endif 118 119 #include <dev/ic/mc146818reg.h> 120 #include <i386/isa/nvram.h> 121 #include <dev/isa/isareg.h> 122 123 int cpu_match(struct device *, struct cfdata *, void *); 124 void cpu_attach(struct device *, struct device *, void *); 125 126 static bool cpu_suspend(device_t); 127 static bool cpu_resume(device_t); 128 129 struct cpu_softc { 130 struct device sc_dev; /* device tree glue */ 131 struct cpu_info *sc_info; /* pointer to CPU info */ 132 }; 133 134 int mp_cpu_start(struct cpu_info *); 135 void mp_cpu_start_cleanup(struct cpu_info *); 136 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 137 mp_cpu_start_cleanup }; 138 139 140 CFATTACH_DECL(cpu, sizeof(struct cpu_softc), 141 cpu_match, cpu_attach, NULL, NULL); 142 143 /* 144 * Statically-allocated CPU info for the primary CPU (or the only 145 * CPU, on uniprocessors). The CPU info list is initialized to 146 * point at it. 147 */ 148 #ifdef TRAPLOG 149 struct tlog tlog_primary; 150 #endif 151 struct cpu_info cpu_info_primary = { 152 .ci_dev = 0, 153 .ci_self = &cpu_info_primary, 154 .ci_idepth = -1, 155 .ci_curlwp = &lwp0, 156 #ifdef TRAPLOG 157 .ci_tlog_base = &tlog_primary, 158 #endif /* !TRAPLOG */ 159 }; 160 161 struct cpu_info *cpu_info_list = &cpu_info_primary; 162 163 static void cpu_set_tss_gates(struct cpu_info *); 164 165 #ifdef i386 166 static void cpu_init_tss(struct i386tss *, void *, void *); 167 #endif 168 169 #ifdef MULTIPROCESSOR 170 static void cpu_init_idle_lwp(struct cpu_info *); 171 #endif 172 173 uint32_t cpus_attached = 0; 174 uint32_t cpus_running = 0; 175 176 extern char x86_64_doubleflt_stack[]; 177 178 bool x86_mp_online; 179 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 180 181 #ifdef MULTIPROCESSOR 182 /* 183 * Array of CPU info structures. Must be statically-allocated because 184 * curproc, etc. are used early. 185 */ 186 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary, }; 187 188 void cpu_hatch(void *); 189 static void cpu_boot_secondary(struct cpu_info *ci); 190 static void cpu_start_secondary(struct cpu_info *ci); 191 static void cpu_copy_trampoline(void); 192 193 /* 194 * Runs once per boot once multiprocessor goo has been detected and 195 * the local APIC on the boot processor has been mapped. 196 * 197 * Called from lapic_boot_init() (from mpbios_scan()). 198 */ 199 void 200 cpu_init_first(void) 201 { 202 int cpunum = lapic_cpu_number(); 203 204 if (cpunum != 0) { 205 cpu_info[0] = NULL; 206 cpu_info[cpunum] = &cpu_info_primary; 207 } 208 209 cpu_info_primary.ci_cpuid = cpunum; 210 cpu_copy_trampoline(); 211 } 212 #endif 213 214 int 215 cpu_match(struct device *parent, struct cfdata *match, 216 void *aux) 217 { 218 219 return 1; 220 } 221 222 static void 223 cpu_vm_init(struct cpu_info *ci) 224 { 225 int ncolors = 2, i; 226 227 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 228 struct x86_cache_info *cai; 229 int tcolors; 230 231 cai = &ci->ci_cinfo[i]; 232 233 tcolors = atop(cai->cai_totalsize); 234 switch(cai->cai_associativity) { 235 case 0xff: 236 tcolors = 1; /* fully associative */ 237 break; 238 case 0: 239 case 1: 240 break; 241 default: 242 tcolors /= cai->cai_associativity; 243 } 244 ncolors = max(ncolors, tcolors); 245 } 246 247 /* 248 * Knowing the size of the largest cache on this CPU, re-color 249 * our pages. 250 */ 251 if (ncolors <= uvmexp.ncolors) 252 return; 253 aprint_verbose("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors); 254 uvm_page_recolor(ncolors); 255 } 256 257 258 void 259 cpu_attach(struct device *parent, struct device *self, void *aux) 260 { 261 struct cpu_softc *sc = (void *) self; 262 struct cpu_attach_args *caa = aux; 263 struct cpu_info *ci; 264 #if defined(MULTIPROCESSOR) 265 int cpunum = caa->cpu_number; 266 #endif 267 268 /* 269 * If we're an Application Processor, allocate a cpu_info 270 * structure, otherwise use the primary's. 271 */ 272 if (caa->cpu_role == CPU_ROLE_AP) { 273 aprint_naive(": Application Processor\n"); 274 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK); 275 memset(ci, 0, sizeof(*ci)); 276 #if defined(MULTIPROCESSOR) 277 if (cpu_info[cpunum] != NULL) { 278 printf("\n"); 279 panic("cpu at apic id %d already attached?", cpunum); 280 } 281 cpu_info[cpunum] = ci; 282 #endif 283 #ifdef TRAPLOG 284 ci->ci_tlog_base = malloc(sizeof(struct tlog), 285 M_DEVBUF, M_WAITOK); 286 #endif 287 } else { 288 aprint_naive(": %s Processor\n", 289 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 290 ci = &cpu_info_primary; 291 #if defined(MULTIPROCESSOR) 292 if (cpunum != lapic_cpu_number()) { 293 printf("\n"); 294 panic("%s: running CPU is at apic %d" 295 " instead of at expected %d", 296 sc->sc_dev.dv_xname, lapic_cpu_number(), cpunum); 297 } 298 #endif 299 } 300 301 ci->ci_self = ci; 302 sc->sc_info = ci; 303 304 ci->ci_dev = self; 305 ci->ci_apicid = caa->cpu_number; 306 #ifdef MULTIPROCESSOR 307 ci->ci_cpuid = ci->ci_apicid; 308 #else 309 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 310 #endif 311 ci->ci_cpumask = (1 << ci->ci_cpuid); 312 ci->ci_func = caa->cpu_func; 313 314 if (caa->cpu_role == CPU_ROLE_AP) { 315 #ifdef MULTIPROCESSOR 316 int error; 317 318 error = mi_cpu_attach(ci); 319 if (error != 0) { 320 aprint_normal("\n"); 321 aprint_error("%s: mi_cpu_attach failed with %d\n", 322 sc->sc_dev.dv_xname, error); 323 return; 324 } 325 #endif 326 } else { 327 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 328 } 329 330 pmap_reference(pmap_kernel()); 331 ci->ci_pmap = pmap_kernel(); 332 ci->ci_tlbstate = TLBSTATE_STALE; 333 334 /* further PCB init done later. */ 335 336 switch (caa->cpu_role) { 337 case CPU_ROLE_SP: 338 aprint_normal(": (uniprocessor)\n"); 339 atomic_or_32(&ci->ci_flags, 340 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 341 cpu_intr_init(ci); 342 identifycpu(ci); 343 cpu_init(ci); 344 cpu_set_tss_gates(ci); 345 pmap_cpu_init_late(ci); 346 x86_errata(); 347 break; 348 349 case CPU_ROLE_BP: 350 aprint_normal(": (boot processor)\n"); 351 atomic_or_32(&ci->ci_flags, 352 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 353 cpu_intr_init(ci); 354 identifycpu(ci); 355 cpu_init(ci); 356 cpu_set_tss_gates(ci); 357 pmap_cpu_init_late(ci); 358 #if NLAPIC > 0 359 /* 360 * Enable local apic 361 */ 362 lapic_enable(); 363 lapic_calibrate_timer(ci); 364 #endif 365 #if NIOAPIC > 0 366 ioapic_bsp_id = caa->cpu_number; 367 #endif 368 x86_errata(); 369 break; 370 371 case CPU_ROLE_AP: 372 /* 373 * report on an AP 374 */ 375 aprint_normal(": (application processor)\n"); 376 377 #if defined(MULTIPROCESSOR) 378 cpu_intr_init(ci); 379 gdt_alloc_cpu(ci); 380 cpu_set_tss_gates(ci); 381 pmap_cpu_init_early(ci); 382 pmap_cpu_init_late(ci); 383 cpu_start_secondary(ci); 384 if (ci->ci_flags & CPUF_PRESENT) { 385 identifycpu(ci); 386 ci->ci_next = cpu_info_list->ci_next; 387 cpu_info_list->ci_next = ci; 388 } 389 #else 390 aprint_normal("%s: not started\n", sc->sc_dev.dv_xname); 391 #endif 392 break; 393 394 default: 395 printf("\n"); 396 panic("unknown processor type??\n"); 397 } 398 cpu_vm_init(ci); 399 400 cpus_attached |= ci->ci_cpumask; 401 402 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 403 aprint_error_dev(self, "couldn't establish power handler\n"); 404 405 #if defined(MULTIPROCESSOR) 406 if (mp_verbose) { 407 struct lwp *l = ci->ci_data.cpu_idlelwp; 408 409 aprint_verbose( 410 "%s: idle lwp at %p, idle sp at %p\n", 411 sc->sc_dev.dv_xname, l, 412 #ifdef i386 413 (void *)l->l_addr->u_pcb.pcb_esp 414 #else 415 (void *)l->l_addr->u_pcb.pcb_rsp 416 #endif 417 ); 418 } 419 #endif 420 } 421 422 /* 423 * Initialize the processor appropriately. 424 */ 425 426 void 427 cpu_init(struct cpu_info *ci) 428 { 429 /* configure the CPU if needed */ 430 if (ci->cpu_setup != NULL) 431 (*ci->cpu_setup)(ci); 432 433 #ifdef i386 434 /* 435 * On a 486 or above, enable ring 0 write protection. 436 */ 437 if (ci->ci_cpu_class >= CPUCLASS_486) 438 lcr0(rcr0() | CR0_WP); 439 #else 440 lcr0(rcr0() | CR0_WP); 441 #endif 442 443 /* 444 * On a P6 or above, enable global TLB caching if the 445 * hardware supports it. 446 */ 447 if (cpu_feature & CPUID_PGE) 448 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 449 450 /* 451 * If we have FXSAVE/FXRESTOR, use them. 452 */ 453 if (cpu_feature & CPUID_FXSR) { 454 lcr4(rcr4() | CR4_OSFXSR); 455 456 /* 457 * If we have SSE/SSE2, enable XMM exceptions. 458 */ 459 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 460 lcr4(rcr4() | CR4_OSXMMEXCPT); 461 } 462 463 #ifdef MTRR 464 /* 465 * On a P6 or above, initialize MTRR's if the hardware supports them. 466 */ 467 if (cpu_feature & CPUID_MTRR) { 468 if ((ci->ci_flags & CPUF_AP) == 0) 469 i686_mtrr_init_first(); 470 mtrr_init_cpu(ci); 471 } 472 473 #ifdef i386 474 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 475 /* 476 * Must be a K6-2 Step >= 7 or a K6-III. 477 */ 478 if (CPUID2FAMILY(ci->ci_signature) == 5) { 479 if (CPUID2MODEL(ci->ci_signature) > 8 || 480 (CPUID2MODEL(ci->ci_signature) == 8 && 481 CPUID2STEPPING(ci->ci_signature) >= 7)) { 482 mtrr_funcs = &k6_mtrr_funcs; 483 k6_mtrr_init_first(); 484 mtrr_init_cpu(ci); 485 } 486 } 487 } 488 #endif /* i386 */ 489 #endif /* MTRR */ 490 491 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 492 atomic_or_32(&cpus_running, ci->ci_cpumask); 493 494 #ifndef MULTIPROCESSOR 495 /* XXX */ 496 x86_patch(); 497 #endif 498 } 499 500 #ifdef MULTIPROCESSOR 501 void 502 cpu_boot_secondary_processors(void) 503 { 504 struct cpu_info *ci; 505 u_long i; 506 507 /* Now that we know the number of CPUs, patch the text segment. */ 508 x86_patch(); 509 510 for (i=0; i < X86_MAXPROCS; i++) { 511 ci = cpu_info[i]; 512 if (ci == NULL) 513 continue; 514 if (ci->ci_data.cpu_idlelwp == NULL) 515 continue; 516 if ((ci->ci_flags & CPUF_PRESENT) == 0) 517 continue; 518 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 519 continue; 520 cpu_boot_secondary(ci); 521 } 522 523 x86_mp_online = true; 524 } 525 526 static void 527 cpu_init_idle_lwp(struct cpu_info *ci) 528 { 529 struct lwp *l = ci->ci_data.cpu_idlelwp; 530 struct pcb *pcb = &l->l_addr->u_pcb; 531 532 pcb->pcb_cr0 = rcr0(); 533 } 534 535 void 536 cpu_init_idle_lwps(void) 537 { 538 struct cpu_info *ci; 539 u_long i; 540 541 for (i = 0; i < X86_MAXPROCS; i++) { 542 ci = cpu_info[i]; 543 if (ci == NULL) 544 continue; 545 if (ci->ci_data.cpu_idlelwp == NULL) 546 continue; 547 if ((ci->ci_flags & CPUF_PRESENT) == 0) 548 continue; 549 cpu_init_idle_lwp(ci); 550 } 551 } 552 553 void 554 cpu_start_secondary(struct cpu_info *ci) 555 { 556 int i; 557 extern paddr_t mp_pdirpa; 558 559 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 560 561 atomic_or_32(&ci->ci_flags, CPUF_AP); 562 563 aprint_debug("%s: starting\n", ci->ci_dev->dv_xname); 564 565 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 566 CPU_STARTUP(ci); 567 568 /* 569 * wait for it to become ready 570 */ 571 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) { 572 i8254_delay(10); 573 } 574 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 575 aprint_error("%s: failed to become ready\n", 576 ci->ci_dev->dv_xname); 577 #if defined(MPDEBUG) && defined(DDB) 578 printf("dropping into debugger; continue from here to resume boot\n"); 579 Debugger(); 580 #endif 581 } 582 583 CPU_START_CLEANUP(ci); 584 } 585 586 void 587 cpu_boot_secondary(struct cpu_info *ci) 588 { 589 int i; 590 591 atomic_or_32(&ci->ci_flags, CPUF_GO); 592 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) { 593 i8254_delay(10); 594 } 595 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 596 aprint_error("%s: failed to start\n", ci->ci_dev->dv_xname); 597 #if defined(MPDEBUG) && defined(DDB) 598 printf("dropping into debugger; continue from here to resume boot\n"); 599 Debugger(); 600 #endif 601 } 602 } 603 604 /* 605 * The CPU ends up here when its ready to run 606 * This is called from code in mptramp.s; at this point, we are running 607 * in the idle pcb/idle stack of the new CPU. When this function returns, 608 * this processor will enter the idle loop and start looking for work. 609 */ 610 void 611 cpu_hatch(void *v) 612 { 613 struct cpu_info *ci = (struct cpu_info *)v; 614 int s, i; 615 616 #ifdef __x86_64__ 617 cpu_init_msrs(ci, true); 618 #endif 619 cpu_probe_features(ci); 620 cpu_feature &= ci->ci_feature_flags; 621 cpu_feature2 &= ci->ci_feature2_flags; 622 623 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 624 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 625 while ((ci->ci_flags & CPUF_GO) == 0) { 626 /* Don't use delay, boot CPU may be patching the text. */ 627 for (i = 10000; i != 0; i--) 628 x86_pause(); 629 } 630 631 /* Beacuse the text may have been patched in x86_patch(). */ 632 wbinvd(); 633 x86_flush(); 634 635 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 636 637 lcr3(pmap_kernel()->pm_pdirpa); 638 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 639 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 640 cpu_init_idt(); 641 gdt_init_cpu(ci); 642 lapic_enable(); 643 lapic_set_lvt(); 644 lapic_initclocks(); 645 646 #ifdef i386 647 npxinit(ci); 648 #else 649 fpuinit(ci); 650 #endif 651 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 652 653 cpu_init(ci); 654 cpu_get_tsc_freq(ci); 655 656 s = splhigh(); 657 #ifdef i386 658 lapic_tpr = 0; 659 #else 660 lcr8(0); 661 #endif 662 x86_enable_intr(); 663 splx(s); 664 x86_errata(); 665 666 aprint_debug("%s: CPU %ld running\n", ci->ci_dev->dv_xname, 667 (long)ci->ci_cpuid); 668 } 669 670 #if defined(DDB) 671 672 #include <ddb/db_output.h> 673 #include <machine/db_machdep.h> 674 675 /* 676 * Dump CPU information from ddb. 677 */ 678 void 679 cpu_debug_dump(void) 680 { 681 struct cpu_info *ci; 682 CPU_INFO_ITERATOR cii; 683 684 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 685 for (CPU_INFO_FOREACH(cii, ci)) { 686 db_printf("%p %s %ld %x %x %10p %10p\n", 687 ci, 688 ci->ci_dev == NULL ? "BOOT" : ci->ci_dev->dv_xname, 689 (long)ci->ci_cpuid, 690 ci->ci_flags, ci->ci_ipis, 691 ci->ci_curlwp, 692 ci->ci_fpcurlwp); 693 } 694 } 695 #endif 696 697 static void 698 cpu_copy_trampoline(void) 699 { 700 /* 701 * Copy boot code. 702 */ 703 extern u_char cpu_spinup_trampoline[]; 704 extern u_char cpu_spinup_trampoline_end[]; 705 706 vaddr_t mp_trampoline_vaddr; 707 708 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 709 UVM_KMF_VAONLY); 710 711 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 712 VM_PROT_READ | VM_PROT_WRITE); 713 pmap_update(pmap_kernel()); 714 memcpy((void *)mp_trampoline_vaddr, 715 cpu_spinup_trampoline, 716 cpu_spinup_trampoline_end-cpu_spinup_trampoline); 717 718 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 719 pmap_update(pmap_kernel()); 720 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 721 } 722 723 #endif 724 725 #ifdef i386 726 static void 727 cpu_init_tss(struct i386tss *tss, void *stack, void *func) 728 { 729 memset(tss, 0, sizeof *tss); 730 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 731 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 732 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 733 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 734 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 735 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 736 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 737 tss->tss_esp = (int)((char *)stack + USPACE - 16); 738 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 739 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 740 tss->__tss_eip = (int)func; 741 } 742 743 /* XXX */ 744 #define IDTVEC(name) __CONCAT(X, name) 745 typedef void (vector)(void); 746 extern vector IDTVEC(tss_trap08); 747 #ifdef DDB 748 extern vector Xintrddbipi; 749 extern int ddb_vec; 750 #endif 751 752 static void 753 cpu_set_tss_gates(struct cpu_info *ci) 754 { 755 struct segment_descriptor sd; 756 757 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 758 UVM_KMF_WIRED); 759 cpu_init_tss(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 760 IDTVEC(tss_trap08)); 761 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 762 SDT_SYS386TSS, SEL_KPL, 0, 0); 763 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 764 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 765 GSEL(GTRAPTSS_SEL, SEL_KPL)); 766 767 #if defined(DDB) && defined(MULTIPROCESSOR) 768 /* 769 * Set up separate handler for the DDB IPI, so that it doesn't 770 * stomp on a possibly corrupted stack. 771 * 772 * XXX overwriting the gate set in db_machine_init. 773 * Should rearrange the code so that it's set only once. 774 */ 775 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 776 UVM_KMF_WIRED); 777 cpu_init_tss(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 778 Xintrddbipi); 779 780 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 781 SDT_SYS386TSS, SEL_KPL, 0, 0); 782 ci->ci_gdt[GIPITSS_SEL].sd = sd; 783 784 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 785 GSEL(GIPITSS_SEL, SEL_KPL)); 786 #endif 787 } 788 #else 789 static void 790 cpu_set_tss_gates(struct cpu_info *ci) 791 { 792 793 } 794 #endif /* i386 */ 795 796 797 int 798 mp_cpu_start(struct cpu_info *ci) 799 { 800 #if NLAPIC > 0 801 int error; 802 #endif 803 unsigned short dwordptr[2]; 804 vaddr_t kva; 805 806 /* 807 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 808 */ 809 810 outb(IO_RTC, NVRAM_RESET); 811 outb(IO_RTC+1, NVRAM_RESET_JUMP); 812 813 /* 814 * "and the warm reset vector (DWORD based at 40:67) to point 815 * to the AP startup code ..." 816 */ 817 818 dwordptr[0] = 0; 819 dwordptr[1] = mp_trampoline_paddr >> 4; 820 821 kva = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 822 if ((void *)kva == NULL) 823 return ENOMEM; 824 pmap_kenter_pa(kva, 0, VM_PROT_READ|VM_PROT_WRITE); 825 pmap_update(pmap_kernel()); 826 memcpy((uint8_t *)(kva + 0x467), dwordptr, 4); 827 pmap_kremove(kva, PAGE_SIZE); 828 pmap_update(pmap_kernel()); 829 uvm_km_free(kernel_map, kva, PAGE_SIZE, UVM_KMF_VAONLY); 830 831 #if NLAPIC > 0 832 /* 833 * ... prior to executing the following sequence:" 834 */ 835 836 if (ci->ci_flags & CPUF_AP) { 837 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 838 return error; 839 840 i8254_delay(10000); 841 842 if (cpu_feature & CPUID_APIC) { 843 844 if ((error = x86_ipi(mp_trampoline_paddr / PAGE_SIZE, 845 ci->ci_apicid, 846 LAPIC_DLMODE_STARTUP)) != 0) 847 return error; 848 i8254_delay(200); 849 850 if ((error = x86_ipi(mp_trampoline_paddr / PAGE_SIZE, 851 ci->ci_apicid, 852 LAPIC_DLMODE_STARTUP)) != 0) 853 return error; 854 i8254_delay(200); 855 } 856 } 857 #endif 858 return 0; 859 } 860 861 void 862 mp_cpu_start_cleanup(struct cpu_info *ci) 863 { 864 /* 865 * Ensure the NVRAM reset byte contains something vaguely sane. 866 */ 867 868 outb(IO_RTC, NVRAM_RESET); 869 outb(IO_RTC+1, NVRAM_RESET_RST); 870 } 871 872 #ifdef __x86_64__ 873 typedef void (vector)(void); 874 extern vector Xsyscall, Xsyscall32; 875 876 void 877 cpu_init_msrs(struct cpu_info *ci, bool full) 878 { 879 wrmsr(MSR_STAR, 880 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 881 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 882 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 883 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 884 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 885 886 if (full) { 887 wrmsr(MSR_FSBASE, 0); 888 wrmsr(MSR_GSBASE, (u_int64_t)ci); 889 wrmsr(MSR_KERNELGSBASE, 0); 890 } 891 892 if (cpu_feature & CPUID_NOX) 893 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 894 } 895 #endif /* __x86_64__ */ 896 897 /* XXX joerg restructure and restart CPUs individually */ 898 static bool 899 cpu_suspend(device_t dv) 900 { 901 struct cpu_softc *sc = device_private(dv); 902 struct cpu_info *ci = sc->sc_info; 903 int err; 904 905 if (ci->ci_flags & CPUF_PRIMARY) 906 return true; 907 if (ci->ci_data.cpu_idlelwp == NULL) 908 return true; 909 if ((ci->ci_flags & CPUF_PRESENT) == 0) 910 return true; 911 912 mutex_enter(&cpu_lock); 913 err = cpu_setonline(ci, false); 914 mutex_exit(&cpu_lock); 915 return err == 0; 916 } 917 918 static bool 919 cpu_resume(device_t dv) 920 { 921 struct cpu_softc *sc = device_private(dv); 922 struct cpu_info *ci = sc->sc_info; 923 int err; 924 925 if (ci->ci_flags & CPUF_PRIMARY) 926 return true; 927 if (ci->ci_data.cpu_idlelwp == NULL) 928 return true; 929 if ((ci->ci_flags & CPUF_PRESENT) == 0) 930 return true; 931 932 mutex_enter(&cpu_lock); 933 err = cpu_setonline(ci, true); 934 mutex_exit(&cpu_lock); 935 936 return err == 0; 937 } 938 939 void 940 cpu_get_tsc_freq(struct cpu_info *ci) 941 { 942 uint64_t last_tsc; 943 u_int junk[4]; 944 945 if (ci->ci_feature_flags & CPUID_TSC) { 946 /* Serialize. */ 947 x86_cpuid(0, junk); 948 last_tsc = rdtsc(); 949 i8254_delay(100000); 950 ci->ci_tsc_freq = (rdtsc() - last_tsc) * 10; 951 } 952 } 953
Indexes created Mon Sep 22 13:09:51 GMT 2025