cpu.c revision 1.14
1 /* $NetBSD: cpu.c,v 1.14 2007/12/18 07:17:17 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999 Stefan Grefen 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by the NetBSD 53 * Foundation, Inc. and its contributors. 54 * 4. Neither the name of The NetBSD Foundation nor the names of its 55 * contributors may be used to endorse or promote products derived 56 * from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 59 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 66 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 68 * SUCH DAMAGE. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.14 2007/12/18 07:17:17 joerg Exp $"); 73 74 #include "opt_ddb.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_mpbios.h" /* for MPDEBUG */ 77 #include "opt_mtrr.h" 78 79 #include "lapic.h" 80 #include "ioapic.h" 81 82 #include <sys/param.h> 83 #include <sys/proc.h> 84 #include <sys/user.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/cpu.h> 89 #include <sys/atomic.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #ifdef i386 106 #include <machine/tlog.h> 107 #endif 108 109 #if NLAPIC > 0 110 #include <machine/apicvar.h> 111 #include <machine/i82489reg.h> 112 #include <machine/i82489var.h> 113 #endif 114 115 #if NIOAPIC > 0 116 #include <machine/i82093var.h> 117 #endif 118 119 #include <dev/ic/mc146818reg.h> 120 #include <i386/isa/nvram.h> 121 #include <dev/isa/isareg.h> 122 123 int cpu_match(struct device *, struct cfdata *, void *); 124 void cpu_attach(struct device *, struct device *, void *); 125 126 static bool cpu_suspend(device_t); 127 static bool cpu_resume(device_t); 128 129 struct cpu_softc { 130 struct device sc_dev; /* device tree glue */ 131 struct cpu_info *sc_info; /* pointer to CPU info */ 132 }; 133 134 int mp_cpu_start(struct cpu_info *, paddr_t); 135 void mp_cpu_start_cleanup(struct cpu_info *); 136 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 137 mp_cpu_start_cleanup }; 138 139 140 CFATTACH_DECL(cpu, sizeof(struct cpu_softc), 141 cpu_match, cpu_attach, NULL, NULL); 142 143 /* 144 * Statically-allocated CPU info for the primary CPU (or the only 145 * CPU, on uniprocessors). The CPU info list is initialized to 146 * point at it. 147 */ 148 #ifdef TRAPLOG 149 struct tlog tlog_primary; 150 #endif 151 struct cpu_info cpu_info_primary = { 152 .ci_dev = 0, 153 .ci_self = &cpu_info_primary, 154 .ci_idepth = -1, 155 .ci_curlwp = &lwp0, 156 #ifdef TRAPLOG 157 .ci_tlog_base = &tlog_primary, 158 #endif /* !TRAPLOG */ 159 }; 160 161 struct cpu_info *cpu_info_list = &cpu_info_primary; 162 163 static void cpu_set_tss_gates(struct cpu_info *); 164 165 #ifdef i386 166 static void cpu_init_tss(struct i386tss *, void *, void *); 167 #endif 168 169 #ifdef MULTIPROCESSOR 170 static void cpu_init_idle_lwp(struct cpu_info *); 171 #endif 172 173 uint32_t cpus_attached = 0; 174 uint32_t cpus_running = 0; 175 176 extern char x86_64_doubleflt_stack[]; 177 178 bool x86_mp_online; 179 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 180 181 static vaddr_t cmos_data_mapping; 182 183 #ifdef MULTIPROCESSOR 184 /* 185 * Array of CPU info structures. Must be statically-allocated because 186 * curproc, etc. are used early. 187 */ 188 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary, }; 189 190 void cpu_hatch(void *); 191 static void cpu_boot_secondary(struct cpu_info *ci); 192 static void cpu_start_secondary(struct cpu_info *ci); 193 static void cpu_copy_trampoline(void); 194 195 /* 196 * Runs once per boot once multiprocessor goo has been detected and 197 * the local APIC on the boot processor has been mapped. 198 * 199 * Called from lapic_boot_init() (from mpbios_scan()). 200 */ 201 void 202 cpu_init_first(void) 203 { 204 int cpunum = lapic_cpu_number(); 205 206 if (cpunum != 0) { 207 cpu_info[0] = NULL; 208 cpu_info[cpunum] = &cpu_info_primary; 209 } 210 211 cpu_info_primary.ci_cpuid = cpunum; 212 cpu_copy_trampoline(); 213 214 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 215 if (cmos_data_mapping == 0) 216 panic("No KVA for page 0"); 217 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE); 218 pmap_update(pmap_kernel()); 219 } 220 #endif 221 222 int 223 cpu_match(struct device *parent, struct cfdata *match, 224 void *aux) 225 { 226 227 return 1; 228 } 229 230 static void 231 cpu_vm_init(struct cpu_info *ci) 232 { 233 int ncolors = 2, i; 234 235 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 236 struct x86_cache_info *cai; 237 int tcolors; 238 239 cai = &ci->ci_cinfo[i]; 240 241 tcolors = atop(cai->cai_totalsize); 242 switch(cai->cai_associativity) { 243 case 0xff: 244 tcolors = 1; /* fully associative */ 245 break; 246 case 0: 247 case 1: 248 break; 249 default: 250 tcolors /= cai->cai_associativity; 251 } 252 ncolors = max(ncolors, tcolors); 253 } 254 255 /* 256 * Knowing the size of the largest cache on this CPU, re-color 257 * our pages. 258 */ 259 if (ncolors <= uvmexp.ncolors) 260 return; 261 aprint_verbose("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors); 262 uvm_page_recolor(ncolors); 263 } 264 265 266 void 267 cpu_attach(struct device *parent, struct device *self, void *aux) 268 { 269 struct cpu_softc *sc = (void *) self; 270 struct cpu_attach_args *caa = aux; 271 struct cpu_info *ci; 272 #if defined(MULTIPROCESSOR) 273 int cpunum = caa->cpu_number; 274 #endif 275 276 /* 277 * If we're an Application Processor, allocate a cpu_info 278 * structure, otherwise use the primary's. 279 */ 280 if (caa->cpu_role == CPU_ROLE_AP) { 281 aprint_naive(": Application Processor\n"); 282 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK); 283 memset(ci, 0, sizeof(*ci)); 284 #if defined(MULTIPROCESSOR) 285 if (cpu_info[cpunum] != NULL) { 286 printf("\n"); 287 panic("cpu at apic id %d already attached?", cpunum); 288 } 289 cpu_info[cpunum] = ci; 290 #endif 291 #ifdef TRAPLOG 292 ci->ci_tlog_base = malloc(sizeof(struct tlog), 293 M_DEVBUF, M_WAITOK); 294 #endif 295 } else { 296 aprint_naive(": %s Processor\n", 297 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 298 ci = &cpu_info_primary; 299 #if defined(MULTIPROCESSOR) 300 if (cpunum != lapic_cpu_number()) { 301 printf("\n"); 302 panic("%s: running CPU is at apic %d" 303 " instead of at expected %d", 304 sc->sc_dev.dv_xname, lapic_cpu_number(), cpunum); 305 } 306 #endif 307 } 308 309 ci->ci_self = ci; 310 sc->sc_info = ci; 311 312 ci->ci_dev = self; 313 ci->ci_apicid = caa->cpu_number; 314 #ifdef MULTIPROCESSOR 315 ci->ci_cpuid = ci->ci_apicid; 316 #else 317 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 318 #endif 319 ci->ci_cpumask = (1 << ci->ci_cpuid); 320 ci->ci_func = caa->cpu_func; 321 322 if (caa->cpu_role == CPU_ROLE_AP) { 323 #ifdef MULTIPROCESSOR 324 int error; 325 326 error = mi_cpu_attach(ci); 327 if (error != 0) { 328 aprint_normal("\n"); 329 aprint_error("%s: mi_cpu_attach failed with %d\n", 330 sc->sc_dev.dv_xname, error); 331 return; 332 } 333 #endif 334 } else { 335 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 336 } 337 338 pmap_reference(pmap_kernel()); 339 ci->ci_pmap = pmap_kernel(); 340 ci->ci_tlbstate = TLBSTATE_STALE; 341 342 /* further PCB init done later. */ 343 344 switch (caa->cpu_role) { 345 case CPU_ROLE_SP: 346 aprint_normal(": (uniprocessor)\n"); 347 atomic_or_32(&ci->ci_flags, 348 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 349 cpu_intr_init(ci); 350 identifycpu(ci); 351 cpu_init(ci); 352 cpu_set_tss_gates(ci); 353 pmap_cpu_init_late(ci); 354 x86_errata(); 355 break; 356 357 case CPU_ROLE_BP: 358 aprint_normal(": (boot processor)\n"); 359 atomic_or_32(&ci->ci_flags, 360 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 361 cpu_intr_init(ci); 362 identifycpu(ci); 363 cpu_init(ci); 364 cpu_set_tss_gates(ci); 365 pmap_cpu_init_late(ci); 366 #if NLAPIC > 0 367 /* 368 * Enable local apic 369 */ 370 lapic_enable(); 371 lapic_calibrate_timer(ci); 372 #endif 373 #if NIOAPIC > 0 374 ioapic_bsp_id = caa->cpu_number; 375 #endif 376 x86_errata(); 377 break; 378 379 case CPU_ROLE_AP: 380 /* 381 * report on an AP 382 */ 383 aprint_normal(": (application processor)\n"); 384 385 #if defined(MULTIPROCESSOR) 386 cpu_intr_init(ci); 387 gdt_alloc_cpu(ci); 388 cpu_set_tss_gates(ci); 389 pmap_cpu_init_early(ci); 390 pmap_cpu_init_late(ci); 391 cpu_start_secondary(ci); 392 if (ci->ci_flags & CPUF_PRESENT) { 393 identifycpu(ci); 394 ci->ci_next = cpu_info_list->ci_next; 395 cpu_info_list->ci_next = ci; 396 } 397 #else 398 aprint_normal("%s: not started\n", sc->sc_dev.dv_xname); 399 #endif 400 break; 401 402 default: 403 printf("\n"); 404 panic("unknown processor type??\n"); 405 } 406 cpu_vm_init(ci); 407 408 cpus_attached |= ci->ci_cpumask; 409 410 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 411 aprint_error_dev(self, "couldn't establish power handler\n"); 412 413 #if defined(MULTIPROCESSOR) 414 if (mp_verbose) { 415 struct lwp *l = ci->ci_data.cpu_idlelwp; 416 417 aprint_verbose( 418 "%s: idle lwp at %p, idle sp at %p\n", 419 sc->sc_dev.dv_xname, l, 420 #ifdef i386 421 (void *)l->l_addr->u_pcb.pcb_esp 422 #else 423 (void *)l->l_addr->u_pcb.pcb_rsp 424 #endif 425 ); 426 } 427 #endif 428 } 429 430 /* 431 * Initialize the processor appropriately. 432 */ 433 434 void 435 cpu_init(struct cpu_info *ci) 436 { 437 /* configure the CPU if needed */ 438 if (ci->cpu_setup != NULL) 439 (*ci->cpu_setup)(ci); 440 441 #ifdef i386 442 /* 443 * On a 486 or above, enable ring 0 write protection. 444 */ 445 if (ci->ci_cpu_class >= CPUCLASS_486) 446 lcr0(rcr0() | CR0_WP); 447 #else 448 lcr0(rcr0() | CR0_WP); 449 #endif 450 451 /* 452 * On a P6 or above, enable global TLB caching if the 453 * hardware supports it. 454 */ 455 if (cpu_feature & CPUID_PGE) 456 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 457 458 /* 459 * If we have FXSAVE/FXRESTOR, use them. 460 */ 461 if (cpu_feature & CPUID_FXSR) { 462 lcr4(rcr4() | CR4_OSFXSR); 463 464 /* 465 * If we have SSE/SSE2, enable XMM exceptions. 466 */ 467 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 468 lcr4(rcr4() | CR4_OSXMMEXCPT); 469 } 470 471 #ifdef MTRR 472 /* 473 * On a P6 or above, initialize MTRR's if the hardware supports them. 474 */ 475 if (cpu_feature & CPUID_MTRR) { 476 if ((ci->ci_flags & CPUF_AP) == 0) 477 i686_mtrr_init_first(); 478 mtrr_init_cpu(ci); 479 } 480 481 #ifdef i386 482 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 483 /* 484 * Must be a K6-2 Step >= 7 or a K6-III. 485 */ 486 if (CPUID2FAMILY(ci->ci_signature) == 5) { 487 if (CPUID2MODEL(ci->ci_signature) > 8 || 488 (CPUID2MODEL(ci->ci_signature) == 8 && 489 CPUID2STEPPING(ci->ci_signature) >= 7)) { 490 mtrr_funcs = &k6_mtrr_funcs; 491 k6_mtrr_init_first(); 492 mtrr_init_cpu(ci); 493 } 494 } 495 } 496 #endif /* i386 */ 497 #endif /* MTRR */ 498 499 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 500 atomic_or_32(&cpus_running, ci->ci_cpumask); 501 502 #ifndef MULTIPROCESSOR 503 /* XXX */ 504 x86_patch(); 505 #endif 506 } 507 508 #ifdef MULTIPROCESSOR 509 void 510 cpu_boot_secondary_processors(void) 511 { 512 struct cpu_info *ci; 513 u_long i; 514 515 /* Now that we know the number of CPUs, patch the text segment. */ 516 x86_patch(); 517 518 for (i=0; i < X86_MAXPROCS; i++) { 519 ci = cpu_info[i]; 520 if (ci == NULL) 521 continue; 522 if (ci->ci_data.cpu_idlelwp == NULL) 523 continue; 524 if ((ci->ci_flags & CPUF_PRESENT) == 0) 525 continue; 526 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 527 continue; 528 cpu_boot_secondary(ci); 529 } 530 531 x86_mp_online = true; 532 } 533 534 static void 535 cpu_init_idle_lwp(struct cpu_info *ci) 536 { 537 struct lwp *l = ci->ci_data.cpu_idlelwp; 538 struct pcb *pcb = &l->l_addr->u_pcb; 539 540 pcb->pcb_cr0 = rcr0(); 541 } 542 543 void 544 cpu_init_idle_lwps(void) 545 { 546 struct cpu_info *ci; 547 u_long i; 548 549 for (i = 0; i < X86_MAXPROCS; i++) { 550 ci = cpu_info[i]; 551 if (ci == NULL) 552 continue; 553 if (ci->ci_data.cpu_idlelwp == NULL) 554 continue; 555 if ((ci->ci_flags & CPUF_PRESENT) == 0) 556 continue; 557 cpu_init_idle_lwp(ci); 558 } 559 } 560 561 void 562 cpu_start_secondary(struct cpu_info *ci) 563 { 564 int i; 565 extern paddr_t mp_pdirpa; 566 567 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 568 569 atomic_or_32(&ci->ci_flags, CPUF_AP); 570 571 aprint_debug("%s: starting\n", ci->ci_dev->dv_xname); 572 573 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 574 CPU_STARTUP(ci, mp_trampoline_paddr); 575 576 /* 577 * wait for it to become ready 578 */ 579 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) { 580 i8254_delay(10); 581 } 582 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 583 aprint_error("%s: failed to become ready\n", 584 ci->ci_dev->dv_xname); 585 #if defined(MPDEBUG) && defined(DDB) 586 printf("dropping into debugger; continue from here to resume boot\n"); 587 Debugger(); 588 #endif 589 } 590 591 CPU_START_CLEANUP(ci); 592 } 593 594 void 595 cpu_boot_secondary(struct cpu_info *ci) 596 { 597 int i; 598 599 atomic_or_32(&ci->ci_flags, CPUF_GO); 600 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) { 601 i8254_delay(10); 602 } 603 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 604 aprint_error("%s: failed to start\n", ci->ci_dev->dv_xname); 605 #if defined(MPDEBUG) && defined(DDB) 606 printf("dropping into debugger; continue from here to resume boot\n"); 607 Debugger(); 608 #endif 609 } 610 } 611 612 /* 613 * The CPU ends up here when its ready to run 614 * This is called from code in mptramp.s; at this point, we are running 615 * in the idle pcb/idle stack of the new CPU. When this function returns, 616 * this processor will enter the idle loop and start looking for work. 617 */ 618 void 619 cpu_hatch(void *v) 620 { 621 struct cpu_info *ci = (struct cpu_info *)v; 622 int s, i; 623 624 #ifdef __x86_64__ 625 cpu_init_msrs(ci, true); 626 #endif 627 cpu_probe_features(ci); 628 cpu_feature &= ci->ci_feature_flags; 629 cpu_feature2 &= ci->ci_feature2_flags; 630 631 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 632 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 633 while ((ci->ci_flags & CPUF_GO) == 0) { 634 /* Don't use delay, boot CPU may be patching the text. */ 635 for (i = 10000; i != 0; i--) 636 x86_pause(); 637 } 638 639 /* Beacuse the text may have been patched in x86_patch(). */ 640 wbinvd(); 641 x86_flush(); 642 643 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 644 645 lcr3(pmap_kernel()->pm_pdirpa); 646 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 647 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 648 cpu_init_idt(); 649 gdt_init_cpu(ci); 650 lapic_enable(); 651 lapic_set_lvt(); 652 lapic_initclocks(); 653 654 #ifdef i386 655 npxinit(ci); 656 #else 657 fpuinit(ci); 658 #endif 659 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 660 661 cpu_init(ci); 662 cpu_get_tsc_freq(ci); 663 664 s = splhigh(); 665 #ifdef i386 666 lapic_tpr = 0; 667 #else 668 lcr8(0); 669 #endif 670 x86_enable_intr(); 671 splx(s); 672 x86_errata(); 673 674 aprint_debug("%s: CPU %ld running\n", ci->ci_dev->dv_xname, 675 (long)ci->ci_cpuid); 676 } 677 678 #if defined(DDB) 679 680 #include <ddb/db_output.h> 681 #include <machine/db_machdep.h> 682 683 /* 684 * Dump CPU information from ddb. 685 */ 686 void 687 cpu_debug_dump(void) 688 { 689 struct cpu_info *ci; 690 CPU_INFO_ITERATOR cii; 691 692 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 693 for (CPU_INFO_FOREACH(cii, ci)) { 694 db_printf("%p %s %ld %x %x %10p %10p\n", 695 ci, 696 ci->ci_dev == NULL ? "BOOT" : ci->ci_dev->dv_xname, 697 (long)ci->ci_cpuid, 698 ci->ci_flags, ci->ci_ipis, 699 ci->ci_curlwp, 700 ci->ci_fpcurlwp); 701 } 702 } 703 #endif 704 705 static void 706 cpu_copy_trampoline(void) 707 { 708 /* 709 * Copy boot code. 710 */ 711 extern u_char cpu_spinup_trampoline[]; 712 extern u_char cpu_spinup_trampoline_end[]; 713 714 vaddr_t mp_trampoline_vaddr; 715 716 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 717 UVM_KMF_VAONLY); 718 719 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 720 VM_PROT_READ | VM_PROT_WRITE); 721 pmap_update(pmap_kernel()); 722 memcpy((void *)mp_trampoline_vaddr, 723 cpu_spinup_trampoline, 724 cpu_spinup_trampoline_end-cpu_spinup_trampoline); 725 726 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 727 pmap_update(pmap_kernel()); 728 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 729 } 730 731 #endif 732 733 #ifdef i386 734 static void 735 cpu_init_tss(struct i386tss *tss, void *stack, void *func) 736 { 737 memset(tss, 0, sizeof *tss); 738 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 739 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 740 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 741 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 742 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 743 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 744 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 745 tss->tss_esp = (int)((char *)stack + USPACE - 16); 746 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 747 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 748 tss->__tss_eip = (int)func; 749 } 750 751 /* XXX */ 752 #define IDTVEC(name) __CONCAT(X, name) 753 typedef void (vector)(void); 754 extern vector IDTVEC(tss_trap08); 755 #ifdef DDB 756 extern vector Xintrddbipi; 757 extern int ddb_vec; 758 #endif 759 760 static void 761 cpu_set_tss_gates(struct cpu_info *ci) 762 { 763 struct segment_descriptor sd; 764 765 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 766 UVM_KMF_WIRED); 767 cpu_init_tss(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 768 IDTVEC(tss_trap08)); 769 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 770 SDT_SYS386TSS, SEL_KPL, 0, 0); 771 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 772 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 773 GSEL(GTRAPTSS_SEL, SEL_KPL)); 774 775 #if defined(DDB) && defined(MULTIPROCESSOR) 776 /* 777 * Set up separate handler for the DDB IPI, so that it doesn't 778 * stomp on a possibly corrupted stack. 779 * 780 * XXX overwriting the gate set in db_machine_init. 781 * Should rearrange the code so that it's set only once. 782 */ 783 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 784 UVM_KMF_WIRED); 785 cpu_init_tss(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 786 Xintrddbipi); 787 788 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 789 SDT_SYS386TSS, SEL_KPL, 0, 0); 790 ci->ci_gdt[GIPITSS_SEL].sd = sd; 791 792 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 793 GSEL(GIPITSS_SEL, SEL_KPL)); 794 #endif 795 } 796 #else 797 static void 798 cpu_set_tss_gates(struct cpu_info *ci) 799 { 800 801 } 802 #endif /* i386 */ 803 804 int 805 mp_cpu_start(struct cpu_info *ci, paddr_t target) 806 { 807 #if NLAPIC > 0 808 int error; 809 #endif 810 unsigned short dwordptr[2]; 811 812 /* 813 * Bootstrap code must be addressable in real mode 814 * and it must be page aligned. 815 */ 816 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 817 818 /* 819 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 820 */ 821 822 outb(IO_RTC, NVRAM_RESET); 823 outb(IO_RTC+1, NVRAM_RESET_JUMP); 824 825 /* 826 * "and the warm reset vector (DWORD based at 40:67) to point 827 * to the AP startup code ..." 828 */ 829 830 dwordptr[0] = 0; 831 dwordptr[1] = target >> 4; 832 833 memcpy((uint8_t *)(cmos_data_mapping + 0x467), dwordptr, 4); 834 835 #if NLAPIC > 0 836 /* 837 * ... prior to executing the following sequence:" 838 */ 839 840 if (ci->ci_flags & CPUF_AP) { 841 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 842 return error; 843 844 i8254_delay(10000); 845 846 if (cpu_feature & CPUID_APIC) { 847 848 if ((error = x86_ipi(target / PAGE_SIZE, 849 ci->ci_apicid, 850 LAPIC_DLMODE_STARTUP)) != 0) 851 return error; 852 i8254_delay(200); 853 854 if ((error = x86_ipi(target / PAGE_SIZE, 855 ci->ci_apicid, 856 LAPIC_DLMODE_STARTUP)) != 0) 857 return error; 858 i8254_delay(200); 859 } 860 } 861 #endif 862 return 0; 863 } 864 865 void 866 mp_cpu_start_cleanup(struct cpu_info *ci) 867 { 868 /* 869 * Ensure the NVRAM reset byte contains something vaguely sane. 870 */ 871 872 outb(IO_RTC, NVRAM_RESET); 873 outb(IO_RTC+1, NVRAM_RESET_RST); 874 } 875 876 #ifdef __x86_64__ 877 typedef void (vector)(void); 878 extern vector Xsyscall, Xsyscall32; 879 880 void 881 cpu_init_msrs(struct cpu_info *ci, bool full) 882 { 883 wrmsr(MSR_STAR, 884 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 885 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 886 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 887 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 888 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 889 890 if (full) { 891 wrmsr(MSR_FSBASE, 0); 892 wrmsr(MSR_GSBASE, (u_int64_t)ci); 893 wrmsr(MSR_KERNELGSBASE, 0); 894 } 895 896 if (cpu_feature & CPUID_NOX) 897 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 898 } 899 #endif /* __x86_64__ */ 900 901 /* XXX joerg restructure and restart CPUs individually */ 902 static bool 903 cpu_suspend(device_t dv) 904 { 905 struct cpu_softc *sc = device_private(dv); 906 struct cpu_info *ci = sc->sc_info; 907 int err; 908 909 if (ci->ci_flags & CPUF_PRIMARY) 910 return true; 911 if (ci->ci_data.cpu_idlelwp == NULL) 912 return true; 913 if ((ci->ci_flags & CPUF_PRESENT) == 0) 914 return true; 915 916 mutex_enter(&cpu_lock); 917 err = cpu_setonline(ci, false); 918 mutex_exit(&cpu_lock); 919 return err == 0; 920 } 921 922 static bool 923 cpu_resume(device_t dv) 924 { 925 struct cpu_softc *sc = device_private(dv); 926 struct cpu_info *ci = sc->sc_info; 927 int err; 928 929 if (ci->ci_flags & CPUF_PRIMARY) 930 return true; 931 if (ci->ci_data.cpu_idlelwp == NULL) 932 return true; 933 if ((ci->ci_flags & CPUF_PRESENT) == 0) 934 return true; 935 936 mutex_enter(&cpu_lock); 937 err = cpu_setonline(ci, true); 938 mutex_exit(&cpu_lock); 939 940 return err == 0; 941 } 942 943 void 944 cpu_get_tsc_freq(struct cpu_info *ci) 945 { 946 uint64_t last_tsc; 947 u_int junk[4]; 948 949 if (ci->ci_feature_flags & CPUID_TSC) { 950 /* Serialize. */ 951 x86_cpuid(0, junk); 952 last_tsc = rdtsc(); 953 i8254_delay(100000); 954 ci->ci_tsc_freq = (rdtsc() - last_tsc) * 10; 955 } 956 } 957
Indexes created Tue Sep 23 07:09:52 GMT 2025