cpu.c revision 1.144
1 /* $NetBSD: cpu.c,v 1.144 2018/01/07 16:10:16 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.144 2018/01/07 16:10:16 maxv Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 #include "opt_svs.h" 72 73 #include "lapic.h" 74 #include "ioapic.h" 75 76 #include <sys/param.h> 77 #include <sys/proc.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #if NLAPIC > 0 109 #include <machine/apicvar.h> 110 #include <machine/i82489reg.h> 111 #include <machine/i82489var.h> 112 #endif 113 114 #include <dev/ic/mc146818reg.h> 115 #include <i386/isa/nvram.h> 116 #include <dev/isa/isareg.h> 117 118 #include "tsc.h" 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static bool cpu_stop(device_t); 126 static bool cpu_suspend(device_t, const pmf_qual_t *); 127 static bool cpu_resume(device_t, const pmf_qual_t *); 128 static bool cpu_shutdown(device_t, int); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 #ifdef MULTIPROCESSOR 137 int mp_cpu_start(struct cpu_info *, paddr_t); 138 void mp_cpu_start_cleanup(struct cpu_info *); 139 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 140 mp_cpu_start_cleanup }; 141 #endif 142 143 144 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 145 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 160 struct cpu_info *cpu_info_list = &cpu_info_primary; 161 162 #ifdef i386 163 void cpu_set_tss_gates(struct cpu_info *); 164 #endif 165 166 static void cpu_init_idle_lwp(struct cpu_info *); 167 168 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits */ 169 /* [0] basic features cpuid.1:%edx 170 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 171 * [2] extended features cpuid:80000001:%edx 172 * [3] extended features cpuid:80000001:%ecx 173 * [4] VIA padlock features 174 * [5] structured extended features cpuid.7:%ebx 175 * [6] structured extended features cpuid.7:%ecx 176 */ 177 178 #ifdef MULTIPROCESSOR 179 bool x86_mp_online; 180 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 181 #endif 182 #if NLAPIC > 0 183 static vaddr_t cmos_data_mapping; 184 #endif 185 struct cpu_info *cpu_starting; 186 187 #ifdef MULTIPROCESSOR 188 void cpu_hatch(void *); 189 static void cpu_boot_secondary(struct cpu_info *ci); 190 static void cpu_start_secondary(struct cpu_info *ci); 191 #endif 192 #if NLAPIC > 0 193 static void cpu_copy_trampoline(paddr_t); 194 #endif 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 #if NLAPIC > 0 203 void 204 cpu_init_first(void) 205 { 206 207 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 208 209 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 210 if (cmos_data_mapping == 0) 211 panic("No KVA for page 0"); 212 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 213 pmap_update(pmap_kernel()); 214 } 215 #endif 216 217 static int 218 cpu_match(device_t parent, cfdata_t match, void *aux) 219 { 220 221 return 1; 222 } 223 224 #ifdef __HAVE_PCPU_AREA 225 void 226 cpu_pcpuarea_init(struct cpu_info *ci) 227 { 228 struct vm_page *pg; 229 size_t i, npages; 230 vaddr_t base, va; 231 paddr_t pa; 232 233 CTASSERT(sizeof(struct pcpu_entry) % PAGE_SIZE == 0); 234 235 npages = sizeof(struct pcpu_entry) / PAGE_SIZE; 236 base = (vaddr_t)&pcpuarea->ent[cpu_index(ci)]; 237 238 for (i = 0; i < npages; i++) { 239 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 240 if (pg == NULL) { 241 panic("failed to allocate pcpu PA"); 242 } 243 244 va = base + i * PAGE_SIZE; 245 pa = VM_PAGE_TO_PHYS(pg); 246 247 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 0); 248 } 249 250 pmap_update(pmap_kernel()); 251 } 252 #endif 253 254 static void 255 cpu_vm_init(struct cpu_info *ci) 256 { 257 int ncolors = 2, i; 258 259 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 260 struct x86_cache_info *cai; 261 int tcolors; 262 263 cai = &ci->ci_cinfo[i]; 264 265 tcolors = atop(cai->cai_totalsize); 266 switch(cai->cai_associativity) { 267 case 0xff: 268 tcolors = 1; /* fully associative */ 269 break; 270 case 0: 271 case 1: 272 break; 273 default: 274 tcolors /= cai->cai_associativity; 275 } 276 ncolors = max(ncolors, tcolors); 277 /* 278 * If the desired number of colors is not a power of 279 * two, it won't be good. Find the greatest power of 280 * two which is an even divisor of the number of colors, 281 * to preserve even coloring of pages. 282 */ 283 if (ncolors & (ncolors - 1) ) { 284 int try, picked = 1; 285 for (try = 1; try < ncolors; try *= 2) { 286 if (ncolors % try == 0) picked = try; 287 } 288 if (picked == 1) { 289 panic("desired number of cache colors %d is " 290 " > 1, but not even!", ncolors); 291 } 292 ncolors = picked; 293 } 294 } 295 296 /* 297 * Knowing the size of the largest cache on this CPU, potentially 298 * re-color our pages. 299 */ 300 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 301 uvm_page_recolor(ncolors); 302 303 pmap_tlb_cpu_init(ci); 304 #ifndef __HAVE_DIRECT_MAP 305 pmap_vpage_cpu_init(ci); 306 #endif 307 } 308 309 static void 310 cpu_attach(device_t parent, device_t self, void *aux) 311 { 312 struct cpu_softc *sc = device_private(self); 313 struct cpu_attach_args *caa = aux; 314 struct cpu_info *ci; 315 uintptr_t ptr; 316 #if NLAPIC > 0 317 int cpunum = caa->cpu_number; 318 #endif 319 static bool again; 320 321 sc->sc_dev = self; 322 323 if (ncpu == maxcpus) { 324 #ifndef _LP64 325 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 326 #else 327 aprint_error(": too many CPUs\n"); 328 #endif 329 return; 330 } 331 332 /* 333 * If we're an Application Processor, allocate a cpu_info 334 * structure, otherwise use the primary's. 335 */ 336 if (caa->cpu_role == CPU_ROLE_AP) { 337 if ((boothowto & RB_MD1) != 0) { 338 aprint_error(": multiprocessor boot disabled\n"); 339 if (!pmf_device_register(self, NULL, NULL)) 340 aprint_error_dev(self, 341 "couldn't establish power handler\n"); 342 return; 343 } 344 aprint_naive(": Application Processor\n"); 345 ptr = (uintptr_t)uvm_km_alloc(kernel_map, 346 sizeof(*ci) + CACHE_LINE_SIZE - 1, 0, 347 UVM_KMF_WIRED|UVM_KMF_ZERO); 348 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 349 ci->ci_curldt = -1; 350 } else { 351 aprint_naive(": %s Processor\n", 352 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 353 ci = &cpu_info_primary; 354 #if NLAPIC > 0 355 if (cpunum != lapic_cpu_number()) { 356 /* XXX should be done earlier. */ 357 uint32_t reg; 358 aprint_verbose("\n"); 359 aprint_verbose_dev(self, "running CPU at apic %d" 360 " instead of at expected %d", lapic_cpu_number(), 361 cpunum); 362 reg = lapic_readreg(LAPIC_ID); 363 lapic_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 364 (cpunum << LAPIC_ID_SHIFT)); 365 } 366 if (cpunum != lapic_cpu_number()) { 367 aprint_error_dev(self, "unable to reset apic id\n"); 368 } 369 #endif 370 } 371 372 ci->ci_self = ci; 373 sc->sc_info = ci; 374 ci->ci_dev = self; 375 ci->ci_acpiid = caa->cpu_id; 376 ci->ci_cpuid = caa->cpu_number; 377 ci->ci_func = caa->cpu_func; 378 aprint_normal("\n"); 379 380 /* Must be before mi_cpu_attach(). */ 381 cpu_vm_init(ci); 382 383 #ifdef SVS 384 cpu_svs_init(ci); 385 #endif 386 387 if (caa->cpu_role == CPU_ROLE_AP) { 388 int error; 389 390 error = mi_cpu_attach(ci); 391 if (error != 0) { 392 aprint_error_dev(self, 393 "mi_cpu_attach failed with %d\n", error); 394 return; 395 } 396 #ifdef __HAVE_PCPU_AREA 397 cpu_pcpuarea_init(ci); 398 #endif 399 cpu_init_tss(ci); 400 } else { 401 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 402 } 403 404 pmap_reference(pmap_kernel()); 405 ci->ci_pmap = pmap_kernel(); 406 ci->ci_tlbstate = TLBSTATE_STALE; 407 408 /* 409 * Boot processor may not be attached first, but the below 410 * must be done to allow booting other processors. 411 */ 412 if (!again) { 413 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 414 /* Basic init. */ 415 cpu_intr_init(ci); 416 cpu_get_tsc_freq(ci); 417 cpu_init(ci); 418 #ifdef i386 419 cpu_set_tss_gates(ci); 420 #endif 421 pmap_cpu_init_late(ci); 422 #if NLAPIC > 0 423 if (caa->cpu_role != CPU_ROLE_SP) { 424 /* Enable lapic. */ 425 lapic_enable(); 426 lapic_set_lvt(); 427 lapic_calibrate_timer(ci); 428 } 429 #endif 430 /* Make sure DELAY() is initialized. */ 431 DELAY(1); 432 again = true; 433 } 434 435 /* further PCB init done later. */ 436 437 switch (caa->cpu_role) { 438 case CPU_ROLE_SP: 439 atomic_or_32(&ci->ci_flags, CPUF_SP); 440 cpu_identify(ci); 441 x86_errata(); 442 x86_cpu_idle_init(); 443 break; 444 445 case CPU_ROLE_BP: 446 atomic_or_32(&ci->ci_flags, CPUF_BSP); 447 cpu_identify(ci); 448 x86_errata(); 449 x86_cpu_idle_init(); 450 break; 451 452 #ifdef MULTIPROCESSOR 453 case CPU_ROLE_AP: 454 /* 455 * report on an AP 456 */ 457 cpu_intr_init(ci); 458 gdt_alloc_cpu(ci); 459 #ifdef i386 460 cpu_set_tss_gates(ci); 461 #endif 462 pmap_cpu_init_late(ci); 463 cpu_start_secondary(ci); 464 if (ci->ci_flags & CPUF_PRESENT) { 465 struct cpu_info *tmp; 466 467 cpu_identify(ci); 468 tmp = cpu_info_list; 469 while (tmp->ci_next) 470 tmp = tmp->ci_next; 471 472 tmp->ci_next = ci; 473 } 474 break; 475 #endif 476 477 default: 478 panic("unknown processor type??\n"); 479 } 480 481 pat_init(ci); 482 483 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 484 aprint_error_dev(self, "couldn't establish power handler\n"); 485 486 #ifdef MULTIPROCESSOR 487 if (mp_verbose) { 488 struct lwp *l = ci->ci_data.cpu_idlelwp; 489 struct pcb *pcb = lwp_getpcb(l); 490 491 aprint_verbose_dev(self, 492 "idle lwp at %p, idle sp at %p\n", 493 l, 494 #ifdef i386 495 (void *)pcb->pcb_esp 496 #else 497 (void *)pcb->pcb_rsp 498 #endif 499 ); 500 } 501 #endif 502 503 /* 504 * Postpone the "cpufeaturebus" scan. 505 * It is safe to scan the pseudo-bus 506 * only after all CPUs have attached. 507 */ 508 (void)config_defer(self, cpu_defer); 509 } 510 511 static void 512 cpu_defer(device_t self) 513 { 514 cpu_rescan(self, NULL, NULL); 515 } 516 517 static int 518 cpu_rescan(device_t self, const char *ifattr, const int *locators) 519 { 520 struct cpu_softc *sc = device_private(self); 521 struct cpufeature_attach_args cfaa; 522 struct cpu_info *ci = sc->sc_info; 523 524 memset(&cfaa, 0, sizeof(cfaa)); 525 cfaa.ci = ci; 526 527 if (ifattr_match(ifattr, "cpufeaturebus")) { 528 if (ci->ci_frequency == NULL) { 529 cfaa.name = "frequency"; 530 ci->ci_frequency = config_found_ia(self, 531 "cpufeaturebus", &cfaa, NULL); 532 } 533 534 if (ci->ci_padlock == NULL) { 535 cfaa.name = "padlock"; 536 ci->ci_padlock = config_found_ia(self, 537 "cpufeaturebus", &cfaa, NULL); 538 } 539 540 if (ci->ci_temperature == NULL) { 541 cfaa.name = "temperature"; 542 ci->ci_temperature = config_found_ia(self, 543 "cpufeaturebus", &cfaa, NULL); 544 } 545 546 if (ci->ci_vm == NULL) { 547 cfaa.name = "vm"; 548 ci->ci_vm = config_found_ia(self, 549 "cpufeaturebus", &cfaa, NULL); 550 } 551 } 552 553 return 0; 554 } 555 556 static void 557 cpu_childdetached(device_t self, device_t child) 558 { 559 struct cpu_softc *sc = device_private(self); 560 struct cpu_info *ci = sc->sc_info; 561 562 if (ci->ci_frequency == child) 563 ci->ci_frequency = NULL; 564 565 if (ci->ci_padlock == child) 566 ci->ci_padlock = NULL; 567 568 if (ci->ci_temperature == child) 569 ci->ci_temperature = NULL; 570 571 if (ci->ci_vm == child) 572 ci->ci_vm = NULL; 573 } 574 575 /* 576 * Initialize the processor appropriately. 577 */ 578 579 void 580 cpu_init(struct cpu_info *ci) 581 { 582 extern int x86_fpu_save; 583 uint32_t cr4 = 0; 584 585 lcr0(rcr0() | CR0_WP); 586 587 /* 588 * On a P6 or above, enable global TLB caching if the 589 * hardware supports it. 590 */ 591 if (cpu_feature[0] & CPUID_PGE) 592 cr4 |= CR4_PGE; /* enable global TLB caching */ 593 594 /* 595 * If we have FXSAVE/FXRESTOR, use them. 596 */ 597 if (cpu_feature[0] & CPUID_FXSR) { 598 cr4 |= CR4_OSFXSR; 599 600 /* 601 * If we have SSE/SSE2, enable XMM exceptions. 602 */ 603 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 604 cr4 |= CR4_OSXMMEXCPT; 605 } 606 607 /* If xsave is supported, enable it */ 608 if (cpu_feature[1] & CPUID2_XSAVE) 609 cr4 |= CR4_OSXSAVE; 610 611 /* If SMEP is supported, enable it */ 612 if (cpu_feature[5] & CPUID_SEF_SMEP) 613 cr4 |= CR4_SMEP; 614 615 #ifdef amd64 616 /* If SMAP is supported, enable it */ 617 if (cpu_feature[5] & CPUID_SEF_SMAP) 618 cr4 |= CR4_SMAP; 619 #endif 620 621 if (cr4) { 622 cr4 |= rcr4(); 623 lcr4(cr4); 624 } 625 626 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 627 fpuinit_mxcsr_mask(); 628 } 629 630 /* If xsave is enabled, enable all fpu features */ 631 if (cr4 & CR4_OSXSAVE) 632 wrxcr(0, x86_xsave_features & XCR0_FPU); 633 634 #ifdef MTRR 635 /* 636 * On a P6 or above, initialize MTRR's if the hardware supports them. 637 */ 638 if (cpu_feature[0] & CPUID_MTRR) { 639 if ((ci->ci_flags & CPUF_AP) == 0) 640 i686_mtrr_init_first(); 641 mtrr_init_cpu(ci); 642 } 643 644 #ifdef i386 645 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 646 /* 647 * Must be a K6-2 Step >= 7 or a K6-III. 648 */ 649 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 650 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 651 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 652 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 653 mtrr_funcs = &k6_mtrr_funcs; 654 k6_mtrr_init_first(); 655 mtrr_init_cpu(ci); 656 } 657 } 658 } 659 #endif /* i386 */ 660 #endif /* MTRR */ 661 662 if (ci != &cpu_info_primary) { 663 /* Synchronize TSC again, and check for drift. */ 664 wbinvd(); 665 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 666 tsc_sync_ap(ci); 667 } else { 668 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 669 } 670 } 671 672 #ifdef MULTIPROCESSOR 673 void 674 cpu_boot_secondary_processors(void) 675 { 676 struct cpu_info *ci; 677 kcpuset_t *cpus; 678 u_long i; 679 680 /* Now that we know the number of CPUs, patch the text segment. */ 681 x86_patch(false); 682 683 kcpuset_create(&cpus, true); 684 kcpuset_set(cpus, cpu_index(curcpu())); 685 for (i = 0; i < maxcpus; i++) { 686 ci = cpu_lookup(i); 687 if (ci == NULL) 688 continue; 689 if (ci->ci_data.cpu_idlelwp == NULL) 690 continue; 691 if ((ci->ci_flags & CPUF_PRESENT) == 0) 692 continue; 693 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 694 continue; 695 cpu_boot_secondary(ci); 696 kcpuset_set(cpus, cpu_index(ci)); 697 } 698 while (!kcpuset_match(cpus, kcpuset_running)) 699 ; 700 kcpuset_destroy(cpus); 701 702 x86_mp_online = true; 703 704 /* Now that we know about the TSC, attach the timecounter. */ 705 tsc_tc_init(); 706 707 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 708 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 709 } 710 #endif 711 712 static void 713 cpu_init_idle_lwp(struct cpu_info *ci) 714 { 715 struct lwp *l = ci->ci_data.cpu_idlelwp; 716 struct pcb *pcb = lwp_getpcb(l); 717 718 pcb->pcb_cr0 = rcr0(); 719 } 720 721 void 722 cpu_init_idle_lwps(void) 723 { 724 struct cpu_info *ci; 725 u_long i; 726 727 for (i = 0; i < maxcpus; i++) { 728 ci = cpu_lookup(i); 729 if (ci == NULL) 730 continue; 731 if (ci->ci_data.cpu_idlelwp == NULL) 732 continue; 733 if ((ci->ci_flags & CPUF_PRESENT) == 0) 734 continue; 735 cpu_init_idle_lwp(ci); 736 } 737 } 738 739 #ifdef MULTIPROCESSOR 740 void 741 cpu_start_secondary(struct cpu_info *ci) 742 { 743 paddr_t mp_pdirpa; 744 u_long psl; 745 int i; 746 747 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 748 cpu_copy_trampoline(mp_pdirpa); 749 750 atomic_or_32(&ci->ci_flags, CPUF_AP); 751 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 752 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 753 return; 754 } 755 756 /* 757 * Wait for it to become ready. Setting cpu_starting opens the 758 * initial gate and allows the AP to start soft initialization. 759 */ 760 KASSERT(cpu_starting == NULL); 761 cpu_starting = ci; 762 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 763 i8254_delay(10); 764 } 765 766 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 767 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 768 #if defined(MPDEBUG) && defined(DDB) 769 printf("dropping into debugger; continue from here to resume boot\n"); 770 Debugger(); 771 #endif 772 } else { 773 /* 774 * Synchronize time stamp counters. Invalidate cache and do 775 * twice to try and minimize possible cache effects. Disable 776 * interrupts to try and rule out any external interference. 777 */ 778 psl = x86_read_psl(); 779 x86_disable_intr(); 780 wbinvd(); 781 tsc_sync_bp(ci); 782 x86_write_psl(psl); 783 } 784 785 CPU_START_CLEANUP(ci); 786 cpu_starting = NULL; 787 } 788 789 void 790 cpu_boot_secondary(struct cpu_info *ci) 791 { 792 int64_t drift; 793 u_long psl; 794 int i; 795 796 atomic_or_32(&ci->ci_flags, CPUF_GO); 797 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 798 i8254_delay(10); 799 } 800 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 801 aprint_error_dev(ci->ci_dev, "failed to start\n"); 802 #if defined(MPDEBUG) && defined(DDB) 803 printf("dropping into debugger; continue from here to resume boot\n"); 804 Debugger(); 805 #endif 806 } else { 807 /* Synchronize TSC again, check for drift. */ 808 drift = ci->ci_data.cpu_cc_skew; 809 psl = x86_read_psl(); 810 x86_disable_intr(); 811 wbinvd(); 812 tsc_sync_bp(ci); 813 x86_write_psl(psl); 814 drift -= ci->ci_data.cpu_cc_skew; 815 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 816 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 817 tsc_sync_drift(drift); 818 } 819 } 820 821 /* 822 * The CPU ends up here when it's ready to run. 823 * This is called from code in mptramp.s; at this point, we are running 824 * in the idle pcb/idle stack of the new CPU. When this function returns, 825 * this processor will enter the idle loop and start looking for work. 826 */ 827 void 828 cpu_hatch(void *v) 829 { 830 struct cpu_info *ci = (struct cpu_info *)v; 831 struct pcb *pcb; 832 int s, i; 833 834 cpu_init_msrs(ci, true); 835 cpu_probe(ci); 836 837 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 838 /* cpu_get_tsc_freq(ci); */ 839 840 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 841 842 /* 843 * Synchronize time stamp counters. Invalidate cache and do twice 844 * to try and minimize possible cache effects. Note that interrupts 845 * are off at this point. 846 */ 847 wbinvd(); 848 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 849 tsc_sync_ap(ci); 850 851 /* 852 * Wait to be brought online. Use 'monitor/mwait' if available, 853 * in order to make the TSC drift as much as possible. so that 854 * we can detect it later. If not available, try 'pause'. 855 * We'd like to use 'hlt', but we have interrupts off. 856 */ 857 while ((ci->ci_flags & CPUF_GO) == 0) { 858 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 859 x86_monitor(&ci->ci_flags, 0, 0); 860 if ((ci->ci_flags & CPUF_GO) != 0) { 861 continue; 862 } 863 x86_mwait(0, 0); 864 } else { 865 /* 866 * XXX The loop repetition count could be a lot higher, but 867 * XXX currently qemu emulator takes a _very_long_time_ to 868 * XXX execute the pause instruction. So for now, use a low 869 * XXX value to allow the cpu to hatch before timing out. 870 */ 871 for (i = 50; i != 0; i--) { 872 x86_pause(); 873 } 874 } 875 } 876 877 /* Because the text may have been patched in x86_patch(). */ 878 wbinvd(); 879 x86_flush(); 880 tlbflushg(); 881 882 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 883 884 #ifdef PAE 885 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 886 for (i = 0 ; i < PDP_SIZE; i++) { 887 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 888 } 889 lcr3(ci->ci_pae_l3_pdirpa); 890 #else 891 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 892 #endif 893 894 pcb = lwp_getpcb(curlwp); 895 pcb->pcb_cr3 = rcr3(); 896 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 897 lcr0(pcb->pcb_cr0); 898 899 cpu_init_idt(); 900 gdt_init_cpu(ci); 901 #if NLAPIC > 0 902 lapic_enable(); 903 lapic_set_lvt(); 904 lapic_initclocks(); 905 #endif 906 907 fpuinit(ci); 908 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 909 ltr(ci->ci_tss_sel); 910 911 cpu_init(ci); 912 cpu_get_tsc_freq(ci); 913 914 s = splhigh(); 915 lapic_write_tpri(0); 916 x86_enable_intr(); 917 splx(s); 918 x86_errata(); 919 920 aprint_debug_dev(ci->ci_dev, "running\n"); 921 922 idle_loop(NULL); 923 KASSERT(false); 924 } 925 #endif 926 927 #if defined(DDB) 928 929 #include <ddb/db_output.h> 930 #include <machine/db_machdep.h> 931 932 /* 933 * Dump CPU information from ddb. 934 */ 935 void 936 cpu_debug_dump(void) 937 { 938 struct cpu_info *ci; 939 CPU_INFO_ITERATOR cii; 940 941 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 942 for (CPU_INFO_FOREACH(cii, ci)) { 943 db_printf("%p %s %ld %x %x %10p %10p\n", 944 ci, 945 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 946 (long)ci->ci_cpuid, 947 ci->ci_flags, ci->ci_ipis, 948 ci->ci_curlwp, 949 ci->ci_fpcurlwp); 950 } 951 } 952 #endif 953 954 #if NLAPIC > 0 955 static void 956 cpu_copy_trampoline(paddr_t pdir_pa) 957 { 958 extern uint32_t nox_flag; 959 extern u_char cpu_spinup_trampoline[]; 960 extern u_char cpu_spinup_trampoline_end[]; 961 vaddr_t mp_trampoline_vaddr; 962 struct { 963 uint32_t large; 964 uint32_t nox; 965 uint32_t pdir; 966 } smp_data; 967 CTASSERT(sizeof(smp_data) == 3 * 4); 968 969 smp_data.large = (pmap_largepages != 0); 970 smp_data.nox = nox_flag; 971 smp_data.pdir = (uint32_t)(pdir_pa & 0xFFFFFFFF); 972 973 /* Enter the physical address */ 974 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 975 UVM_KMF_VAONLY); 976 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 977 VM_PROT_READ | VM_PROT_WRITE, 0); 978 pmap_update(pmap_kernel()); 979 980 /* Copy boot code */ 981 memcpy((void *)mp_trampoline_vaddr, 982 cpu_spinup_trampoline, 983 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 984 985 /* Copy smp_data at the end */ 986 memcpy((void *)(mp_trampoline_vaddr + PAGE_SIZE - sizeof(smp_data)), 987 &smp_data, sizeof(smp_data)); 988 989 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 990 pmap_update(pmap_kernel()); 991 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 992 } 993 #endif 994 995 #ifdef MULTIPROCESSOR 996 int 997 mp_cpu_start(struct cpu_info *ci, paddr_t target) 998 { 999 unsigned short dwordptr[2]; 1000 int error; 1001 1002 /* 1003 * Bootstrap code must be addressable in real mode 1004 * and it must be page aligned. 1005 */ 1006 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1007 1008 /* 1009 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1010 */ 1011 1012 outb(IO_RTC, NVRAM_RESET); 1013 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1014 1015 /* 1016 * "and the warm reset vector (DWORD based at 40:67) to point 1017 * to the AP startup code ..." 1018 */ 1019 1020 dwordptr[0] = 0; 1021 dwordptr[1] = target >> 4; 1022 1023 #if NLAPIC > 0 1024 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1025 #endif 1026 1027 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1028 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1029 return ENODEV; 1030 } 1031 1032 /* 1033 * ... prior to executing the following sequence:". We'll also add in 1034 * local cache flush, in case the BIOS has left the AP with its cache 1035 * disabled. It may not be able to cope with MP coherency. 1036 */ 1037 wbinvd(); 1038 1039 if (ci->ci_flags & CPUF_AP) { 1040 error = x86_ipi_init(ci->ci_cpuid); 1041 if (error != 0) { 1042 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1043 __func__); 1044 return error; 1045 } 1046 i8254_delay(10000); 1047 1048 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1049 if (error != 0) { 1050 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1051 __func__); 1052 return error; 1053 } 1054 i8254_delay(200); 1055 1056 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1057 if (error != 0) { 1058 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1059 __func__); 1060 return error; 1061 } 1062 i8254_delay(200); 1063 } 1064 1065 return 0; 1066 } 1067 1068 void 1069 mp_cpu_start_cleanup(struct cpu_info *ci) 1070 { 1071 /* 1072 * Ensure the NVRAM reset byte contains something vaguely sane. 1073 */ 1074 1075 outb(IO_RTC, NVRAM_RESET); 1076 outb(IO_RTC+1, NVRAM_RESET_RST); 1077 } 1078 #endif 1079 1080 #ifdef __x86_64__ 1081 typedef void (vector)(void); 1082 extern vector Xsyscall, Xsyscall32; 1083 #endif 1084 1085 void 1086 cpu_init_msrs(struct cpu_info *ci, bool full) 1087 { 1088 #ifdef __x86_64__ 1089 wrmsr(MSR_STAR, 1090 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1091 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1092 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1093 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1094 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_AC); 1095 1096 if (full) { 1097 wrmsr(MSR_FSBASE, 0); 1098 wrmsr(MSR_GSBASE, (uint64_t)ci); 1099 wrmsr(MSR_KERNELGSBASE, 0); 1100 } 1101 #endif /* __x86_64__ */ 1102 1103 if (cpu_feature[2] & CPUID_NOX) 1104 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1105 } 1106 1107 void 1108 cpu_offline_md(void) 1109 { 1110 int s; 1111 1112 s = splhigh(); 1113 fpusave_cpu(true); 1114 splx(s); 1115 } 1116 1117 /* XXX joerg restructure and restart CPUs individually */ 1118 static bool 1119 cpu_stop(device_t dv) 1120 { 1121 struct cpu_softc *sc = device_private(dv); 1122 struct cpu_info *ci = sc->sc_info; 1123 int err; 1124 1125 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1126 1127 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1128 return true; 1129 1130 if (ci->ci_data.cpu_idlelwp == NULL) 1131 return true; 1132 1133 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1134 1135 if (sc->sc_wasonline) { 1136 mutex_enter(&cpu_lock); 1137 err = cpu_setstate(ci, false); 1138 mutex_exit(&cpu_lock); 1139 1140 if (err != 0) 1141 return false; 1142 } 1143 1144 return true; 1145 } 1146 1147 static bool 1148 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1149 { 1150 struct cpu_softc *sc = device_private(dv); 1151 struct cpu_info *ci = sc->sc_info; 1152 1153 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1154 return true; 1155 else { 1156 cpufreq_suspend(ci); 1157 } 1158 1159 return cpu_stop(dv); 1160 } 1161 1162 static bool 1163 cpu_resume(device_t dv, const pmf_qual_t *qual) 1164 { 1165 struct cpu_softc *sc = device_private(dv); 1166 struct cpu_info *ci = sc->sc_info; 1167 int err = 0; 1168 1169 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1170 return true; 1171 1172 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1173 goto out; 1174 1175 if (ci->ci_data.cpu_idlelwp == NULL) 1176 goto out; 1177 1178 if (sc->sc_wasonline) { 1179 mutex_enter(&cpu_lock); 1180 err = cpu_setstate(ci, true); 1181 mutex_exit(&cpu_lock); 1182 } 1183 1184 out: 1185 if (err != 0) 1186 return false; 1187 1188 cpufreq_resume(ci); 1189 1190 return true; 1191 } 1192 1193 static bool 1194 cpu_shutdown(device_t dv, int how) 1195 { 1196 struct cpu_softc *sc = device_private(dv); 1197 struct cpu_info *ci = sc->sc_info; 1198 1199 if ((ci->ci_flags & CPUF_BSP) != 0) 1200 return false; 1201 1202 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1203 return true; 1204 1205 return cpu_stop(dv); 1206 } 1207 1208 void 1209 cpu_get_tsc_freq(struct cpu_info *ci) 1210 { 1211 uint64_t last_tsc; 1212 1213 if (cpu_hascounter()) { 1214 last_tsc = cpu_counter_serializing(); 1215 i8254_delay(100000); 1216 ci->ci_data.cpu_cc_freq = 1217 (cpu_counter_serializing() - last_tsc) * 10; 1218 } 1219 } 1220 1221 void 1222 x86_cpu_idle_mwait(void) 1223 { 1224 struct cpu_info *ci = curcpu(); 1225 1226 KASSERT(ci->ci_ilevel == IPL_NONE); 1227 1228 x86_monitor(&ci->ci_want_resched, 0, 0); 1229 if (__predict_false(ci->ci_want_resched)) { 1230 return; 1231 } 1232 x86_mwait(0, 0); 1233 } 1234 1235 void 1236 x86_cpu_idle_halt(void) 1237 { 1238 struct cpu_info *ci = curcpu(); 1239 1240 KASSERT(ci->ci_ilevel == IPL_NONE); 1241 1242 x86_disable_intr(); 1243 if (!__predict_false(ci->ci_want_resched)) { 1244 x86_stihlt(); 1245 } else { 1246 x86_enable_intr(); 1247 } 1248 } 1249 1250 /* 1251 * Loads pmap for the current CPU. 1252 */ 1253 void 1254 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1255 { 1256 #ifdef SVS 1257 svs_pdir_switch(pmap); 1258 #endif 1259 1260 #ifdef PAE 1261 struct cpu_info *ci = curcpu(); 1262 bool interrupts_enabled; 1263 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1264 int i; 1265 1266 /* 1267 * disable interrupts to block TLB shootdowns, which can reload cr3. 1268 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1269 * reload cr3. 1270 */ 1271 interrupts_enabled = (x86_read_flags() & PSL_I) != 0; 1272 if (interrupts_enabled) 1273 x86_disable_intr(); 1274 1275 for (i = 0 ; i < PDP_SIZE; i++) { 1276 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1277 } 1278 1279 if (interrupts_enabled) 1280 x86_enable_intr(); 1281 tlbflush(); 1282 #else /* PAE */ 1283 lcr3(pmap_pdirpa(pmap, 0)); 1284 #endif /* PAE */ 1285 } 1286 1287 /* 1288 * Notify all other cpus to halt. 1289 */ 1290 1291 void 1292 cpu_broadcast_halt(void) 1293 { 1294 x86_broadcast_ipi(X86_IPI_HALT); 1295 } 1296 1297 /* 1298 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1299 */ 1300 1301 void 1302 cpu_kick(struct cpu_info *ci) 1303 { 1304 x86_send_ipi(ci, 0); 1305 } 1306
Indexes created Thu Sep 25 08:09:54 GMT 2025