cpu.c revision 1.145
1 /* $NetBSD: cpu.c,v 1.145 2018/01/11 09:18:16 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.145 2018/01/11 09:18:16 msaitoh Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 #include "opt_svs.h" 72 73 #include "lapic.h" 74 #include "ioapic.h" 75 76 #include <sys/param.h> 77 #include <sys/proc.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #if NLAPIC > 0 109 #include <machine/apicvar.h> 110 #include <machine/i82489reg.h> 111 #include <machine/i82489var.h> 112 #endif 113 114 #include <dev/ic/mc146818reg.h> 115 #include <i386/isa/nvram.h> 116 #include <dev/isa/isareg.h> 117 118 #include "tsc.h" 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static bool cpu_stop(device_t); 126 static bool cpu_suspend(device_t, const pmf_qual_t *); 127 static bool cpu_resume(device_t, const pmf_qual_t *); 128 static bool cpu_shutdown(device_t, int); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 #ifdef MULTIPROCESSOR 137 int mp_cpu_start(struct cpu_info *, paddr_t); 138 void mp_cpu_start_cleanup(struct cpu_info *); 139 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 140 mp_cpu_start_cleanup }; 141 #endif 142 143 144 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 145 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 160 struct cpu_info *cpu_info_list = &cpu_info_primary; 161 162 #ifdef i386 163 void cpu_set_tss_gates(struct cpu_info *); 164 #endif 165 166 static void cpu_init_idle_lwp(struct cpu_info *); 167 168 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits */ 169 /* [0] basic features cpuid.1:%edx 170 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 171 * [2] extended features cpuid:80000001:%edx 172 * [3] extended features cpuid:80000001:%ecx 173 * [4] VIA padlock features 174 * [5] structured extended features cpuid.7:%ebx 175 * [6] structured extended features cpuid.7:%ecx 176 */ 177 178 #ifdef MULTIPROCESSOR 179 bool x86_mp_online; 180 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 181 #endif 182 #if NLAPIC > 0 183 static vaddr_t cmos_data_mapping; 184 #endif 185 struct cpu_info *cpu_starting; 186 187 #ifdef MULTIPROCESSOR 188 void cpu_hatch(void *); 189 static void cpu_boot_secondary(struct cpu_info *ci); 190 static void cpu_start_secondary(struct cpu_info *ci); 191 #endif 192 #if NLAPIC > 0 193 static void cpu_copy_trampoline(paddr_t); 194 #endif 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 #if NLAPIC > 0 203 void 204 cpu_init_first(void) 205 { 206 207 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 208 209 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 210 if (cmos_data_mapping == 0) 211 panic("No KVA for page 0"); 212 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 213 pmap_update(pmap_kernel()); 214 } 215 #endif 216 217 static int 218 cpu_match(device_t parent, cfdata_t match, void *aux) 219 { 220 221 return 1; 222 } 223 224 #ifdef __HAVE_PCPU_AREA 225 void 226 cpu_pcpuarea_init(struct cpu_info *ci) 227 { 228 struct vm_page *pg; 229 size_t i, npages; 230 vaddr_t base, va; 231 paddr_t pa; 232 233 CTASSERT(sizeof(struct pcpu_entry) % PAGE_SIZE == 0); 234 235 npages = sizeof(struct pcpu_entry) / PAGE_SIZE; 236 base = (vaddr_t)&pcpuarea->ent[cpu_index(ci)]; 237 238 for (i = 0; i < npages; i++) { 239 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 240 if (pg == NULL) { 241 panic("failed to allocate pcpu PA"); 242 } 243 244 va = base + i * PAGE_SIZE; 245 pa = VM_PAGE_TO_PHYS(pg); 246 247 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 0); 248 } 249 250 pmap_update(pmap_kernel()); 251 } 252 #endif 253 254 static void 255 cpu_vm_init(struct cpu_info *ci) 256 { 257 int ncolors = 2, i; 258 259 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 260 struct x86_cache_info *cai; 261 int tcolors; 262 263 cai = &ci->ci_cinfo[i]; 264 265 tcolors = atop(cai->cai_totalsize); 266 switch(cai->cai_associativity) { 267 case 0xff: 268 tcolors = 1; /* fully associative */ 269 break; 270 case 0: 271 case 1: 272 break; 273 default: 274 tcolors /= cai->cai_associativity; 275 } 276 ncolors = max(ncolors, tcolors); 277 /* 278 * If the desired number of colors is not a power of 279 * two, it won't be good. Find the greatest power of 280 * two which is an even divisor of the number of colors, 281 * to preserve even coloring of pages. 282 */ 283 if (ncolors & (ncolors - 1) ) { 284 int try, picked = 1; 285 for (try = 1; try < ncolors; try *= 2) { 286 if (ncolors % try == 0) picked = try; 287 } 288 if (picked == 1) { 289 panic("desired number of cache colors %d is " 290 " > 1, but not even!", ncolors); 291 } 292 ncolors = picked; 293 } 294 } 295 296 /* 297 * Knowing the size of the largest cache on this CPU, potentially 298 * re-color our pages. 299 */ 300 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 301 uvm_page_recolor(ncolors); 302 303 pmap_tlb_cpu_init(ci); 304 #ifndef __HAVE_DIRECT_MAP 305 pmap_vpage_cpu_init(ci); 306 #endif 307 } 308 309 static void 310 cpu_attach(device_t parent, device_t self, void *aux) 311 { 312 struct cpu_softc *sc = device_private(self); 313 struct cpu_attach_args *caa = aux; 314 struct cpu_info *ci; 315 uintptr_t ptr; 316 #if NLAPIC > 0 317 int cpunum = caa->cpu_number; 318 #endif 319 static bool again; 320 321 sc->sc_dev = self; 322 323 if (ncpu == maxcpus) { 324 #ifndef _LP64 325 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 326 #else 327 aprint_error(": too many CPUs\n"); 328 #endif 329 return; 330 } 331 332 /* 333 * If we're an Application Processor, allocate a cpu_info 334 * structure, otherwise use the primary's. 335 */ 336 if (caa->cpu_role == CPU_ROLE_AP) { 337 if ((boothowto & RB_MD1) != 0) { 338 aprint_error(": multiprocessor boot disabled\n"); 339 if (!pmf_device_register(self, NULL, NULL)) 340 aprint_error_dev(self, 341 "couldn't establish power handler\n"); 342 return; 343 } 344 aprint_naive(": Application Processor\n"); 345 ptr = (uintptr_t)uvm_km_alloc(kernel_map, 346 sizeof(*ci) + CACHE_LINE_SIZE - 1, 0, 347 UVM_KMF_WIRED|UVM_KMF_ZERO); 348 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 349 ci->ci_curldt = -1; 350 } else { 351 aprint_naive(": %s Processor\n", 352 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 353 ci = &cpu_info_primary; 354 #if NLAPIC > 0 355 if (cpunum != lapic_cpu_number()) { 356 /* XXX should be done earlier. */ 357 uint32_t reg; 358 aprint_verbose("\n"); 359 aprint_verbose_dev(self, "running CPU at apic %d" 360 " instead of at expected %d", lapic_cpu_number(), 361 cpunum); 362 reg = lapic_readreg(LAPIC_ID); 363 lapic_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 364 (cpunum << LAPIC_ID_SHIFT)); 365 } 366 if (cpunum != lapic_cpu_number()) { 367 aprint_error_dev(self, "unable to reset apic id\n"); 368 } 369 #endif 370 } 371 372 ci->ci_self = ci; 373 sc->sc_info = ci; 374 ci->ci_dev = self; 375 ci->ci_acpiid = caa->cpu_id; 376 ci->ci_cpuid = caa->cpu_number; 377 ci->ci_func = caa->cpu_func; 378 aprint_normal("\n"); 379 380 /* Must be before mi_cpu_attach(). */ 381 cpu_vm_init(ci); 382 383 #ifdef SVS 384 cpu_svs_init(ci); 385 #endif 386 387 if (caa->cpu_role == CPU_ROLE_AP) { 388 int error; 389 390 error = mi_cpu_attach(ci); 391 if (error != 0) { 392 aprint_error_dev(self, 393 "mi_cpu_attach failed with %d\n", error); 394 return; 395 } 396 #ifdef __HAVE_PCPU_AREA 397 cpu_pcpuarea_init(ci); 398 #endif 399 cpu_init_tss(ci); 400 } else { 401 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 402 } 403 404 pmap_reference(pmap_kernel()); 405 ci->ci_pmap = pmap_kernel(); 406 ci->ci_tlbstate = TLBSTATE_STALE; 407 408 /* 409 * Boot processor may not be attached first, but the below 410 * must be done to allow booting other processors. 411 */ 412 if (!again) { 413 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 414 /* Basic init. */ 415 cpu_intr_init(ci); 416 cpu_get_tsc_freq(ci); 417 cpu_init(ci); 418 #ifdef i386 419 cpu_set_tss_gates(ci); 420 #endif 421 pmap_cpu_init_late(ci); 422 #if NLAPIC > 0 423 if (caa->cpu_role != CPU_ROLE_SP) { 424 /* Enable lapic. */ 425 lapic_enable(); 426 lapic_set_lvt(); 427 lapic_calibrate_timer(ci); 428 } 429 #endif 430 /* Make sure DELAY() is initialized. */ 431 DELAY(1); 432 again = true; 433 } 434 435 /* further PCB init done later. */ 436 437 switch (caa->cpu_role) { 438 case CPU_ROLE_SP: 439 atomic_or_32(&ci->ci_flags, CPUF_SP); 440 cpu_identify(ci); 441 x86_errata(); 442 x86_cpu_idle_init(); 443 break; 444 445 case CPU_ROLE_BP: 446 atomic_or_32(&ci->ci_flags, CPUF_BSP); 447 cpu_identify(ci); 448 x86_errata(); 449 x86_cpu_idle_init(); 450 break; 451 452 #ifdef MULTIPROCESSOR 453 case CPU_ROLE_AP: 454 /* 455 * report on an AP 456 */ 457 cpu_intr_init(ci); 458 gdt_alloc_cpu(ci); 459 #ifdef i386 460 cpu_set_tss_gates(ci); 461 #endif 462 pmap_cpu_init_late(ci); 463 cpu_start_secondary(ci); 464 if (ci->ci_flags & CPUF_PRESENT) { 465 struct cpu_info *tmp; 466 467 cpu_identify(ci); 468 tmp = cpu_info_list; 469 while (tmp->ci_next) 470 tmp = tmp->ci_next; 471 472 tmp->ci_next = ci; 473 } 474 break; 475 #endif 476 477 default: 478 panic("unknown processor type??\n"); 479 } 480 481 pat_init(ci); 482 483 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 484 aprint_error_dev(self, "couldn't establish power handler\n"); 485 486 #ifdef MULTIPROCESSOR 487 if (mp_verbose) { 488 struct lwp *l = ci->ci_data.cpu_idlelwp; 489 struct pcb *pcb = lwp_getpcb(l); 490 491 aprint_verbose_dev(self, 492 "idle lwp at %p, idle sp at %p\n", 493 l, 494 #ifdef i386 495 (void *)pcb->pcb_esp 496 #else 497 (void *)pcb->pcb_rsp 498 #endif 499 ); 500 } 501 #endif 502 503 /* 504 * Postpone the "cpufeaturebus" scan. 505 * It is safe to scan the pseudo-bus 506 * only after all CPUs have attached. 507 */ 508 (void)config_defer(self, cpu_defer); 509 } 510 511 static void 512 cpu_defer(device_t self) 513 { 514 cpu_rescan(self, NULL, NULL); 515 } 516 517 static int 518 cpu_rescan(device_t self, const char *ifattr, const int *locators) 519 { 520 struct cpu_softc *sc = device_private(self); 521 struct cpufeature_attach_args cfaa; 522 struct cpu_info *ci = sc->sc_info; 523 524 memset(&cfaa, 0, sizeof(cfaa)); 525 cfaa.ci = ci; 526 527 if (ifattr_match(ifattr, "cpufeaturebus")) { 528 if (ci->ci_frequency == NULL) { 529 cfaa.name = "frequency"; 530 ci->ci_frequency = config_found_ia(self, 531 "cpufeaturebus", &cfaa, NULL); 532 } 533 534 if (ci->ci_padlock == NULL) { 535 cfaa.name = "padlock"; 536 ci->ci_padlock = config_found_ia(self, 537 "cpufeaturebus", &cfaa, NULL); 538 } 539 540 if (ci->ci_temperature == NULL) { 541 cfaa.name = "temperature"; 542 ci->ci_temperature = config_found_ia(self, 543 "cpufeaturebus", &cfaa, NULL); 544 } 545 546 if (ci->ci_vm == NULL) { 547 cfaa.name = "vm"; 548 ci->ci_vm = config_found_ia(self, 549 "cpufeaturebus", &cfaa, NULL); 550 } 551 } 552 553 return 0; 554 } 555 556 static void 557 cpu_childdetached(device_t self, device_t child) 558 { 559 struct cpu_softc *sc = device_private(self); 560 struct cpu_info *ci = sc->sc_info; 561 562 if (ci->ci_frequency == child) 563 ci->ci_frequency = NULL; 564 565 if (ci->ci_padlock == child) 566 ci->ci_padlock = NULL; 567 568 if (ci->ci_temperature == child) 569 ci->ci_temperature = NULL; 570 571 if (ci->ci_vm == child) 572 ci->ci_vm = NULL; 573 } 574 575 /* 576 * Initialize the processor appropriately. 577 */ 578 579 void 580 cpu_init(struct cpu_info *ci) 581 { 582 extern int x86_fpu_save; 583 uint32_t cr4 = 0; 584 585 lcr0(rcr0() | CR0_WP); 586 587 /* 588 * On a P6 or above, enable global TLB caching if the 589 * hardware supports it. 590 */ 591 if (cpu_feature[0] & CPUID_PGE) 592 cr4 |= CR4_PGE; /* enable global TLB caching */ 593 594 /* 595 * If we have FXSAVE/FXRESTOR, use them. 596 */ 597 if (cpu_feature[0] & CPUID_FXSR) { 598 cr4 |= CR4_OSFXSR; 599 600 /* 601 * If we have SSE/SSE2, enable XMM exceptions. 602 */ 603 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 604 cr4 |= CR4_OSXMMEXCPT; 605 } 606 607 /* If xsave is supported, enable it */ 608 if (cpu_feature[1] & CPUID2_XSAVE) 609 cr4 |= CR4_OSXSAVE; 610 611 /* If SMEP is supported, enable it */ 612 if (cpu_feature[5] & CPUID_SEF_SMEP) 613 cr4 |= CR4_SMEP; 614 615 #ifdef amd64 616 /* If SMAP is supported, enable it */ 617 if (cpu_feature[5] & CPUID_SEF_SMAP) 618 cr4 |= CR4_SMAP; 619 #endif 620 621 if (cr4) { 622 cr4 |= rcr4(); 623 lcr4(cr4); 624 } 625 626 /* 627 * Changing CR4 register may change cpuid values. For example, setting 628 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in 629 * ci_feat_val[1], so update it. 630 * XXX Other than ci_feat_val[1] might be changed. 631 */ 632 if (cpuid_level >= 1) { 633 u_int descs[4]; 634 635 x86_cpuid(1, descs); 636 ci->ci_feat_val[1] = descs[2]; 637 } 638 639 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 640 fpuinit_mxcsr_mask(); 641 } 642 643 /* If xsave is enabled, enable all fpu features */ 644 if (cr4 & CR4_OSXSAVE) 645 wrxcr(0, x86_xsave_features & XCR0_FPU); 646 647 #ifdef MTRR 648 /* 649 * On a P6 or above, initialize MTRR's if the hardware supports them. 650 */ 651 if (cpu_feature[0] & CPUID_MTRR) { 652 if ((ci->ci_flags & CPUF_AP) == 0) 653 i686_mtrr_init_first(); 654 mtrr_init_cpu(ci); 655 } 656 657 #ifdef i386 658 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 659 /* 660 * Must be a K6-2 Step >= 7 or a K6-III. 661 */ 662 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 663 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 664 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 665 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 666 mtrr_funcs = &k6_mtrr_funcs; 667 k6_mtrr_init_first(); 668 mtrr_init_cpu(ci); 669 } 670 } 671 } 672 #endif /* i386 */ 673 #endif /* MTRR */ 674 675 if (ci != &cpu_info_primary) { 676 /* Synchronize TSC again, and check for drift. */ 677 wbinvd(); 678 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 679 tsc_sync_ap(ci); 680 } else { 681 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 682 } 683 } 684 685 #ifdef MULTIPROCESSOR 686 void 687 cpu_boot_secondary_processors(void) 688 { 689 struct cpu_info *ci; 690 kcpuset_t *cpus; 691 u_long i; 692 693 /* Now that we know the number of CPUs, patch the text segment. */ 694 x86_patch(false); 695 696 kcpuset_create(&cpus, true); 697 kcpuset_set(cpus, cpu_index(curcpu())); 698 for (i = 0; i < maxcpus; i++) { 699 ci = cpu_lookup(i); 700 if (ci == NULL) 701 continue; 702 if (ci->ci_data.cpu_idlelwp == NULL) 703 continue; 704 if ((ci->ci_flags & CPUF_PRESENT) == 0) 705 continue; 706 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 707 continue; 708 cpu_boot_secondary(ci); 709 kcpuset_set(cpus, cpu_index(ci)); 710 } 711 while (!kcpuset_match(cpus, kcpuset_running)) 712 ; 713 kcpuset_destroy(cpus); 714 715 x86_mp_online = true; 716 717 /* Now that we know about the TSC, attach the timecounter. */ 718 tsc_tc_init(); 719 720 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 721 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 722 } 723 #endif 724 725 static void 726 cpu_init_idle_lwp(struct cpu_info *ci) 727 { 728 struct lwp *l = ci->ci_data.cpu_idlelwp; 729 struct pcb *pcb = lwp_getpcb(l); 730 731 pcb->pcb_cr0 = rcr0(); 732 } 733 734 void 735 cpu_init_idle_lwps(void) 736 { 737 struct cpu_info *ci; 738 u_long i; 739 740 for (i = 0; i < maxcpus; i++) { 741 ci = cpu_lookup(i); 742 if (ci == NULL) 743 continue; 744 if (ci->ci_data.cpu_idlelwp == NULL) 745 continue; 746 if ((ci->ci_flags & CPUF_PRESENT) == 0) 747 continue; 748 cpu_init_idle_lwp(ci); 749 } 750 } 751 752 #ifdef MULTIPROCESSOR 753 void 754 cpu_start_secondary(struct cpu_info *ci) 755 { 756 paddr_t mp_pdirpa; 757 u_long psl; 758 int i; 759 760 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 761 cpu_copy_trampoline(mp_pdirpa); 762 763 atomic_or_32(&ci->ci_flags, CPUF_AP); 764 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 765 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 766 return; 767 } 768 769 /* 770 * Wait for it to become ready. Setting cpu_starting opens the 771 * initial gate and allows the AP to start soft initialization. 772 */ 773 KASSERT(cpu_starting == NULL); 774 cpu_starting = ci; 775 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 776 i8254_delay(10); 777 } 778 779 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 780 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 781 #if defined(MPDEBUG) && defined(DDB) 782 printf("dropping into debugger; continue from here to resume boot\n"); 783 Debugger(); 784 #endif 785 } else { 786 /* 787 * Synchronize time stamp counters. Invalidate cache and do 788 * twice to try and minimize possible cache effects. Disable 789 * interrupts to try and rule out any external interference. 790 */ 791 psl = x86_read_psl(); 792 x86_disable_intr(); 793 wbinvd(); 794 tsc_sync_bp(ci); 795 x86_write_psl(psl); 796 } 797 798 CPU_START_CLEANUP(ci); 799 cpu_starting = NULL; 800 } 801 802 void 803 cpu_boot_secondary(struct cpu_info *ci) 804 { 805 int64_t drift; 806 u_long psl; 807 int i; 808 809 atomic_or_32(&ci->ci_flags, CPUF_GO); 810 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 811 i8254_delay(10); 812 } 813 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 814 aprint_error_dev(ci->ci_dev, "failed to start\n"); 815 #if defined(MPDEBUG) && defined(DDB) 816 printf("dropping into debugger; continue from here to resume boot\n"); 817 Debugger(); 818 #endif 819 } else { 820 /* Synchronize TSC again, check for drift. */ 821 drift = ci->ci_data.cpu_cc_skew; 822 psl = x86_read_psl(); 823 x86_disable_intr(); 824 wbinvd(); 825 tsc_sync_bp(ci); 826 x86_write_psl(psl); 827 drift -= ci->ci_data.cpu_cc_skew; 828 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 829 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 830 tsc_sync_drift(drift); 831 } 832 } 833 834 /* 835 * The CPU ends up here when it's ready to run. 836 * This is called from code in mptramp.s; at this point, we are running 837 * in the idle pcb/idle stack of the new CPU. When this function returns, 838 * this processor will enter the idle loop and start looking for work. 839 */ 840 void 841 cpu_hatch(void *v) 842 { 843 struct cpu_info *ci = (struct cpu_info *)v; 844 struct pcb *pcb; 845 int s, i; 846 847 cpu_init_msrs(ci, true); 848 cpu_probe(ci); 849 850 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 851 /* cpu_get_tsc_freq(ci); */ 852 853 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 854 855 /* 856 * Synchronize time stamp counters. Invalidate cache and do twice 857 * to try and minimize possible cache effects. Note that interrupts 858 * are off at this point. 859 */ 860 wbinvd(); 861 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 862 tsc_sync_ap(ci); 863 864 /* 865 * Wait to be brought online. Use 'monitor/mwait' if available, 866 * in order to make the TSC drift as much as possible. so that 867 * we can detect it later. If not available, try 'pause'. 868 * We'd like to use 'hlt', but we have interrupts off. 869 */ 870 while ((ci->ci_flags & CPUF_GO) == 0) { 871 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 872 x86_monitor(&ci->ci_flags, 0, 0); 873 if ((ci->ci_flags & CPUF_GO) != 0) { 874 continue; 875 } 876 x86_mwait(0, 0); 877 } else { 878 /* 879 * XXX The loop repetition count could be a lot higher, but 880 * XXX currently qemu emulator takes a _very_long_time_ to 881 * XXX execute the pause instruction. So for now, use a low 882 * XXX value to allow the cpu to hatch before timing out. 883 */ 884 for (i = 50; i != 0; i--) { 885 x86_pause(); 886 } 887 } 888 } 889 890 /* Because the text may have been patched in x86_patch(). */ 891 wbinvd(); 892 x86_flush(); 893 tlbflushg(); 894 895 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 896 897 #ifdef PAE 898 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 899 for (i = 0 ; i < PDP_SIZE; i++) { 900 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 901 } 902 lcr3(ci->ci_pae_l3_pdirpa); 903 #else 904 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 905 #endif 906 907 pcb = lwp_getpcb(curlwp); 908 pcb->pcb_cr3 = rcr3(); 909 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 910 lcr0(pcb->pcb_cr0); 911 912 cpu_init_idt(); 913 gdt_init_cpu(ci); 914 #if NLAPIC > 0 915 lapic_enable(); 916 lapic_set_lvt(); 917 lapic_initclocks(); 918 #endif 919 920 fpuinit(ci); 921 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 922 ltr(ci->ci_tss_sel); 923 924 cpu_init(ci); 925 cpu_get_tsc_freq(ci); 926 927 s = splhigh(); 928 lapic_write_tpri(0); 929 x86_enable_intr(); 930 splx(s); 931 x86_errata(); 932 933 aprint_debug_dev(ci->ci_dev, "running\n"); 934 935 idle_loop(NULL); 936 KASSERT(false); 937 } 938 #endif 939 940 #if defined(DDB) 941 942 #include <ddb/db_output.h> 943 #include <machine/db_machdep.h> 944 945 /* 946 * Dump CPU information from ddb. 947 */ 948 void 949 cpu_debug_dump(void) 950 { 951 struct cpu_info *ci; 952 CPU_INFO_ITERATOR cii; 953 954 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 955 for (CPU_INFO_FOREACH(cii, ci)) { 956 db_printf("%p %s %ld %x %x %10p %10p\n", 957 ci, 958 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 959 (long)ci->ci_cpuid, 960 ci->ci_flags, ci->ci_ipis, 961 ci->ci_curlwp, 962 ci->ci_fpcurlwp); 963 } 964 } 965 #endif 966 967 #if NLAPIC > 0 968 static void 969 cpu_copy_trampoline(paddr_t pdir_pa) 970 { 971 extern uint32_t nox_flag; 972 extern u_char cpu_spinup_trampoline[]; 973 extern u_char cpu_spinup_trampoline_end[]; 974 vaddr_t mp_trampoline_vaddr; 975 struct { 976 uint32_t large; 977 uint32_t nox; 978 uint32_t pdir; 979 } smp_data; 980 CTASSERT(sizeof(smp_data) == 3 * 4); 981 982 smp_data.large = (pmap_largepages != 0); 983 smp_data.nox = nox_flag; 984 smp_data.pdir = (uint32_t)(pdir_pa & 0xFFFFFFFF); 985 986 /* Enter the physical address */ 987 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 988 UVM_KMF_VAONLY); 989 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 990 VM_PROT_READ | VM_PROT_WRITE, 0); 991 pmap_update(pmap_kernel()); 992 993 /* Copy boot code */ 994 memcpy((void *)mp_trampoline_vaddr, 995 cpu_spinup_trampoline, 996 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 997 998 /* Copy smp_data at the end */ 999 memcpy((void *)(mp_trampoline_vaddr + PAGE_SIZE - sizeof(smp_data)), 1000 &smp_data, sizeof(smp_data)); 1001 1002 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 1003 pmap_update(pmap_kernel()); 1004 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 1005 } 1006 #endif 1007 1008 #ifdef MULTIPROCESSOR 1009 int 1010 mp_cpu_start(struct cpu_info *ci, paddr_t target) 1011 { 1012 unsigned short dwordptr[2]; 1013 int error; 1014 1015 /* 1016 * Bootstrap code must be addressable in real mode 1017 * and it must be page aligned. 1018 */ 1019 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1020 1021 /* 1022 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1023 */ 1024 1025 outb(IO_RTC, NVRAM_RESET); 1026 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1027 1028 /* 1029 * "and the warm reset vector (DWORD based at 40:67) to point 1030 * to the AP startup code ..." 1031 */ 1032 1033 dwordptr[0] = 0; 1034 dwordptr[1] = target >> 4; 1035 1036 #if NLAPIC > 0 1037 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1038 #endif 1039 1040 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1041 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1042 return ENODEV; 1043 } 1044 1045 /* 1046 * ... prior to executing the following sequence:". We'll also add in 1047 * local cache flush, in case the BIOS has left the AP with its cache 1048 * disabled. It may not be able to cope with MP coherency. 1049 */ 1050 wbinvd(); 1051 1052 if (ci->ci_flags & CPUF_AP) { 1053 error = x86_ipi_init(ci->ci_cpuid); 1054 if (error != 0) { 1055 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1056 __func__); 1057 return error; 1058 } 1059 i8254_delay(10000); 1060 1061 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1062 if (error != 0) { 1063 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1064 __func__); 1065 return error; 1066 } 1067 i8254_delay(200); 1068 1069 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1070 if (error != 0) { 1071 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1072 __func__); 1073 return error; 1074 } 1075 i8254_delay(200); 1076 } 1077 1078 return 0; 1079 } 1080 1081 void 1082 mp_cpu_start_cleanup(struct cpu_info *ci) 1083 { 1084 /* 1085 * Ensure the NVRAM reset byte contains something vaguely sane. 1086 */ 1087 1088 outb(IO_RTC, NVRAM_RESET); 1089 outb(IO_RTC+1, NVRAM_RESET_RST); 1090 } 1091 #endif 1092 1093 #ifdef __x86_64__ 1094 typedef void (vector)(void); 1095 extern vector Xsyscall, Xsyscall32; 1096 #endif 1097 1098 void 1099 cpu_init_msrs(struct cpu_info *ci, bool full) 1100 { 1101 #ifdef __x86_64__ 1102 wrmsr(MSR_STAR, 1103 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1104 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1105 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1106 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1107 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_AC); 1108 1109 if (full) { 1110 wrmsr(MSR_FSBASE, 0); 1111 wrmsr(MSR_GSBASE, (uint64_t)ci); 1112 wrmsr(MSR_KERNELGSBASE, 0); 1113 } 1114 #endif /* __x86_64__ */ 1115 1116 if (cpu_feature[2] & CPUID_NOX) 1117 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1118 } 1119 1120 void 1121 cpu_offline_md(void) 1122 { 1123 int s; 1124 1125 s = splhigh(); 1126 fpusave_cpu(true); 1127 splx(s); 1128 } 1129 1130 /* XXX joerg restructure and restart CPUs individually */ 1131 static bool 1132 cpu_stop(device_t dv) 1133 { 1134 struct cpu_softc *sc = device_private(dv); 1135 struct cpu_info *ci = sc->sc_info; 1136 int err; 1137 1138 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1139 1140 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1141 return true; 1142 1143 if (ci->ci_data.cpu_idlelwp == NULL) 1144 return true; 1145 1146 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1147 1148 if (sc->sc_wasonline) { 1149 mutex_enter(&cpu_lock); 1150 err = cpu_setstate(ci, false); 1151 mutex_exit(&cpu_lock); 1152 1153 if (err != 0) 1154 return false; 1155 } 1156 1157 return true; 1158 } 1159 1160 static bool 1161 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1162 { 1163 struct cpu_softc *sc = device_private(dv); 1164 struct cpu_info *ci = sc->sc_info; 1165 1166 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1167 return true; 1168 else { 1169 cpufreq_suspend(ci); 1170 } 1171 1172 return cpu_stop(dv); 1173 } 1174 1175 static bool 1176 cpu_resume(device_t dv, const pmf_qual_t *qual) 1177 { 1178 struct cpu_softc *sc = device_private(dv); 1179 struct cpu_info *ci = sc->sc_info; 1180 int err = 0; 1181 1182 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1183 return true; 1184 1185 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1186 goto out; 1187 1188 if (ci->ci_data.cpu_idlelwp == NULL) 1189 goto out; 1190 1191 if (sc->sc_wasonline) { 1192 mutex_enter(&cpu_lock); 1193 err = cpu_setstate(ci, true); 1194 mutex_exit(&cpu_lock); 1195 } 1196 1197 out: 1198 if (err != 0) 1199 return false; 1200 1201 cpufreq_resume(ci); 1202 1203 return true; 1204 } 1205 1206 static bool 1207 cpu_shutdown(device_t dv, int how) 1208 { 1209 struct cpu_softc *sc = device_private(dv); 1210 struct cpu_info *ci = sc->sc_info; 1211 1212 if ((ci->ci_flags & CPUF_BSP) != 0) 1213 return false; 1214 1215 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1216 return true; 1217 1218 return cpu_stop(dv); 1219 } 1220 1221 void 1222 cpu_get_tsc_freq(struct cpu_info *ci) 1223 { 1224 uint64_t last_tsc; 1225 1226 if (cpu_hascounter()) { 1227 last_tsc = cpu_counter_serializing(); 1228 i8254_delay(100000); 1229 ci->ci_data.cpu_cc_freq = 1230 (cpu_counter_serializing() - last_tsc) * 10; 1231 } 1232 } 1233 1234 void 1235 x86_cpu_idle_mwait(void) 1236 { 1237 struct cpu_info *ci = curcpu(); 1238 1239 KASSERT(ci->ci_ilevel == IPL_NONE); 1240 1241 x86_monitor(&ci->ci_want_resched, 0, 0); 1242 if (__predict_false(ci->ci_want_resched)) { 1243 return; 1244 } 1245 x86_mwait(0, 0); 1246 } 1247 1248 void 1249 x86_cpu_idle_halt(void) 1250 { 1251 struct cpu_info *ci = curcpu(); 1252 1253 KASSERT(ci->ci_ilevel == IPL_NONE); 1254 1255 x86_disable_intr(); 1256 if (!__predict_false(ci->ci_want_resched)) { 1257 x86_stihlt(); 1258 } else { 1259 x86_enable_intr(); 1260 } 1261 } 1262 1263 /* 1264 * Loads pmap for the current CPU. 1265 */ 1266 void 1267 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1268 { 1269 #ifdef SVS 1270 svs_pdir_switch(pmap); 1271 #endif 1272 1273 #ifdef PAE 1274 struct cpu_info *ci = curcpu(); 1275 bool interrupts_enabled; 1276 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1277 int i; 1278 1279 /* 1280 * disable interrupts to block TLB shootdowns, which can reload cr3. 1281 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1282 * reload cr3. 1283 */ 1284 interrupts_enabled = (x86_read_flags() & PSL_I) != 0; 1285 if (interrupts_enabled) 1286 x86_disable_intr(); 1287 1288 for (i = 0 ; i < PDP_SIZE; i++) { 1289 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1290 } 1291 1292 if (interrupts_enabled) 1293 x86_enable_intr(); 1294 tlbflush(); 1295 #else /* PAE */ 1296 lcr3(pmap_pdirpa(pmap, 0)); 1297 #endif /* PAE */ 1298 } 1299 1300 /* 1301 * Notify all other cpus to halt. 1302 */ 1303 1304 void 1305 cpu_broadcast_halt(void) 1306 { 1307 x86_broadcast_ipi(X86_IPI_HALT); 1308 } 1309 1310 /* 1311 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1312 */ 1313 1314 void 1315 cpu_kick(struct cpu_info *ci) 1316 { 1317 x86_send_ipi(ci, 0); 1318 } 1319
Indexes created Tue Sep 23 22:09:46 GMT 2025