cpu.c revision 1.149
1 /* $NetBSD: cpu.c,v 1.149 2018/02/22 13:27:18 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.149 2018/02/22 13:27:18 maxv Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 #include "opt_svs.h" 72 73 #include "lapic.h" 74 #include "ioapic.h" 75 76 #include <sys/param.h> 77 #include <sys/proc.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #if NLAPIC > 0 109 #include <machine/apicvar.h> 110 #include <machine/i82489reg.h> 111 #include <machine/i82489var.h> 112 #endif 113 114 #include <dev/ic/mc146818reg.h> 115 #include <i386/isa/nvram.h> 116 #include <dev/isa/isareg.h> 117 118 #include "tsc.h" 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static bool cpu_stop(device_t); 126 static bool cpu_suspend(device_t, const pmf_qual_t *); 127 static bool cpu_resume(device_t, const pmf_qual_t *); 128 static bool cpu_shutdown(device_t, int); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 #ifdef MULTIPROCESSOR 137 int mp_cpu_start(struct cpu_info *, paddr_t); 138 void mp_cpu_start_cleanup(struct cpu_info *); 139 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 140 mp_cpu_start_cleanup }; 141 #endif 142 143 144 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 145 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 160 struct cpu_info *cpu_info_list = &cpu_info_primary; 161 162 #ifdef i386 163 void cpu_set_tss_gates(struct cpu_info *); 164 #endif 165 166 static void cpu_init_idle_lwp(struct cpu_info *); 167 168 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits */ 169 /* [0] basic features cpuid.1:%edx 170 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 171 * [2] extended features cpuid:80000001:%edx 172 * [3] extended features cpuid:80000001:%ecx 173 * [4] VIA padlock features 174 * [5] structured extended features cpuid.7:%ebx 175 * [6] structured extended features cpuid.7:%ecx 176 */ 177 178 #ifdef MULTIPROCESSOR 179 bool x86_mp_online; 180 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 181 #endif 182 #if NLAPIC > 0 183 static vaddr_t cmos_data_mapping; 184 #endif 185 struct cpu_info *cpu_starting; 186 187 #ifdef MULTIPROCESSOR 188 void cpu_hatch(void *); 189 static void cpu_boot_secondary(struct cpu_info *ci); 190 static void cpu_start_secondary(struct cpu_info *ci); 191 #endif 192 #if NLAPIC > 0 193 static void cpu_copy_trampoline(paddr_t); 194 #endif 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 #if NLAPIC > 0 203 void 204 cpu_init_first(void) 205 { 206 207 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 208 209 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 210 if (cmos_data_mapping == 0) 211 panic("No KVA for page 0"); 212 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 213 pmap_update(pmap_kernel()); 214 } 215 #endif 216 217 static int 218 cpu_match(device_t parent, cfdata_t match, void *aux) 219 { 220 221 return 1; 222 } 223 224 #ifdef __HAVE_PCPU_AREA 225 void 226 cpu_pcpuarea_init(struct cpu_info *ci) 227 { 228 struct vm_page *pg; 229 size_t i, npages; 230 vaddr_t base, va; 231 paddr_t pa; 232 233 CTASSERT(sizeof(struct pcpu_entry) % PAGE_SIZE == 0); 234 235 npages = sizeof(struct pcpu_entry) / PAGE_SIZE; 236 base = (vaddr_t)&pcpuarea->ent[cpu_index(ci)]; 237 238 for (i = 0; i < npages; i++) { 239 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 240 if (pg == NULL) { 241 panic("failed to allocate pcpu PA"); 242 } 243 244 va = base + i * PAGE_SIZE; 245 pa = VM_PAGE_TO_PHYS(pg); 246 247 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 0); 248 } 249 250 pmap_update(pmap_kernel()); 251 } 252 #endif 253 254 static void 255 cpu_vm_init(struct cpu_info *ci) 256 { 257 int ncolors = 2, i; 258 259 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 260 struct x86_cache_info *cai; 261 int tcolors; 262 263 cai = &ci->ci_cinfo[i]; 264 265 tcolors = atop(cai->cai_totalsize); 266 switch(cai->cai_associativity) { 267 case 0xff: 268 tcolors = 1; /* fully associative */ 269 break; 270 case 0: 271 case 1: 272 break; 273 default: 274 tcolors /= cai->cai_associativity; 275 } 276 ncolors = max(ncolors, tcolors); 277 /* 278 * If the desired number of colors is not a power of 279 * two, it won't be good. Find the greatest power of 280 * two which is an even divisor of the number of colors, 281 * to preserve even coloring of pages. 282 */ 283 if (ncolors & (ncolors - 1) ) { 284 int try, picked = 1; 285 for (try = 1; try < ncolors; try *= 2) { 286 if (ncolors % try == 0) picked = try; 287 } 288 if (picked == 1) { 289 panic("desired number of cache colors %d is " 290 " > 1, but not even!", ncolors); 291 } 292 ncolors = picked; 293 } 294 } 295 296 /* 297 * Knowing the size of the largest cache on this CPU, potentially 298 * re-color our pages. 299 */ 300 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 301 uvm_page_recolor(ncolors); 302 303 pmap_tlb_cpu_init(ci); 304 #ifndef __HAVE_DIRECT_MAP 305 pmap_vpage_cpu_init(ci); 306 #endif 307 } 308 309 static void 310 cpu_attach(device_t parent, device_t self, void *aux) 311 { 312 struct cpu_softc *sc = device_private(self); 313 struct cpu_attach_args *caa = aux; 314 struct cpu_info *ci; 315 uintptr_t ptr; 316 #if NLAPIC > 0 317 int cpunum = caa->cpu_number; 318 #endif 319 static bool again; 320 321 sc->sc_dev = self; 322 323 if (ncpu == maxcpus) { 324 #ifndef _LP64 325 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 326 #else 327 aprint_error(": too many CPUs\n"); 328 #endif 329 return; 330 } 331 332 /* 333 * If we're an Application Processor, allocate a cpu_info 334 * structure, otherwise use the primary's. 335 */ 336 if (caa->cpu_role == CPU_ROLE_AP) { 337 if ((boothowto & RB_MD1) != 0) { 338 aprint_error(": multiprocessor boot disabled\n"); 339 if (!pmf_device_register(self, NULL, NULL)) 340 aprint_error_dev(self, 341 "couldn't establish power handler\n"); 342 return; 343 } 344 aprint_naive(": Application Processor\n"); 345 ptr = (uintptr_t)uvm_km_alloc(kernel_map, 346 sizeof(*ci) + CACHE_LINE_SIZE - 1, 0, 347 UVM_KMF_WIRED|UVM_KMF_ZERO); 348 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 349 ci->ci_curldt = -1; 350 } else { 351 aprint_naive(": %s Processor\n", 352 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 353 ci = &cpu_info_primary; 354 #if NLAPIC > 0 355 if (cpunum != lapic_cpu_number()) { 356 /* XXX should be done earlier. */ 357 uint32_t reg; 358 aprint_verbose("\n"); 359 aprint_verbose_dev(self, "running CPU at apic %d" 360 " instead of at expected %d", lapic_cpu_number(), 361 cpunum); 362 reg = lapic_readreg(LAPIC_ID); 363 lapic_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 364 (cpunum << LAPIC_ID_SHIFT)); 365 } 366 if (cpunum != lapic_cpu_number()) { 367 aprint_error_dev(self, "unable to reset apic id\n"); 368 } 369 #endif 370 } 371 372 ci->ci_self = ci; 373 sc->sc_info = ci; 374 ci->ci_dev = self; 375 ci->ci_acpiid = caa->cpu_id; 376 ci->ci_cpuid = caa->cpu_number; 377 ci->ci_func = caa->cpu_func; 378 aprint_normal("\n"); 379 380 /* Must be before mi_cpu_attach(). */ 381 cpu_vm_init(ci); 382 383 if (caa->cpu_role == CPU_ROLE_AP) { 384 int error; 385 386 error = mi_cpu_attach(ci); 387 if (error != 0) { 388 aprint_error_dev(self, 389 "mi_cpu_attach failed with %d\n", error); 390 return; 391 } 392 #ifdef __HAVE_PCPU_AREA 393 cpu_pcpuarea_init(ci); 394 #endif 395 cpu_init_tss(ci); 396 } else { 397 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 398 } 399 400 #ifdef SVS 401 cpu_svs_init(ci); 402 #endif 403 404 pmap_reference(pmap_kernel()); 405 ci->ci_pmap = pmap_kernel(); 406 ci->ci_tlbstate = TLBSTATE_STALE; 407 408 /* 409 * Boot processor may not be attached first, but the below 410 * must be done to allow booting other processors. 411 */ 412 if (!again) { 413 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 414 /* Basic init. */ 415 cpu_intr_init(ci); 416 cpu_get_tsc_freq(ci); 417 cpu_init(ci); 418 #ifdef i386 419 cpu_set_tss_gates(ci); 420 #endif 421 pmap_cpu_init_late(ci); 422 #if NLAPIC > 0 423 if (caa->cpu_role != CPU_ROLE_SP) { 424 /* Enable lapic. */ 425 lapic_enable(); 426 lapic_set_lvt(); 427 lapic_calibrate_timer(ci); 428 } 429 #endif 430 /* Make sure DELAY() is initialized. */ 431 DELAY(1); 432 again = true; 433 } 434 435 /* further PCB init done later. */ 436 437 switch (caa->cpu_role) { 438 case CPU_ROLE_SP: 439 atomic_or_32(&ci->ci_flags, CPUF_SP); 440 cpu_identify(ci); 441 x86_errata(); 442 x86_cpu_idle_init(); 443 break; 444 445 case CPU_ROLE_BP: 446 atomic_or_32(&ci->ci_flags, CPUF_BSP); 447 cpu_identify(ci); 448 x86_errata(); 449 x86_cpu_idle_init(); 450 break; 451 452 #ifdef MULTIPROCESSOR 453 case CPU_ROLE_AP: 454 /* 455 * report on an AP 456 */ 457 cpu_intr_init(ci); 458 gdt_alloc_cpu(ci); 459 #ifdef i386 460 cpu_set_tss_gates(ci); 461 #endif 462 pmap_cpu_init_late(ci); 463 cpu_start_secondary(ci); 464 if (ci->ci_flags & CPUF_PRESENT) { 465 struct cpu_info *tmp; 466 467 cpu_identify(ci); 468 tmp = cpu_info_list; 469 while (tmp->ci_next) 470 tmp = tmp->ci_next; 471 472 tmp->ci_next = ci; 473 } 474 break; 475 #endif 476 477 default: 478 panic("unknown processor type??\n"); 479 } 480 481 pat_init(ci); 482 483 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 484 aprint_error_dev(self, "couldn't establish power handler\n"); 485 486 #ifdef MULTIPROCESSOR 487 if (mp_verbose) { 488 struct lwp *l = ci->ci_data.cpu_idlelwp; 489 struct pcb *pcb = lwp_getpcb(l); 490 491 aprint_verbose_dev(self, 492 "idle lwp at %p, idle sp at %p\n", 493 l, 494 #ifdef i386 495 (void *)pcb->pcb_esp 496 #else 497 (void *)pcb->pcb_rsp 498 #endif 499 ); 500 } 501 #endif 502 503 /* 504 * Postpone the "cpufeaturebus" scan. 505 * It is safe to scan the pseudo-bus 506 * only after all CPUs have attached. 507 */ 508 (void)config_defer(self, cpu_defer); 509 } 510 511 static void 512 cpu_defer(device_t self) 513 { 514 cpu_rescan(self, NULL, NULL); 515 } 516 517 static int 518 cpu_rescan(device_t self, const char *ifattr, const int *locators) 519 { 520 struct cpu_softc *sc = device_private(self); 521 struct cpufeature_attach_args cfaa; 522 struct cpu_info *ci = sc->sc_info; 523 524 memset(&cfaa, 0, sizeof(cfaa)); 525 cfaa.ci = ci; 526 527 if (ifattr_match(ifattr, "cpufeaturebus")) { 528 if (ci->ci_frequency == NULL) { 529 cfaa.name = "frequency"; 530 ci->ci_frequency = config_found_ia(self, 531 "cpufeaturebus", &cfaa, NULL); 532 } 533 534 if (ci->ci_padlock == NULL) { 535 cfaa.name = "padlock"; 536 ci->ci_padlock = config_found_ia(self, 537 "cpufeaturebus", &cfaa, NULL); 538 } 539 540 if (ci->ci_temperature == NULL) { 541 cfaa.name = "temperature"; 542 ci->ci_temperature = config_found_ia(self, 543 "cpufeaturebus", &cfaa, NULL); 544 } 545 546 if (ci->ci_vm == NULL) { 547 cfaa.name = "vm"; 548 ci->ci_vm = config_found_ia(self, 549 "cpufeaturebus", &cfaa, NULL); 550 } 551 } 552 553 return 0; 554 } 555 556 static void 557 cpu_childdetached(device_t self, device_t child) 558 { 559 struct cpu_softc *sc = device_private(self); 560 struct cpu_info *ci = sc->sc_info; 561 562 if (ci->ci_frequency == child) 563 ci->ci_frequency = NULL; 564 565 if (ci->ci_padlock == child) 566 ci->ci_padlock = NULL; 567 568 if (ci->ci_temperature == child) 569 ci->ci_temperature = NULL; 570 571 if (ci->ci_vm == child) 572 ci->ci_vm = NULL; 573 } 574 575 /* 576 * Initialize the processor appropriately. 577 */ 578 579 void 580 cpu_init(struct cpu_info *ci) 581 { 582 extern int x86_fpu_save; 583 uint32_t cr4 = 0; 584 585 lcr0(rcr0() | CR0_WP); 586 587 /* 588 * On a P6 or above, enable global TLB caching if the 589 * hardware supports it. 590 */ 591 if (cpu_feature[0] & CPUID_PGE) 592 #ifdef SVS 593 if (!svs_enabled) 594 #endif 595 cr4 |= CR4_PGE; /* enable global TLB caching */ 596 597 /* 598 * If we have FXSAVE/FXRESTOR, use them. 599 */ 600 if (cpu_feature[0] & CPUID_FXSR) { 601 cr4 |= CR4_OSFXSR; 602 603 /* 604 * If we have SSE/SSE2, enable XMM exceptions. 605 */ 606 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 607 cr4 |= CR4_OSXMMEXCPT; 608 } 609 610 /* If xsave is supported, enable it */ 611 if (cpu_feature[1] & CPUID2_XSAVE) 612 cr4 |= CR4_OSXSAVE; 613 614 /* If SMEP is supported, enable it */ 615 if (cpu_feature[5] & CPUID_SEF_SMEP) 616 cr4 |= CR4_SMEP; 617 618 /* If SMAP is supported, enable it */ 619 if (cpu_feature[5] & CPUID_SEF_SMAP) 620 cr4 |= CR4_SMAP; 621 622 if (cr4) { 623 cr4 |= rcr4(); 624 lcr4(cr4); 625 } 626 627 /* 628 * Changing CR4 register may change cpuid values. For example, setting 629 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in 630 * ci_feat_val[1], so update it. 631 * XXX Other than ci_feat_val[1] might be changed. 632 */ 633 if (cpuid_level >= 1) { 634 u_int descs[4]; 635 636 x86_cpuid(1, descs); 637 ci->ci_feat_val[1] = descs[2]; 638 } 639 640 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 641 fpuinit_mxcsr_mask(); 642 } 643 644 /* If xsave is enabled, enable all fpu features */ 645 if (cr4 & CR4_OSXSAVE) 646 wrxcr(0, x86_xsave_features & XCR0_FPU); 647 648 #ifdef MTRR 649 /* 650 * On a P6 or above, initialize MTRR's if the hardware supports them. 651 */ 652 if (cpu_feature[0] & CPUID_MTRR) { 653 if ((ci->ci_flags & CPUF_AP) == 0) 654 i686_mtrr_init_first(); 655 mtrr_init_cpu(ci); 656 } 657 658 #ifdef i386 659 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 660 /* 661 * Must be a K6-2 Step >= 7 or a K6-III. 662 */ 663 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 664 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 665 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 666 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 667 mtrr_funcs = &k6_mtrr_funcs; 668 k6_mtrr_init_first(); 669 mtrr_init_cpu(ci); 670 } 671 } 672 } 673 #endif /* i386 */ 674 #endif /* MTRR */ 675 676 if (ci != &cpu_info_primary) { 677 /* Synchronize TSC again, and check for drift. */ 678 wbinvd(); 679 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 680 tsc_sync_ap(ci); 681 } else { 682 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 683 } 684 } 685 686 #ifdef MULTIPROCESSOR 687 void 688 cpu_boot_secondary_processors(void) 689 { 690 struct cpu_info *ci; 691 kcpuset_t *cpus; 692 u_long i; 693 694 /* Now that we know the number of CPUs, patch the text segment. */ 695 x86_patch(false); 696 697 kcpuset_create(&cpus, true); 698 kcpuset_set(cpus, cpu_index(curcpu())); 699 for (i = 0; i < maxcpus; i++) { 700 ci = cpu_lookup(i); 701 if (ci == NULL) 702 continue; 703 if (ci->ci_data.cpu_idlelwp == NULL) 704 continue; 705 if ((ci->ci_flags & CPUF_PRESENT) == 0) 706 continue; 707 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 708 continue; 709 cpu_boot_secondary(ci); 710 kcpuset_set(cpus, cpu_index(ci)); 711 } 712 while (!kcpuset_match(cpus, kcpuset_running)) 713 ; 714 kcpuset_destroy(cpus); 715 716 x86_mp_online = true; 717 718 /* Now that we know about the TSC, attach the timecounter. */ 719 tsc_tc_init(); 720 721 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 722 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 723 } 724 #endif 725 726 static void 727 cpu_init_idle_lwp(struct cpu_info *ci) 728 { 729 struct lwp *l = ci->ci_data.cpu_idlelwp; 730 struct pcb *pcb = lwp_getpcb(l); 731 732 pcb->pcb_cr0 = rcr0(); 733 } 734 735 void 736 cpu_init_idle_lwps(void) 737 { 738 struct cpu_info *ci; 739 u_long i; 740 741 for (i = 0; i < maxcpus; i++) { 742 ci = cpu_lookup(i); 743 if (ci == NULL) 744 continue; 745 if (ci->ci_data.cpu_idlelwp == NULL) 746 continue; 747 if ((ci->ci_flags & CPUF_PRESENT) == 0) 748 continue; 749 cpu_init_idle_lwp(ci); 750 } 751 } 752 753 #ifdef MULTIPROCESSOR 754 void 755 cpu_start_secondary(struct cpu_info *ci) 756 { 757 paddr_t mp_pdirpa; 758 u_long psl; 759 int i; 760 761 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 762 cpu_copy_trampoline(mp_pdirpa); 763 764 atomic_or_32(&ci->ci_flags, CPUF_AP); 765 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 766 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 767 return; 768 } 769 770 /* 771 * Wait for it to become ready. Setting cpu_starting opens the 772 * initial gate and allows the AP to start soft initialization. 773 */ 774 KASSERT(cpu_starting == NULL); 775 cpu_starting = ci; 776 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 777 i8254_delay(10); 778 } 779 780 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 781 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 782 #if defined(MPDEBUG) && defined(DDB) 783 printf("dropping into debugger; continue from here to resume boot\n"); 784 Debugger(); 785 #endif 786 } else { 787 /* 788 * Synchronize time stamp counters. Invalidate cache and do 789 * twice to try and minimize possible cache effects. Disable 790 * interrupts to try and rule out any external interference. 791 */ 792 psl = x86_read_psl(); 793 x86_disable_intr(); 794 wbinvd(); 795 tsc_sync_bp(ci); 796 x86_write_psl(psl); 797 } 798 799 CPU_START_CLEANUP(ci); 800 cpu_starting = NULL; 801 } 802 803 void 804 cpu_boot_secondary(struct cpu_info *ci) 805 { 806 int64_t drift; 807 u_long psl; 808 int i; 809 810 atomic_or_32(&ci->ci_flags, CPUF_GO); 811 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 812 i8254_delay(10); 813 } 814 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 815 aprint_error_dev(ci->ci_dev, "failed to start\n"); 816 #if defined(MPDEBUG) && defined(DDB) 817 printf("dropping into debugger; continue from here to resume boot\n"); 818 Debugger(); 819 #endif 820 } else { 821 /* Synchronize TSC again, check for drift. */ 822 drift = ci->ci_data.cpu_cc_skew; 823 psl = x86_read_psl(); 824 x86_disable_intr(); 825 wbinvd(); 826 tsc_sync_bp(ci); 827 x86_write_psl(psl); 828 drift -= ci->ci_data.cpu_cc_skew; 829 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 830 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 831 tsc_sync_drift(drift); 832 } 833 } 834 835 /* 836 * The CPU ends up here when it's ready to run. 837 * This is called from code in mptramp.s; at this point, we are running 838 * in the idle pcb/idle stack of the new CPU. When this function returns, 839 * this processor will enter the idle loop and start looking for work. 840 */ 841 void 842 cpu_hatch(void *v) 843 { 844 struct cpu_info *ci = (struct cpu_info *)v; 845 struct pcb *pcb; 846 int s, i; 847 848 cpu_init_msrs(ci, true); 849 cpu_probe(ci); 850 851 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 852 /* cpu_get_tsc_freq(ci); */ 853 854 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 855 856 /* 857 * Synchronize time stamp counters. Invalidate cache and do twice 858 * to try and minimize possible cache effects. Note that interrupts 859 * are off at this point. 860 */ 861 wbinvd(); 862 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 863 tsc_sync_ap(ci); 864 865 /* 866 * Wait to be brought online. Use 'monitor/mwait' if available, 867 * in order to make the TSC drift as much as possible. so that 868 * we can detect it later. If not available, try 'pause'. 869 * We'd like to use 'hlt', but we have interrupts off. 870 */ 871 while ((ci->ci_flags & CPUF_GO) == 0) { 872 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 873 x86_monitor(&ci->ci_flags, 0, 0); 874 if ((ci->ci_flags & CPUF_GO) != 0) { 875 continue; 876 } 877 x86_mwait(0, 0); 878 } else { 879 /* 880 * XXX The loop repetition count could be a lot higher, but 881 * XXX currently qemu emulator takes a _very_long_time_ to 882 * XXX execute the pause instruction. So for now, use a low 883 * XXX value to allow the cpu to hatch before timing out. 884 */ 885 for (i = 50; i != 0; i--) { 886 x86_pause(); 887 } 888 } 889 } 890 891 /* Because the text may have been patched in x86_patch(). */ 892 wbinvd(); 893 x86_flush(); 894 tlbflushg(); 895 896 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 897 898 #ifdef PAE 899 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 900 for (i = 0 ; i < PDP_SIZE; i++) { 901 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 902 } 903 lcr3(ci->ci_pae_l3_pdirpa); 904 #else 905 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 906 #endif 907 908 pcb = lwp_getpcb(curlwp); 909 pcb->pcb_cr3 = rcr3(); 910 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 911 lcr0(pcb->pcb_cr0); 912 913 cpu_init_idt(); 914 gdt_init_cpu(ci); 915 #if NLAPIC > 0 916 lapic_enable(); 917 lapic_set_lvt(); 918 lapic_initclocks(); 919 #endif 920 921 fpuinit(ci); 922 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 923 ltr(ci->ci_tss_sel); 924 925 cpu_init(ci); 926 cpu_get_tsc_freq(ci); 927 928 s = splhigh(); 929 lapic_write_tpri(0); 930 x86_enable_intr(); 931 splx(s); 932 x86_errata(); 933 934 aprint_debug_dev(ci->ci_dev, "running\n"); 935 936 idle_loop(NULL); 937 KASSERT(false); 938 } 939 #endif 940 941 #if defined(DDB) 942 943 #include <ddb/db_output.h> 944 #include <machine/db_machdep.h> 945 946 /* 947 * Dump CPU information from ddb. 948 */ 949 void 950 cpu_debug_dump(void) 951 { 952 struct cpu_info *ci; 953 CPU_INFO_ITERATOR cii; 954 955 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 956 for (CPU_INFO_FOREACH(cii, ci)) { 957 db_printf("%p %s %ld %x %x %10p %10p\n", 958 ci, 959 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 960 (long)ci->ci_cpuid, 961 ci->ci_flags, ci->ci_ipis, 962 ci->ci_curlwp, 963 ci->ci_fpcurlwp); 964 } 965 } 966 #endif 967 968 #if NLAPIC > 0 969 static void 970 cpu_copy_trampoline(paddr_t pdir_pa) 971 { 972 extern uint32_t nox_flag; 973 extern u_char cpu_spinup_trampoline[]; 974 extern u_char cpu_spinup_trampoline_end[]; 975 vaddr_t mp_trampoline_vaddr; 976 struct { 977 uint32_t large; 978 uint32_t nox; 979 uint32_t pdir; 980 } smp_data; 981 CTASSERT(sizeof(smp_data) == 3 * 4); 982 983 smp_data.large = (pmap_largepages != 0); 984 smp_data.nox = nox_flag; 985 smp_data.pdir = (uint32_t)(pdir_pa & 0xFFFFFFFF); 986 987 /* Enter the physical address */ 988 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 989 UVM_KMF_VAONLY); 990 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 991 VM_PROT_READ | VM_PROT_WRITE, 0); 992 pmap_update(pmap_kernel()); 993 994 /* Copy boot code */ 995 memcpy((void *)mp_trampoline_vaddr, 996 cpu_spinup_trampoline, 997 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 998 999 /* Copy smp_data at the end */ 1000 memcpy((void *)(mp_trampoline_vaddr + PAGE_SIZE - sizeof(smp_data)), 1001 &smp_data, sizeof(smp_data)); 1002 1003 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 1004 pmap_update(pmap_kernel()); 1005 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 1006 } 1007 #endif 1008 1009 #ifdef MULTIPROCESSOR 1010 int 1011 mp_cpu_start(struct cpu_info *ci, paddr_t target) 1012 { 1013 unsigned short dwordptr[2]; 1014 int error; 1015 1016 /* 1017 * Bootstrap code must be addressable in real mode 1018 * and it must be page aligned. 1019 */ 1020 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1021 1022 /* 1023 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1024 */ 1025 1026 outb(IO_RTC, NVRAM_RESET); 1027 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1028 1029 /* 1030 * "and the warm reset vector (DWORD based at 40:67) to point 1031 * to the AP startup code ..." 1032 */ 1033 1034 dwordptr[0] = 0; 1035 dwordptr[1] = target >> 4; 1036 1037 #if NLAPIC > 0 1038 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1039 #endif 1040 1041 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1042 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1043 return ENODEV; 1044 } 1045 1046 /* 1047 * ... prior to executing the following sequence:". We'll also add in 1048 * local cache flush, in case the BIOS has left the AP with its cache 1049 * disabled. It may not be able to cope with MP coherency. 1050 */ 1051 wbinvd(); 1052 1053 if (ci->ci_flags & CPUF_AP) { 1054 error = x86_ipi_init(ci->ci_cpuid); 1055 if (error != 0) { 1056 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1057 __func__); 1058 return error; 1059 } 1060 i8254_delay(10000); 1061 1062 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1063 if (error != 0) { 1064 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1065 __func__); 1066 return error; 1067 } 1068 i8254_delay(200); 1069 1070 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1071 if (error != 0) { 1072 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1073 __func__); 1074 return error; 1075 } 1076 i8254_delay(200); 1077 } 1078 1079 return 0; 1080 } 1081 1082 void 1083 mp_cpu_start_cleanup(struct cpu_info *ci) 1084 { 1085 /* 1086 * Ensure the NVRAM reset byte contains something vaguely sane. 1087 */ 1088 1089 outb(IO_RTC, NVRAM_RESET); 1090 outb(IO_RTC+1, NVRAM_RESET_RST); 1091 } 1092 #endif 1093 1094 #ifdef __x86_64__ 1095 typedef void (vector)(void); 1096 extern vector Xsyscall, Xsyscall32, Xsyscall_svs; 1097 #endif 1098 1099 void 1100 cpu_init_msrs(struct cpu_info *ci, bool full) 1101 { 1102 #ifdef __x86_64__ 1103 wrmsr(MSR_STAR, 1104 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1105 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1106 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1107 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1108 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_AC); 1109 1110 #ifdef SVS 1111 if (svs_enabled) 1112 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall_svs); 1113 #endif 1114 1115 if (full) { 1116 wrmsr(MSR_FSBASE, 0); 1117 wrmsr(MSR_GSBASE, (uint64_t)ci); 1118 wrmsr(MSR_KERNELGSBASE, 0); 1119 } 1120 #endif /* __x86_64__ */ 1121 1122 if (cpu_feature[2] & CPUID_NOX) 1123 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1124 } 1125 1126 void 1127 cpu_offline_md(void) 1128 { 1129 int s; 1130 1131 s = splhigh(); 1132 fpusave_cpu(true); 1133 splx(s); 1134 } 1135 1136 /* XXX joerg restructure and restart CPUs individually */ 1137 static bool 1138 cpu_stop(device_t dv) 1139 { 1140 struct cpu_softc *sc = device_private(dv); 1141 struct cpu_info *ci = sc->sc_info; 1142 int err; 1143 1144 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1145 1146 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1147 return true; 1148 1149 if (ci->ci_data.cpu_idlelwp == NULL) 1150 return true; 1151 1152 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1153 1154 if (sc->sc_wasonline) { 1155 mutex_enter(&cpu_lock); 1156 err = cpu_setstate(ci, false); 1157 mutex_exit(&cpu_lock); 1158 1159 if (err != 0) 1160 return false; 1161 } 1162 1163 return true; 1164 } 1165 1166 static bool 1167 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1168 { 1169 struct cpu_softc *sc = device_private(dv); 1170 struct cpu_info *ci = sc->sc_info; 1171 1172 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1173 return true; 1174 else { 1175 cpufreq_suspend(ci); 1176 } 1177 1178 return cpu_stop(dv); 1179 } 1180 1181 static bool 1182 cpu_resume(device_t dv, const pmf_qual_t *qual) 1183 { 1184 struct cpu_softc *sc = device_private(dv); 1185 struct cpu_info *ci = sc->sc_info; 1186 int err = 0; 1187 1188 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1189 return true; 1190 1191 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1192 goto out; 1193 1194 if (ci->ci_data.cpu_idlelwp == NULL) 1195 goto out; 1196 1197 if (sc->sc_wasonline) { 1198 mutex_enter(&cpu_lock); 1199 err = cpu_setstate(ci, true); 1200 mutex_exit(&cpu_lock); 1201 } 1202 1203 out: 1204 if (err != 0) 1205 return false; 1206 1207 cpufreq_resume(ci); 1208 1209 return true; 1210 } 1211 1212 static bool 1213 cpu_shutdown(device_t dv, int how) 1214 { 1215 struct cpu_softc *sc = device_private(dv); 1216 struct cpu_info *ci = sc->sc_info; 1217 1218 if ((ci->ci_flags & CPUF_BSP) != 0) 1219 return false; 1220 1221 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1222 return true; 1223 1224 return cpu_stop(dv); 1225 } 1226 1227 void 1228 cpu_get_tsc_freq(struct cpu_info *ci) 1229 { 1230 uint64_t last_tsc; 1231 1232 if (cpu_hascounter()) { 1233 last_tsc = cpu_counter_serializing(); 1234 i8254_delay(100000); 1235 ci->ci_data.cpu_cc_freq = 1236 (cpu_counter_serializing() - last_tsc) * 10; 1237 } 1238 } 1239 1240 void 1241 x86_cpu_idle_mwait(void) 1242 { 1243 struct cpu_info *ci = curcpu(); 1244 1245 KASSERT(ci->ci_ilevel == IPL_NONE); 1246 1247 x86_monitor(&ci->ci_want_resched, 0, 0); 1248 if (__predict_false(ci->ci_want_resched)) { 1249 return; 1250 } 1251 x86_mwait(0, 0); 1252 } 1253 1254 void 1255 x86_cpu_idle_halt(void) 1256 { 1257 struct cpu_info *ci = curcpu(); 1258 1259 KASSERT(ci->ci_ilevel == IPL_NONE); 1260 1261 x86_disable_intr(); 1262 if (!__predict_false(ci->ci_want_resched)) { 1263 x86_stihlt(); 1264 } else { 1265 x86_enable_intr(); 1266 } 1267 } 1268 1269 /* 1270 * Loads pmap for the current CPU. 1271 */ 1272 void 1273 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1274 { 1275 #ifdef SVS 1276 svs_pdir_switch(pmap); 1277 #endif 1278 1279 #ifdef PAE 1280 struct cpu_info *ci = curcpu(); 1281 bool interrupts_enabled; 1282 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1283 int i; 1284 1285 /* 1286 * disable interrupts to block TLB shootdowns, which can reload cr3. 1287 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1288 * reload cr3. 1289 */ 1290 interrupts_enabled = (x86_read_flags() & PSL_I) != 0; 1291 if (interrupts_enabled) 1292 x86_disable_intr(); 1293 1294 for (i = 0 ; i < PDP_SIZE; i++) { 1295 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1296 } 1297 1298 if (interrupts_enabled) 1299 x86_enable_intr(); 1300 tlbflush(); 1301 #else /* PAE */ 1302 lcr3(pmap_pdirpa(pmap, 0)); 1303 #endif /* PAE */ 1304 } 1305 1306 /* 1307 * Notify all other cpus to halt. 1308 */ 1309 1310 void 1311 cpu_broadcast_halt(void) 1312 { 1313 x86_broadcast_ipi(X86_IPI_HALT); 1314 } 1315 1316 /* 1317 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1318 */ 1319 1320 void 1321 cpu_kick(struct cpu_info *ci) 1322 { 1323 x86_send_ipi(ci, 0); 1324 } 1325
Indexes created Wed Sep 24 05:09:52 GMT 2025