cpu.c revision 1.23
1 /* $NetBSD: cpu.c,v 1.23 2008/03/04 15:24:02 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999 Stefan Grefen 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by the NetBSD 53 * Foundation, Inc. and its contributors. 54 * 4. Neither the name of The NetBSD Foundation nor the names of its 55 * contributors may be used to endorse or promote products derived 56 * from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 59 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 66 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 68 * SUCH DAMAGE. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.23 2008/03/04 15:24:02 cube Exp $"); 73 74 #include "opt_ddb.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_mpbios.h" /* for MPDEBUG */ 77 #include "opt_mtrr.h" 78 79 #include "lapic.h" 80 #include "ioapic.h" 81 82 #include <sys/param.h> 83 #include <sys/proc.h> 84 #include <sys/user.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/cpu.h> 89 #include <sys/atomic.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #ifdef i386 106 #include <machine/tlog.h> 107 #endif 108 109 #if NLAPIC > 0 110 #include <machine/apicvar.h> 111 #include <machine/i82489reg.h> 112 #include <machine/i82489var.h> 113 #endif 114 115 #if NIOAPIC > 0 116 #include <machine/i82093var.h> 117 #endif 118 119 #include <dev/ic/mc146818reg.h> 120 #include <i386/isa/nvram.h> 121 #include <dev/isa/isareg.h> 122 123 int cpu_match(device_t, cfdata_t, void *); 124 void cpu_attach(device_t, device_t, void *); 125 126 static bool cpu_suspend(device_t PMF_FN_PROTO); 127 static bool cpu_resume(device_t PMF_FN_PROTO); 128 129 struct cpu_softc { 130 device_t sc_dev; /* device tree glue */ 131 struct cpu_info *sc_info; /* pointer to CPU info */ 132 bool sc_wasonline; 133 }; 134 135 int mp_cpu_start(struct cpu_info *, paddr_t); 136 void mp_cpu_start_cleanup(struct cpu_info *); 137 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 138 mp_cpu_start_cleanup }; 139 140 141 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL); 143 144 /* 145 * Statically-allocated CPU info for the primary CPU (or the only 146 * CPU, on uniprocessors). The CPU info list is initialized to 147 * point at it. 148 */ 149 #ifdef TRAPLOG 150 struct tlog tlog_primary; 151 #endif 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 #ifdef TRAPLOG 158 .ci_tlog_base = &tlog_primary, 159 #endif /* !TRAPLOG */ 160 }; 161 162 struct cpu_info *cpu_info_list = &cpu_info_primary; 163 164 static void cpu_set_tss_gates(struct cpu_info *); 165 166 #ifdef i386 167 static void tss_init(struct i386tss *, void *, void *); 168 #endif 169 170 #ifdef MULTIPROCESSOR 171 static void cpu_init_idle_lwp(struct cpu_info *); 172 #endif 173 174 uint32_t cpus_attached = 0; 175 uint32_t cpus_running = 0; 176 177 extern char x86_64_doubleflt_stack[]; 178 179 bool x86_mp_online; 180 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 181 182 static vaddr_t cmos_data_mapping; 183 184 #ifdef MULTIPROCESSOR 185 /* 186 * Array of CPU info structures. Must be statically-allocated because 187 * curproc, etc. are used early. 188 */ 189 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary, }; 190 191 void cpu_hatch(void *); 192 static void cpu_boot_secondary(struct cpu_info *ci); 193 static void cpu_start_secondary(struct cpu_info *ci); 194 static void cpu_copy_trampoline(void); 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 void 203 cpu_init_first(void) 204 { 205 int cpunum = lapic_cpu_number(); 206 207 if (cpunum != 0) { 208 cpu_info[0] = NULL; 209 cpu_info[cpunum] = &cpu_info_primary; 210 } 211 212 cpu_info_primary.ci_cpuid = cpunum; 213 cpu_copy_trampoline(); 214 215 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 216 if (cmos_data_mapping == 0) 217 panic("No KVA for page 0"); 218 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE); 219 pmap_update(pmap_kernel()); 220 } 221 #endif 222 223 int 224 cpu_match(device_t parent, cfdata_t match, void *aux) 225 { 226 227 return 1; 228 } 229 230 static void 231 cpu_vm_init(struct cpu_info *ci) 232 { 233 int ncolors = 2, i; 234 235 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 236 struct x86_cache_info *cai; 237 int tcolors; 238 239 cai = &ci->ci_cinfo[i]; 240 241 tcolors = atop(cai->cai_totalsize); 242 switch(cai->cai_associativity) { 243 case 0xff: 244 tcolors = 1; /* fully associative */ 245 break; 246 case 0: 247 case 1: 248 break; 249 default: 250 tcolors /= cai->cai_associativity; 251 } 252 ncolors = max(ncolors, tcolors); 253 } 254 255 /* 256 * Knowing the size of the largest cache on this CPU, re-color 257 * our pages. 258 */ 259 if (ncolors <= uvmexp.ncolors) 260 return; 261 aprint_verbose("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors); 262 uvm_page_recolor(ncolors); 263 } 264 265 266 void 267 cpu_attach(device_t parent, device_t self, void *aux) 268 { 269 struct cpu_softc *sc = device_private(self); 270 struct cpu_attach_args *caa = aux; 271 struct cpu_info *ci; 272 uintptr_t ptr; 273 #if defined(MULTIPROCESSOR) 274 int cpunum = caa->cpu_number; 275 #endif 276 277 sc->sc_dev = self; 278 279 /* 280 * If we're an Application Processor, allocate a cpu_info 281 * structure, otherwise use the primary's. 282 */ 283 if (caa->cpu_role == CPU_ROLE_AP) { 284 aprint_naive(": Application Processor\n"); 285 ptr = (uintptr_t)malloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 286 M_DEVBUF, M_WAITOK); 287 ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) & 288 ~(CACHE_LINE_SIZE - 1)); 289 memset(ci, 0, sizeof(*ci)); 290 #if defined(MULTIPROCESSOR) 291 if (cpu_info[cpunum] != NULL) { 292 printf("\n"); 293 panic("cpu at apic id %d already attached?", cpunum); 294 } 295 cpu_info[cpunum] = ci; 296 #endif 297 #ifdef TRAPLOG 298 ci->ci_tlog_base = malloc(sizeof(struct tlog), 299 M_DEVBUF, M_WAITOK); 300 #endif 301 } else { 302 aprint_naive(": %s Processor\n", 303 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 304 ci = &cpu_info_primary; 305 #if defined(MULTIPROCESSOR) 306 if (cpunum != lapic_cpu_number()) { 307 printf("\n"); 308 panic("%s: running CPU is at apic %d" 309 " instead of at expected %d", 310 device_xname(sc->sc_dev), lapic_cpu_number(), 311 cpunum); 312 } 313 #endif 314 } 315 316 ci->ci_self = ci; 317 sc->sc_info = ci; 318 319 ci->ci_dev = self; 320 ci->ci_apicid = caa->cpu_number; 321 #ifdef MULTIPROCESSOR 322 ci->ci_cpuid = ci->ci_apicid; 323 #else 324 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 325 #endif 326 ci->ci_cpumask = (1 << ci->ci_cpuid); 327 ci->ci_func = caa->cpu_func; 328 329 if (caa->cpu_role == CPU_ROLE_AP) { 330 #ifdef MULTIPROCESSOR 331 int error; 332 333 error = mi_cpu_attach(ci); 334 if (error != 0) { 335 aprint_normal("\n"); 336 aprint_error("%s: mi_cpu_attach failed with %d\n", 337 device_xname(sc->sc_dev), error); 338 return; 339 } 340 #endif 341 cpu_init_tss(ci); 342 } else { 343 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 344 } 345 346 pmap_reference(pmap_kernel()); 347 ci->ci_pmap = pmap_kernel(); 348 ci->ci_tlbstate = TLBSTATE_STALE; 349 350 /* further PCB init done later. */ 351 352 switch (caa->cpu_role) { 353 case CPU_ROLE_SP: 354 aprint_normal(": (uniprocessor)\n"); 355 atomic_or_32(&ci->ci_flags, 356 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 357 cpu_intr_init(ci); 358 identifycpu(ci); 359 cpu_init(ci); 360 cpu_set_tss_gates(ci); 361 pmap_cpu_init_late(ci); 362 x86_errata(); 363 break; 364 365 case CPU_ROLE_BP: 366 aprint_normal(": (boot processor)\n"); 367 atomic_or_32(&ci->ci_flags, 368 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 369 cpu_intr_init(ci); 370 identifycpu(ci); 371 cpu_init(ci); 372 cpu_set_tss_gates(ci); 373 pmap_cpu_init_late(ci); 374 #if NLAPIC > 0 375 /* 376 * Enable local apic 377 */ 378 lapic_enable(); 379 lapic_set_lvt(); 380 lapic_calibrate_timer(ci); 381 #endif 382 #if NIOAPIC > 0 383 ioapic_bsp_id = caa->cpu_number; 384 #endif 385 x86_errata(); 386 break; 387 388 case CPU_ROLE_AP: 389 /* 390 * report on an AP 391 */ 392 aprint_normal(": (application processor)\n"); 393 394 #if defined(MULTIPROCESSOR) 395 cpu_intr_init(ci); 396 gdt_alloc_cpu(ci); 397 cpu_set_tss_gates(ci); 398 pmap_cpu_init_early(ci); 399 pmap_cpu_init_late(ci); 400 cpu_start_secondary(ci); 401 if (ci->ci_flags & CPUF_PRESENT) { 402 identifycpu(ci); 403 ci->ci_next = cpu_info_list->ci_next; 404 cpu_info_list->ci_next = ci; 405 } 406 #else 407 aprint_normal("%s: not started\n", device_xname(sc->sc_dev)); 408 #endif 409 break; 410 411 default: 412 printf("\n"); 413 panic("unknown processor type??\n"); 414 } 415 cpu_vm_init(ci); 416 417 cpus_attached |= ci->ci_cpumask; 418 419 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 420 aprint_error_dev(self, "couldn't establish power handler\n"); 421 422 #if defined(MULTIPROCESSOR) 423 if (mp_verbose) { 424 struct lwp *l = ci->ci_data.cpu_idlelwp; 425 426 aprint_verbose( 427 "%s: idle lwp at %p, idle sp at %p\n", 428 device_xname(sc->sc_dev), l, 429 #ifdef i386 430 (void *)l->l_addr->u_pcb.pcb_esp 431 #else 432 (void *)l->l_addr->u_pcb.pcb_rsp 433 #endif 434 ); 435 } 436 #endif 437 } 438 439 /* 440 * Initialize the processor appropriately. 441 */ 442 443 void 444 cpu_init(struct cpu_info *ci) 445 { 446 /* configure the CPU if needed */ 447 if (ci->cpu_setup != NULL) 448 (*ci->cpu_setup)(ci); 449 450 #ifdef i386 451 /* 452 * On a 486 or above, enable ring 0 write protection. 453 */ 454 if (ci->ci_cpu_class >= CPUCLASS_486) 455 lcr0(rcr0() | CR0_WP); 456 #else 457 lcr0(rcr0() | CR0_WP); 458 #endif 459 460 /* 461 * On a P6 or above, enable global TLB caching if the 462 * hardware supports it. 463 */ 464 if (cpu_feature & CPUID_PGE) 465 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 466 467 /* 468 * If we have FXSAVE/FXRESTOR, use them. 469 */ 470 if (cpu_feature & CPUID_FXSR) { 471 lcr4(rcr4() | CR4_OSFXSR); 472 473 /* 474 * If we have SSE/SSE2, enable XMM exceptions. 475 */ 476 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 477 lcr4(rcr4() | CR4_OSXMMEXCPT); 478 } 479 480 #ifdef MTRR 481 /* 482 * On a P6 or above, initialize MTRR's if the hardware supports them. 483 */ 484 if (cpu_feature & CPUID_MTRR) { 485 if ((ci->ci_flags & CPUF_AP) == 0) 486 i686_mtrr_init_first(); 487 mtrr_init_cpu(ci); 488 } 489 490 #ifdef i386 491 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 492 /* 493 * Must be a K6-2 Step >= 7 or a K6-III. 494 */ 495 if (CPUID2FAMILY(ci->ci_signature) == 5) { 496 if (CPUID2MODEL(ci->ci_signature) > 8 || 497 (CPUID2MODEL(ci->ci_signature) == 8 && 498 CPUID2STEPPING(ci->ci_signature) >= 7)) { 499 mtrr_funcs = &k6_mtrr_funcs; 500 k6_mtrr_init_first(); 501 mtrr_init_cpu(ci); 502 } 503 } 504 } 505 #endif /* i386 */ 506 #endif /* MTRR */ 507 508 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 509 atomic_or_32(&cpus_running, ci->ci_cpumask); 510 511 #ifndef MULTIPROCESSOR 512 /* XXX */ 513 x86_patch(); 514 #endif 515 } 516 517 #ifdef MULTIPROCESSOR 518 void 519 cpu_boot_secondary_processors(void) 520 { 521 struct cpu_info *ci; 522 u_long i; 523 524 /* Now that we know the number of CPUs, patch the text segment. */ 525 x86_patch(); 526 527 for (i=0; i < X86_MAXPROCS; i++) { 528 ci = cpu_info[i]; 529 if (ci == NULL) 530 continue; 531 if (ci->ci_data.cpu_idlelwp == NULL) 532 continue; 533 if ((ci->ci_flags & CPUF_PRESENT) == 0) 534 continue; 535 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 536 continue; 537 cpu_boot_secondary(ci); 538 } 539 540 x86_mp_online = true; 541 } 542 543 static void 544 cpu_init_idle_lwp(struct cpu_info *ci) 545 { 546 struct lwp *l = ci->ci_data.cpu_idlelwp; 547 struct pcb *pcb = &l->l_addr->u_pcb; 548 549 pcb->pcb_cr0 = rcr0(); 550 } 551 552 void 553 cpu_init_idle_lwps(void) 554 { 555 struct cpu_info *ci; 556 u_long i; 557 558 for (i = 0; i < X86_MAXPROCS; i++) { 559 ci = cpu_info[i]; 560 if (ci == NULL) 561 continue; 562 if (ci->ci_data.cpu_idlelwp == NULL) 563 continue; 564 if ((ci->ci_flags & CPUF_PRESENT) == 0) 565 continue; 566 cpu_init_idle_lwp(ci); 567 } 568 } 569 570 void 571 cpu_start_secondary(struct cpu_info *ci) 572 { 573 int i; 574 extern paddr_t mp_pdirpa; 575 576 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 577 578 atomic_or_32(&ci->ci_flags, CPUF_AP); 579 580 aprint_debug("%s: starting\n", ci->ci_dev->dv_xname); 581 582 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 583 CPU_STARTUP(ci, mp_trampoline_paddr); 584 585 /* 586 * wait for it to become ready 587 */ 588 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) { 589 i8254_delay(10); 590 } 591 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 592 aprint_error("%s: failed to become ready\n", 593 ci->ci_dev->dv_xname); 594 #if defined(MPDEBUG) && defined(DDB) 595 printf("dropping into debugger; continue from here to resume boot\n"); 596 Debugger(); 597 #endif 598 } 599 600 CPU_START_CLEANUP(ci); 601 } 602 603 void 604 cpu_boot_secondary(struct cpu_info *ci) 605 { 606 int i; 607 608 atomic_or_32(&ci->ci_flags, CPUF_GO); 609 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) { 610 i8254_delay(10); 611 } 612 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 613 aprint_error("%s: failed to start\n", ci->ci_dev->dv_xname); 614 #if defined(MPDEBUG) && defined(DDB) 615 printf("dropping into debugger; continue from here to resume boot\n"); 616 Debugger(); 617 #endif 618 } 619 } 620 621 /* 622 * The CPU ends up here when its ready to run 623 * This is called from code in mptramp.s; at this point, we are running 624 * in the idle pcb/idle stack of the new CPU. When this function returns, 625 * this processor will enter the idle loop and start looking for work. 626 */ 627 void 628 cpu_hatch(void *v) 629 { 630 struct cpu_info *ci = (struct cpu_info *)v; 631 int s, i; 632 633 #ifdef __x86_64__ 634 cpu_init_msrs(ci, true); 635 #endif 636 cpu_probe_features(ci); 637 cpu_feature &= ci->ci_feature_flags; 638 cpu_feature2 &= ci->ci_feature2_flags; 639 640 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 641 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 642 while ((ci->ci_flags & CPUF_GO) == 0) { 643 /* Don't use delay, boot CPU may be patching the text. */ 644 for (i = 10000; i != 0; i--) 645 x86_pause(); 646 } 647 648 /* Beacuse the text may have been patched in x86_patch(). */ 649 wbinvd(); 650 x86_flush(); 651 652 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 653 654 lcr3(pmap_kernel()->pm_pdirpa); 655 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 656 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 657 cpu_init_idt(); 658 gdt_init_cpu(ci); 659 lapic_enable(); 660 lapic_set_lvt(); 661 lapic_initclocks(); 662 663 #ifdef i386 664 npxinit(ci); 665 #else 666 fpuinit(ci); 667 #endif 668 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 669 ltr(ci->ci_tss_sel); 670 671 cpu_init(ci); 672 cpu_get_tsc_freq(ci); 673 674 s = splhigh(); 675 #ifdef i386 676 lapic_tpr = 0; 677 #else 678 lcr8(0); 679 #endif 680 x86_enable_intr(); 681 splx(s); 682 x86_errata(); 683 684 aprint_debug("%s: CPU %ld running\n", ci->ci_dev->dv_xname, 685 (long)ci->ci_cpuid); 686 } 687 688 #if defined(DDB) 689 690 #include <ddb/db_output.h> 691 #include <machine/db_machdep.h> 692 693 /* 694 * Dump CPU information from ddb. 695 */ 696 void 697 cpu_debug_dump(void) 698 { 699 struct cpu_info *ci; 700 CPU_INFO_ITERATOR cii; 701 702 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 703 for (CPU_INFO_FOREACH(cii, ci)) { 704 db_printf("%p %s %ld %x %x %10p %10p\n", 705 ci, 706 ci->ci_dev == NULL ? "BOOT" : ci->ci_dev->dv_xname, 707 (long)ci->ci_cpuid, 708 ci->ci_flags, ci->ci_ipis, 709 ci->ci_curlwp, 710 ci->ci_fpcurlwp); 711 } 712 } 713 #endif 714 715 static void 716 cpu_copy_trampoline(void) 717 { 718 /* 719 * Copy boot code. 720 */ 721 extern u_char cpu_spinup_trampoline[]; 722 extern u_char cpu_spinup_trampoline_end[]; 723 724 vaddr_t mp_trampoline_vaddr; 725 726 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 727 UVM_KMF_VAONLY); 728 729 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 730 VM_PROT_READ | VM_PROT_WRITE); 731 pmap_update(pmap_kernel()); 732 memcpy((void *)mp_trampoline_vaddr, 733 cpu_spinup_trampoline, 734 cpu_spinup_trampoline_end-cpu_spinup_trampoline); 735 736 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 737 pmap_update(pmap_kernel()); 738 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 739 } 740 741 #endif 742 743 #ifdef i386 744 static void 745 tss_init(struct i386tss *tss, void *stack, void *func) 746 { 747 memset(tss, 0, sizeof *tss); 748 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 749 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 750 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 751 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 752 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 753 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 754 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 755 tss->tss_esp = (int)((char *)stack + USPACE - 16); 756 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 757 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 758 tss->__tss_eip = (int)func; 759 } 760 761 /* XXX */ 762 #define IDTVEC(name) __CONCAT(X, name) 763 typedef void (vector)(void); 764 extern vector IDTVEC(tss_trap08); 765 #ifdef DDB 766 extern vector Xintrddbipi; 767 extern int ddb_vec; 768 #endif 769 770 static void 771 cpu_set_tss_gates(struct cpu_info *ci) 772 { 773 struct segment_descriptor sd; 774 775 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 776 UVM_KMF_WIRED); 777 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 778 IDTVEC(tss_trap08)); 779 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 780 SDT_SYS386TSS, SEL_KPL, 0, 0); 781 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 782 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 783 GSEL(GTRAPTSS_SEL, SEL_KPL)); 784 785 #if defined(DDB) && defined(MULTIPROCESSOR) 786 /* 787 * Set up separate handler for the DDB IPI, so that it doesn't 788 * stomp on a possibly corrupted stack. 789 * 790 * XXX overwriting the gate set in db_machine_init. 791 * Should rearrange the code so that it's set only once. 792 */ 793 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 794 UVM_KMF_WIRED); 795 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi); 796 797 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 798 SDT_SYS386TSS, SEL_KPL, 0, 0); 799 ci->ci_gdt[GIPITSS_SEL].sd = sd; 800 801 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 802 GSEL(GIPITSS_SEL, SEL_KPL)); 803 #endif 804 } 805 #else 806 static void 807 cpu_set_tss_gates(struct cpu_info *ci) 808 { 809 810 } 811 #endif /* i386 */ 812 813 int 814 mp_cpu_start(struct cpu_info *ci, paddr_t target) 815 { 816 #if NLAPIC > 0 817 int error; 818 #endif 819 unsigned short dwordptr[2]; 820 821 /* 822 * Bootstrap code must be addressable in real mode 823 * and it must be page aligned. 824 */ 825 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 826 827 /* 828 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 829 */ 830 831 outb(IO_RTC, NVRAM_RESET); 832 outb(IO_RTC+1, NVRAM_RESET_JUMP); 833 834 /* 835 * "and the warm reset vector (DWORD based at 40:67) to point 836 * to the AP startup code ..." 837 */ 838 839 dwordptr[0] = 0; 840 dwordptr[1] = target >> 4; 841 842 memcpy((uint8_t *)(cmos_data_mapping + 0x467), dwordptr, 4); 843 844 #if NLAPIC > 0 845 /* 846 * ... prior to executing the following sequence:" 847 */ 848 849 if (ci->ci_flags & CPUF_AP) { 850 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 851 return error; 852 853 i8254_delay(10000); 854 855 if (cpu_feature & CPUID_APIC) { 856 857 if ((error = x86_ipi(target / PAGE_SIZE, 858 ci->ci_apicid, 859 LAPIC_DLMODE_STARTUP)) != 0) 860 return error; 861 i8254_delay(200); 862 863 if ((error = x86_ipi(target / PAGE_SIZE, 864 ci->ci_apicid, 865 LAPIC_DLMODE_STARTUP)) != 0) 866 return error; 867 i8254_delay(200); 868 } 869 } 870 #endif 871 return 0; 872 } 873 874 void 875 mp_cpu_start_cleanup(struct cpu_info *ci) 876 { 877 /* 878 * Ensure the NVRAM reset byte contains something vaguely sane. 879 */ 880 881 outb(IO_RTC, NVRAM_RESET); 882 outb(IO_RTC+1, NVRAM_RESET_RST); 883 } 884 885 #ifdef __x86_64__ 886 typedef void (vector)(void); 887 extern vector Xsyscall, Xsyscall32; 888 889 void 890 cpu_init_msrs(struct cpu_info *ci, bool full) 891 { 892 wrmsr(MSR_STAR, 893 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 894 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 895 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 896 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 897 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 898 899 if (full) { 900 wrmsr(MSR_FSBASE, 0); 901 wrmsr(MSR_GSBASE, (u_int64_t)ci); 902 wrmsr(MSR_KERNELGSBASE, 0); 903 } 904 905 if (cpu_feature & CPUID_NOX) 906 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 907 } 908 #endif /* __x86_64__ */ 909 910 void 911 cpu_offline_md(void) 912 { 913 int s; 914 915 s = splhigh(); 916 #ifdef __i386__ 917 npxsave_cpu(true); 918 #else 919 fpusave_cpu(true); 920 #endif 921 splx(s); 922 } 923 924 /* XXX joerg restructure and restart CPUs individually */ 925 static bool 926 cpu_suspend(device_t dv PMF_FN_ARGS) 927 { 928 struct cpu_softc *sc = device_private(dv); 929 struct cpu_info *ci = sc->sc_info; 930 int err; 931 932 if (ci->ci_flags & CPUF_PRIMARY) 933 return true; 934 if (ci->ci_data.cpu_idlelwp == NULL) 935 return true; 936 if ((ci->ci_flags & CPUF_PRESENT) == 0) 937 return true; 938 939 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 940 941 if (sc->sc_wasonline) { 942 mutex_enter(&cpu_lock); 943 err = cpu_setonline(ci, false); 944 mutex_exit(&cpu_lock); 945 946 if (err) 947 return false; 948 } 949 950 return true; 951 } 952 953 static bool 954 cpu_resume(device_t dv PMF_FN_ARGS) 955 { 956 struct cpu_softc *sc = device_private(dv); 957 struct cpu_info *ci = sc->sc_info; 958 int err = 0; 959 960 if (ci->ci_flags & CPUF_PRIMARY) 961 return true; 962 if (ci->ci_data.cpu_idlelwp == NULL) 963 return true; 964 if ((ci->ci_flags & CPUF_PRESENT) == 0) 965 return true; 966 967 if (sc->sc_wasonline) { 968 mutex_enter(&cpu_lock); 969 err = cpu_setonline(ci, true); 970 mutex_exit(&cpu_lock); 971 } 972 973 return err == 0; 974 } 975 976 void 977 cpu_get_tsc_freq(struct cpu_info *ci) 978 { 979 uint64_t last_tsc; 980 u_int junk[4]; 981 982 if (ci->ci_feature_flags & CPUID_TSC) { 983 /* Serialize. */ 984 x86_cpuid(0, junk); 985 last_tsc = rdtsc(); 986 i8254_delay(100000); 987 ci->ci_tsc_freq = (rdtsc() - last_tsc) * 10; 988 } 989 } 990
Indexes created Tue Sep 23 22:09:46 GMT 2025