cpu.c revision 1.81
1 /* $NetBSD: cpu.c,v 1.81 2011/02/19 13:52:28 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.81 2011/02/19 13:52:28 jmcneill Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 71 #include "lapic.h" 72 #include "ioapic.h" 73 74 #ifdef i386 75 #include "npx.h" 76 #endif 77 78 #include <sys/param.h> 79 #include <sys/proc.h> 80 #include <sys/systm.h> 81 #include <sys/device.h> 82 #include <sys/kmem.h> 83 #include <sys/cpu.h> 84 #include <sys/atomic.h> 85 #include <sys/reboot.h> 86 87 #include <uvm/uvm.h> 88 89 #include <machine/cpufunc.h> 90 #include <machine/cpuvar.h> 91 #include <machine/pmap.h> 92 #include <machine/vmparam.h> 93 #include <machine/mpbiosvar.h> 94 #include <machine/pcb.h> 95 #include <machine/specialreg.h> 96 #include <machine/segments.h> 97 #include <machine/gdt.h> 98 #include <machine/mtrr.h> 99 #include <machine/pio.h> 100 #include <machine/cpu_counter.h> 101 102 #ifdef i386 103 #include <machine/tlog.h> 104 #endif 105 106 #include <machine/apicvar.h> 107 #include <machine/i82489reg.h> 108 #include <machine/i82489var.h> 109 110 #include <dev/ic/mc146818reg.h> 111 #include <i386/isa/nvram.h> 112 #include <dev/isa/isareg.h> 113 114 #include "tsc.h" 115 116 #if MAXCPUS > 32 117 #error cpu_info contains 32bit bitmasks 118 #endif 119 120 int cpu_match(device_t, cfdata_t, void *); 121 void cpu_attach(device_t, device_t, void *); 122 int cpu_rescan(device_t, const char *, const int *); 123 void cpu_childdetached(device_t, device_t); 124 125 126 static bool cpu_suspend(device_t, const pmf_qual_t *); 127 static bool cpu_resume(device_t, const pmf_qual_t *); 128 static bool cpu_shutdown(device_t, int); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 int mp_cpu_start(struct cpu_info *, paddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 142 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 143 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 144 145 /* 146 * Statically-allocated CPU info for the primary CPU (or the only 147 * CPU, on uniprocessors). The CPU info list is initialized to 148 * point at it. 149 */ 150 #ifdef TRAPLOG 151 struct tlog tlog_primary; 152 #endif 153 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 154 .ci_dev = 0, 155 .ci_self = &cpu_info_primary, 156 .ci_idepth = -1, 157 .ci_curlwp = &lwp0, 158 .ci_curldt = -1, 159 #ifdef TRAPLOG 160 .ci_tlog_base = &tlog_primary, 161 #endif /* !TRAPLOG */ 162 }; 163 164 struct cpu_info *cpu_info_list = &cpu_info_primary; 165 166 static void cpu_set_tss_gates(struct cpu_info *); 167 168 #ifdef i386 169 static void tss_init(struct i386tss *, void *, void *); 170 #endif 171 172 static void cpu_init_idle_lwp(struct cpu_info *); 173 174 uint32_t cpus_attached = 0; 175 uint32_t cpus_running = 0; 176 177 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 178 * [0] basic features %edx 179 * [1] basic features %ecx 180 * [2] extended features %edx 181 * [3] extended features %ecx 182 * [4] VIA padlock features 183 */ 184 185 extern char x86_64_doubleflt_stack[]; 186 187 bool x86_mp_online; 188 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 189 static vaddr_t cmos_data_mapping; 190 struct cpu_info *cpu_starting; 191 192 void cpu_hatch(void *); 193 static void cpu_boot_secondary(struct cpu_info *ci); 194 static void cpu_start_secondary(struct cpu_info *ci); 195 static void cpu_copy_trampoline(void); 196 197 /* 198 * Runs once per boot once multiprocessor goo has been detected and 199 * the local APIC on the boot processor has been mapped. 200 * 201 * Called from lapic_boot_init() (from mpbios_scan()). 202 */ 203 void 204 cpu_init_first(void) 205 { 206 207 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 208 cpu_copy_trampoline(); 209 210 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 211 if (cmos_data_mapping == 0) 212 panic("No KVA for page 0"); 213 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 214 pmap_update(pmap_kernel()); 215 } 216 217 int 218 cpu_match(device_t parent, cfdata_t match, void *aux) 219 { 220 221 return 1; 222 } 223 224 static void 225 cpu_vm_init(struct cpu_info *ci) 226 { 227 int ncolors = 2, i; 228 229 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 230 struct x86_cache_info *cai; 231 int tcolors; 232 233 cai = &ci->ci_cinfo[i]; 234 235 tcolors = atop(cai->cai_totalsize); 236 switch(cai->cai_associativity) { 237 case 0xff: 238 tcolors = 1; /* fully associative */ 239 break; 240 case 0: 241 case 1: 242 break; 243 default: 244 tcolors /= cai->cai_associativity; 245 } 246 ncolors = max(ncolors, tcolors); 247 /* 248 * If the desired number of colors is not a power of 249 * two, it won't be good. Find the greatest power of 250 * two which is an even divisor of the number of colors, 251 * to preserve even coloring of pages. 252 */ 253 if (ncolors & (ncolors - 1) ) { 254 int try, picked = 1; 255 for (try = 1; try < ncolors; try *= 2) { 256 if (ncolors % try == 0) picked = try; 257 } 258 if (picked == 1) { 259 panic("desired number of cache colors %d is " 260 " > 1, but not even!", ncolors); 261 } 262 ncolors = picked; 263 } 264 } 265 266 /* 267 * Knowing the size of the largest cache on this CPU, re-color 268 * our pages. 269 */ 270 if (ncolors <= uvmexp.ncolors) 271 return; 272 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 273 uvm_page_recolor(ncolors); 274 } 275 276 277 void 278 cpu_attach(device_t parent, device_t self, void *aux) 279 { 280 struct cpu_softc *sc = device_private(self); 281 struct cpu_attach_args *caa = aux; 282 struct cpu_info *ci; 283 uintptr_t ptr; 284 int cpunum = caa->cpu_number; 285 static bool again; 286 287 sc->sc_dev = self; 288 289 if (cpus_attached == ~0) { 290 aprint_error(": increase MAXCPUS\n"); 291 return; 292 } 293 294 /* 295 * If we're an Application Processor, allocate a cpu_info 296 * structure, otherwise use the primary's. 297 */ 298 if (caa->cpu_role == CPU_ROLE_AP) { 299 if ((boothowto & RB_MD1) != 0) { 300 aprint_error(": multiprocessor boot disabled\n"); 301 if (!pmf_device_register(self, NULL, NULL)) 302 aprint_error_dev(self, 303 "couldn't establish power handler\n"); 304 return; 305 } 306 aprint_naive(": Application Processor\n"); 307 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 308 KM_SLEEP); 309 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 310 ci->ci_curldt = -1; 311 #ifdef TRAPLOG 312 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 313 #endif 314 } else { 315 aprint_naive(": %s Processor\n", 316 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 317 ci = &cpu_info_primary; 318 if (cpunum != lapic_cpu_number()) { 319 /* XXX should be done earlier. */ 320 uint32_t reg; 321 aprint_verbose("\n"); 322 aprint_verbose_dev(self, "running CPU at apic %d" 323 " instead of at expected %d", lapic_cpu_number(), 324 cpunum); 325 reg = i82489_readreg(LAPIC_ID); 326 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 327 (cpunum << LAPIC_ID_SHIFT)); 328 } 329 if (cpunum != lapic_cpu_number()) { 330 aprint_error_dev(self, "unable to reset apic id\n"); 331 } 332 } 333 334 ci->ci_self = ci; 335 sc->sc_info = ci; 336 ci->ci_dev = self; 337 ci->ci_acpiid = caa->cpu_id; 338 ci->ci_cpuid = caa->cpu_number; 339 ci->ci_func = caa->cpu_func; 340 341 /* Must be before mi_cpu_attach(). */ 342 cpu_vm_init(ci); 343 344 if (caa->cpu_role == CPU_ROLE_AP) { 345 int error; 346 347 error = mi_cpu_attach(ci); 348 if (error != 0) { 349 aprint_normal("\n"); 350 aprint_error_dev(self, 351 "mi_cpu_attach failed with %d\n", error); 352 return; 353 } 354 cpu_init_tss(ci); 355 } else { 356 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 357 } 358 359 ci->ci_cpumask = (1 << cpu_index(ci)); 360 pmap_reference(pmap_kernel()); 361 ci->ci_pmap = pmap_kernel(); 362 ci->ci_tlbstate = TLBSTATE_STALE; 363 364 /* 365 * Boot processor may not be attached first, but the below 366 * must be done to allow booting other processors. 367 */ 368 if (!again) { 369 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 370 /* Basic init. */ 371 cpu_intr_init(ci); 372 cpu_get_tsc_freq(ci); 373 cpu_init(ci); 374 cpu_set_tss_gates(ci); 375 pmap_cpu_init_late(ci); 376 if (caa->cpu_role != CPU_ROLE_SP) { 377 /* Enable lapic. */ 378 lapic_enable(); 379 lapic_set_lvt(); 380 lapic_calibrate_timer(ci); 381 } 382 /* Make sure DELAY() is initialized. */ 383 DELAY(1); 384 again = true; 385 } 386 387 /* further PCB init done later. */ 388 389 switch (caa->cpu_role) { 390 case CPU_ROLE_SP: 391 atomic_or_32(&ci->ci_flags, CPUF_SP); 392 cpu_identify(ci); 393 x86_errata(); 394 x86_cpu_idle_init(); 395 break; 396 397 case CPU_ROLE_BP: 398 atomic_or_32(&ci->ci_flags, CPUF_BSP); 399 cpu_identify(ci); 400 x86_errata(); 401 x86_cpu_idle_init(); 402 break; 403 404 case CPU_ROLE_AP: 405 /* 406 * report on an AP 407 */ 408 cpu_intr_init(ci); 409 gdt_alloc_cpu(ci); 410 cpu_set_tss_gates(ci); 411 pmap_cpu_init_early(ci); 412 pmap_cpu_init_late(ci); 413 cpu_start_secondary(ci); 414 if (ci->ci_flags & CPUF_PRESENT) { 415 struct cpu_info *tmp; 416 417 cpu_identify(ci); 418 tmp = cpu_info_list; 419 while (tmp->ci_next) 420 tmp = tmp->ci_next; 421 422 tmp->ci_next = ci; 423 } 424 break; 425 426 default: 427 aprint_normal("\n"); 428 panic("unknown processor type??\n"); 429 } 430 431 pat_init(ci); 432 atomic_or_32(&cpus_attached, ci->ci_cpumask); 433 434 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 435 aprint_error_dev(self, "couldn't establish power handler\n"); 436 437 if (mp_verbose) { 438 struct lwp *l = ci->ci_data.cpu_idlelwp; 439 struct pcb *pcb = lwp_getpcb(l); 440 441 aprint_verbose_dev(self, 442 "idle lwp at %p, idle sp at %p\n", 443 l, 444 #ifdef i386 445 (void *)pcb->pcb_esp 446 #else 447 (void *)pcb->pcb_rsp 448 #endif 449 ); 450 } 451 452 cpu_rescan(self, NULL, NULL); 453 } 454 455 int 456 cpu_rescan(device_t self, const char *ifattr, const int *locators) 457 { 458 struct cpufeature_attach_args cfaa; 459 struct cpu_softc *sc = device_private(self); 460 struct cpu_info *ci = sc->sc_info; 461 462 memset(&cfaa, 0, sizeof(cfaa)); 463 cfaa.ci = ci; 464 465 if (ifattr_match(ifattr, "cpufeaturebus")) { 466 if (ci->ci_padlock == NULL) { 467 cfaa.name = "padlock"; 468 ci->ci_padlock = config_found_ia(self, 469 "cpufeaturebus", &cfaa, NULL); 470 } 471 } 472 473 return 0; 474 } 475 476 void 477 cpu_childdetached(device_t self, device_t child) 478 { 479 struct cpu_softc *sc = device_private(self); 480 struct cpu_info *ci = sc->sc_info; 481 482 if (ci->ci_padlock == child) 483 ci->ci_padlock = NULL; 484 } 485 486 /* 487 * Initialize the processor appropriately. 488 */ 489 490 void 491 cpu_init(struct cpu_info *ci) 492 { 493 494 lcr0(rcr0() | CR0_WP); 495 496 /* 497 * On a P6 or above, enable global TLB caching if the 498 * hardware supports it. 499 */ 500 if (cpu_feature[0] & CPUID_PGE) 501 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 502 503 /* 504 * If we have FXSAVE/FXRESTOR, use them. 505 */ 506 if (cpu_feature[0] & CPUID_FXSR) { 507 lcr4(rcr4() | CR4_OSFXSR); 508 509 /* 510 * If we have SSE/SSE2, enable XMM exceptions. 511 */ 512 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 513 lcr4(rcr4() | CR4_OSXMMEXCPT); 514 } 515 516 #ifdef MTRR 517 /* 518 * On a P6 or above, initialize MTRR's if the hardware supports them. 519 */ 520 if (cpu_feature[0] & CPUID_MTRR) { 521 if ((ci->ci_flags & CPUF_AP) == 0) 522 i686_mtrr_init_first(); 523 mtrr_init_cpu(ci); 524 } 525 526 #ifdef i386 527 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 528 /* 529 * Must be a K6-2 Step >= 7 or a K6-III. 530 */ 531 if (CPUID2FAMILY(ci->ci_signature) == 5) { 532 if (CPUID2MODEL(ci->ci_signature) > 8 || 533 (CPUID2MODEL(ci->ci_signature) == 8 && 534 CPUID2STEPPING(ci->ci_signature) >= 7)) { 535 mtrr_funcs = &k6_mtrr_funcs; 536 k6_mtrr_init_first(); 537 mtrr_init_cpu(ci); 538 } 539 } 540 } 541 #endif /* i386 */ 542 #endif /* MTRR */ 543 544 atomic_or_32(&cpus_running, ci->ci_cpumask); 545 546 if (ci != &cpu_info_primary) { 547 /* Synchronize TSC again, and check for drift. */ 548 wbinvd(); 549 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 550 tsc_sync_ap(ci); 551 } else { 552 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 553 } 554 } 555 556 void 557 cpu_boot_secondary_processors(void) 558 { 559 struct cpu_info *ci; 560 u_long i; 561 562 /* Now that we know the number of CPUs, patch the text segment. */ 563 x86_patch(false); 564 565 for (i=0; i < maxcpus; i++) { 566 ci = cpu_lookup(i); 567 if (ci == NULL) 568 continue; 569 if (ci->ci_data.cpu_idlelwp == NULL) 570 continue; 571 if ((ci->ci_flags & CPUF_PRESENT) == 0) 572 continue; 573 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 574 continue; 575 cpu_boot_secondary(ci); 576 } 577 578 x86_mp_online = true; 579 580 /* Now that we know about the TSC, attach the timecounter. */ 581 tsc_tc_init(); 582 583 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 584 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 585 } 586 587 static void 588 cpu_init_idle_lwp(struct cpu_info *ci) 589 { 590 struct lwp *l = ci->ci_data.cpu_idlelwp; 591 struct pcb *pcb = lwp_getpcb(l); 592 593 pcb->pcb_cr0 = rcr0(); 594 } 595 596 void 597 cpu_init_idle_lwps(void) 598 { 599 struct cpu_info *ci; 600 u_long i; 601 602 for (i = 0; i < maxcpus; i++) { 603 ci = cpu_lookup(i); 604 if (ci == NULL) 605 continue; 606 if (ci->ci_data.cpu_idlelwp == NULL) 607 continue; 608 if ((ci->ci_flags & CPUF_PRESENT) == 0) 609 continue; 610 cpu_init_idle_lwp(ci); 611 } 612 } 613 614 void 615 cpu_start_secondary(struct cpu_info *ci) 616 { 617 extern paddr_t mp_pdirpa; 618 u_long psl; 619 int i; 620 621 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 622 atomic_or_32(&ci->ci_flags, CPUF_AP); 623 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 624 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 625 return; 626 } 627 628 /* 629 * Wait for it to become ready. Setting cpu_starting opens the 630 * initial gate and allows the AP to start soft initialization. 631 */ 632 KASSERT(cpu_starting == NULL); 633 cpu_starting = ci; 634 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 635 #ifdef MPDEBUG 636 extern int cpu_trace[3]; 637 static int otrace[3]; 638 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 639 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 640 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 641 memcpy(otrace, cpu_trace, sizeof(otrace)); 642 } 643 #endif 644 i8254_delay(10); 645 } 646 647 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 648 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 649 #if defined(MPDEBUG) && defined(DDB) 650 printf("dropping into debugger; continue from here to resume boot\n"); 651 Debugger(); 652 #endif 653 } else { 654 /* 655 * Synchronize time stamp counters. Invalidate cache and do 656 * twice to try and minimize possible cache effects. Disable 657 * interrupts to try and rule out any external interference. 658 */ 659 psl = x86_read_psl(); 660 x86_disable_intr(); 661 wbinvd(); 662 tsc_sync_bp(ci); 663 x86_write_psl(psl); 664 } 665 666 CPU_START_CLEANUP(ci); 667 cpu_starting = NULL; 668 } 669 670 void 671 cpu_boot_secondary(struct cpu_info *ci) 672 { 673 int64_t drift; 674 u_long psl; 675 int i; 676 677 atomic_or_32(&ci->ci_flags, CPUF_GO); 678 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 679 i8254_delay(10); 680 } 681 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 682 aprint_error_dev(ci->ci_dev, "failed to start\n"); 683 #if defined(MPDEBUG) && defined(DDB) 684 printf("dropping into debugger; continue from here to resume boot\n"); 685 Debugger(); 686 #endif 687 } else { 688 /* Synchronize TSC again, check for drift. */ 689 drift = ci->ci_data.cpu_cc_skew; 690 psl = x86_read_psl(); 691 x86_disable_intr(); 692 wbinvd(); 693 tsc_sync_bp(ci); 694 x86_write_psl(psl); 695 drift -= ci->ci_data.cpu_cc_skew; 696 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 697 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 698 tsc_sync_drift(drift); 699 } 700 } 701 702 /* 703 * The CPU ends up here when its ready to run 704 * This is called from code in mptramp.s; at this point, we are running 705 * in the idle pcb/idle stack of the new CPU. When this function returns, 706 * this processor will enter the idle loop and start looking for work. 707 */ 708 void 709 cpu_hatch(void *v) 710 { 711 struct cpu_info *ci = (struct cpu_info *)v; 712 struct pcb *pcb; 713 int s, i; 714 715 cpu_init_msrs(ci, true); 716 cpu_probe(ci); 717 718 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 719 /* cpu_get_tsc_freq(ci); */ 720 721 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 722 723 /* 724 * Synchronize time stamp counters. Invalidate cache and do twice 725 * to try and minimize possible cache effects. Note that interrupts 726 * are off at this point. 727 */ 728 wbinvd(); 729 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 730 tsc_sync_ap(ci); 731 732 /* 733 * Wait to be brought online. Use 'monitor/mwait' if available, 734 * in order to make the TSC drift as much as possible. so that 735 * we can detect it later. If not available, try 'pause'. 736 * We'd like to use 'hlt', but we have interrupts off. 737 */ 738 while ((ci->ci_flags & CPUF_GO) == 0) { 739 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 740 x86_monitor(&ci->ci_flags, 0, 0); 741 if ((ci->ci_flags & CPUF_GO) != 0) { 742 continue; 743 } 744 x86_mwait(0, 0); 745 } else { 746 for (i = 10000; i != 0; i--) { 747 x86_pause(); 748 } 749 } 750 } 751 752 /* Because the text may have been patched in x86_patch(). */ 753 wbinvd(); 754 x86_flush(); 755 756 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 757 758 #ifdef PAE 759 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 760 for (i = 0 ; i < PDP_SIZE; i++) { 761 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 762 } 763 lcr3(ci->ci_pae_l3_pdirpa); 764 #else 765 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 766 #endif 767 768 pcb = lwp_getpcb(curlwp); 769 pcb->pcb_cr3 = rcr3(); 770 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 771 lcr0(pcb->pcb_cr0); 772 773 cpu_init_idt(); 774 gdt_init_cpu(ci); 775 lapic_enable(); 776 lapic_set_lvt(); 777 lapic_initclocks(); 778 779 #ifdef i386 780 #if NNPX > 0 781 npxinit(ci); 782 #endif 783 #else 784 fpuinit(ci); 785 #endif 786 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 787 ltr(ci->ci_tss_sel); 788 789 cpu_init(ci); 790 cpu_get_tsc_freq(ci); 791 792 s = splhigh(); 793 #ifdef i386 794 lapic_tpr = 0; 795 #else 796 lcr8(0); 797 #endif 798 x86_enable_intr(); 799 splx(s); 800 x86_errata(); 801 802 aprint_debug_dev(ci->ci_dev, "running\n"); 803 } 804 805 #if defined(DDB) 806 807 #include <ddb/db_output.h> 808 #include <machine/db_machdep.h> 809 810 /* 811 * Dump CPU information from ddb. 812 */ 813 void 814 cpu_debug_dump(void) 815 { 816 struct cpu_info *ci; 817 CPU_INFO_ITERATOR cii; 818 819 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 820 for (CPU_INFO_FOREACH(cii, ci)) { 821 db_printf("%p %s %ld %x %x %10p %10p\n", 822 ci, 823 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 824 (long)ci->ci_cpuid, 825 ci->ci_flags, ci->ci_ipis, 826 ci->ci_curlwp, 827 ci->ci_fpcurlwp); 828 } 829 } 830 #endif 831 832 static void 833 cpu_copy_trampoline(void) 834 { 835 /* 836 * Copy boot code. 837 */ 838 extern u_char cpu_spinup_trampoline[]; 839 extern u_char cpu_spinup_trampoline_end[]; 840 841 vaddr_t mp_trampoline_vaddr; 842 843 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 844 UVM_KMF_VAONLY); 845 846 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 847 VM_PROT_READ | VM_PROT_WRITE, 0); 848 pmap_update(pmap_kernel()); 849 memcpy((void *)mp_trampoline_vaddr, 850 cpu_spinup_trampoline, 851 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 852 853 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 854 pmap_update(pmap_kernel()); 855 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 856 } 857 858 #ifdef i386 859 static void 860 tss_init(struct i386tss *tss, void *stack, void *func) 861 { 862 KASSERT(curcpu()->ci_pmap == pmap_kernel()); 863 864 memset(tss, 0, sizeof *tss); 865 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 866 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 867 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 868 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 869 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 870 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 871 /* %cr3 contains the value associated to pmap_kernel */ 872 tss->tss_cr3 = rcr3(); 873 tss->tss_esp = (int)((char *)stack + USPACE - 16); 874 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 875 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 876 tss->__tss_eip = (int)func; 877 } 878 879 /* XXX */ 880 #define IDTVEC(name) __CONCAT(X, name) 881 typedef void (vector)(void); 882 extern vector IDTVEC(tss_trap08); 883 #ifdef DDB 884 extern vector Xintrddbipi; 885 extern int ddb_vec; 886 #endif 887 888 static void 889 cpu_set_tss_gates(struct cpu_info *ci) 890 { 891 struct segment_descriptor sd; 892 893 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 894 UVM_KMF_WIRED); 895 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 896 IDTVEC(tss_trap08)); 897 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 898 SDT_SYS386TSS, SEL_KPL, 0, 0); 899 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 900 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 901 GSEL(GTRAPTSS_SEL, SEL_KPL)); 902 903 #if defined(DDB) 904 /* 905 * Set up separate handler for the DDB IPI, so that it doesn't 906 * stomp on a possibly corrupted stack. 907 * 908 * XXX overwriting the gate set in db_machine_init. 909 * Should rearrange the code so that it's set only once. 910 */ 911 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 912 UVM_KMF_WIRED); 913 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi); 914 915 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 916 SDT_SYS386TSS, SEL_KPL, 0, 0); 917 ci->ci_gdt[GIPITSS_SEL].sd = sd; 918 919 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 920 GSEL(GIPITSS_SEL, SEL_KPL)); 921 #endif 922 } 923 #else 924 static void 925 cpu_set_tss_gates(struct cpu_info *ci) 926 { 927 928 } 929 #endif /* i386 */ 930 931 int 932 mp_cpu_start(struct cpu_info *ci, paddr_t target) 933 { 934 unsigned short dwordptr[2]; 935 int error; 936 937 /* 938 * Bootstrap code must be addressable in real mode 939 * and it must be page aligned. 940 */ 941 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 942 943 /* 944 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 945 */ 946 947 outb(IO_RTC, NVRAM_RESET); 948 outb(IO_RTC+1, NVRAM_RESET_JUMP); 949 950 /* 951 * "and the warm reset vector (DWORD based at 40:67) to point 952 * to the AP startup code ..." 953 */ 954 955 dwordptr[0] = 0; 956 dwordptr[1] = target >> 4; 957 958 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 959 960 if ((cpu_feature[0] & CPUID_APIC) == 0) { 961 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 962 return ENODEV; 963 } 964 965 /* 966 * ... prior to executing the following sequence:". We'll also add in 967 * local cache flush, in case the BIOS has left the AP with its cache 968 * disabled. It may not be able to cope with MP coherency. 969 */ 970 wbinvd(); 971 972 if (ci->ci_flags & CPUF_AP) { 973 error = x86_ipi_init(ci->ci_cpuid); 974 if (error != 0) { 975 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 976 __func__); 977 return error; 978 } 979 i8254_delay(10000); 980 981 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 982 if (error != 0) { 983 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 984 __func__); 985 return error; 986 } 987 i8254_delay(200); 988 989 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 990 if (error != 0) { 991 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 992 __func__); 993 return error; 994 } 995 i8254_delay(200); 996 } 997 998 return 0; 999 } 1000 1001 void 1002 mp_cpu_start_cleanup(struct cpu_info *ci) 1003 { 1004 /* 1005 * Ensure the NVRAM reset byte contains something vaguely sane. 1006 */ 1007 1008 outb(IO_RTC, NVRAM_RESET); 1009 outb(IO_RTC+1, NVRAM_RESET_RST); 1010 } 1011 1012 #ifdef __x86_64__ 1013 typedef void (vector)(void); 1014 extern vector Xsyscall, Xsyscall32; 1015 #endif 1016 1017 void 1018 cpu_init_msrs(struct cpu_info *ci, bool full) 1019 { 1020 #ifdef __x86_64__ 1021 wrmsr(MSR_STAR, 1022 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1023 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1024 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1025 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1026 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 1027 1028 if (full) { 1029 wrmsr(MSR_FSBASE, 0); 1030 wrmsr(MSR_GSBASE, (uint64_t)ci); 1031 wrmsr(MSR_KERNELGSBASE, 0); 1032 } 1033 #endif /* __x86_64__ */ 1034 1035 if (cpu_feature[2] & CPUID_NOX) 1036 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1037 } 1038 1039 void 1040 cpu_offline_md(void) 1041 { 1042 int s; 1043 1044 s = splhigh(); 1045 #ifdef i386 1046 #if NNPX > 0 1047 npxsave_cpu(true); 1048 #endif 1049 #else 1050 fpusave_cpu(true); 1051 #endif 1052 splx(s); 1053 } 1054 1055 /* XXX joerg restructure and restart CPUs individually */ 1056 static bool 1057 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1058 { 1059 struct cpu_softc *sc = device_private(dv); 1060 struct cpu_info *ci = sc->sc_info; 1061 int err; 1062 1063 if (ci->ci_flags & CPUF_PRIMARY) 1064 return true; 1065 if (ci->ci_data.cpu_idlelwp == NULL) 1066 return true; 1067 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1068 return true; 1069 1070 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1071 1072 if (sc->sc_wasonline) { 1073 mutex_enter(&cpu_lock); 1074 err = cpu_setstate(ci, false); 1075 mutex_exit(&cpu_lock); 1076 1077 if (err) 1078 return false; 1079 } 1080 1081 return true; 1082 } 1083 1084 static bool 1085 cpu_resume(device_t dv, const pmf_qual_t *qual) 1086 { 1087 struct cpu_softc *sc = device_private(dv); 1088 struct cpu_info *ci = sc->sc_info; 1089 int err = 0; 1090 1091 if (ci->ci_flags & CPUF_PRIMARY) 1092 return true; 1093 if (ci->ci_data.cpu_idlelwp == NULL) 1094 return true; 1095 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1096 return true; 1097 1098 if (sc->sc_wasonline) { 1099 mutex_enter(&cpu_lock); 1100 err = cpu_setstate(ci, true); 1101 mutex_exit(&cpu_lock); 1102 } 1103 1104 return err == 0; 1105 } 1106 1107 static bool 1108 cpu_shutdown(device_t dv, int how) 1109 { 1110 return cpu_suspend(dv, NULL); 1111 } 1112 1113 void 1114 cpu_get_tsc_freq(struct cpu_info *ci) 1115 { 1116 uint64_t last_tsc; 1117 1118 if (cpu_hascounter()) { 1119 last_tsc = cpu_counter_serializing(); 1120 i8254_delay(100000); 1121 ci->ci_data.cpu_cc_freq = 1122 (cpu_counter_serializing() - last_tsc) * 10; 1123 } 1124 } 1125 1126 void 1127 x86_cpu_idle_mwait(void) 1128 { 1129 struct cpu_info *ci = curcpu(); 1130 1131 KASSERT(ci->ci_ilevel == IPL_NONE); 1132 1133 x86_monitor(&ci->ci_want_resched, 0, 0); 1134 if (__predict_false(ci->ci_want_resched)) { 1135 return; 1136 } 1137 x86_mwait(0, 0); 1138 } 1139 1140 void 1141 x86_cpu_idle_halt(void) 1142 { 1143 struct cpu_info *ci = curcpu(); 1144 1145 KASSERT(ci->ci_ilevel == IPL_NONE); 1146 1147 x86_disable_intr(); 1148 if (!__predict_false(ci->ci_want_resched)) { 1149 x86_stihlt(); 1150 } else { 1151 x86_enable_intr(); 1152 } 1153 } 1154 1155 /* 1156 * Loads pmap for the current CPU. 1157 */ 1158 void 1159 cpu_load_pmap(struct pmap *pmap) 1160 { 1161 #ifdef PAE 1162 int i, s; 1163 struct cpu_info *ci; 1164 1165 s = splvm(); /* just to be safe */ 1166 ci = curcpu(); 1167 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1168 for (i = 0 ; i < PDP_SIZE; i++) { 1169 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1170 } 1171 splx(s); 1172 tlbflush(); 1173 #else /* PAE */ 1174 lcr3(pmap_pdirpa(pmap, 0)); 1175 #endif /* PAE */ 1176 } 1177
Indexes created Mon Sep 29 21:09:56 GMT 2025