intr.h revision 1.9
1 /* $NetBSD: intr.h,v 1.9 2006/02/16 20:17:15 perry Exp $ */ 2 /* NetBSD intr.h,v 1.15 2004/10/31 10:39:34 yamt Exp */ 3 4 /*- 5 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, and by Jason R. Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _XEN_INTR_H_ 41 #define _XEN_INTR_H_ 42 43 #include <machine/intrdefs.h> 44 45 #ifndef _LOCORE 46 #include <machine/cpu.h> 47 #include <machine/pic.h> 48 49 /* 50 * Struct describing an event channel. 51 */ 52 53 struct evtsource { 54 int ev_maxlevel; /* max. IPL for this source */ 55 u_int32_t ev_imask; /* interrupt mask */ 56 struct intrhand *ev_handlers; /* handler chain */ 57 struct evcnt ev_evcnt; /* interrupt counter */ 58 char ev_evname[32]; /* event counter name */ 59 }; 60 61 /* 62 * Structure describing an interrupt level. struct cpu_info has an array of 63 * IPL_MAX of theses. The index in the array is equal to the stub number of 64 * the stubcode as present in vector.s 65 */ 66 67 struct intrstub { 68 #if 0 69 void *ist_entry; 70 #endif 71 void *ist_recurse; 72 void *ist_resume; 73 }; 74 75 struct iplsource { 76 struct intrhand *ipl_handlers; /* handler chain */ 77 void *ipl_recurse; /* entry for spllower */ 78 void *ipl_resume; /* entry for doreti */ 79 u_int32_t ipl_evt_mask1; /* pending events for this IPL */ 80 u_int32_t ipl_evt_mask2[NR_EVENT_CHANNELS]; 81 }; 82 83 84 85 /* 86 * Interrupt handler chains. These are linked in both the evtsource and 87 * the iplsource. 88 * The handler is called with its (single) argument. 89 */ 90 91 struct intrhand { 92 int (*ih_fun)(void *); 93 void *ih_arg; 94 int ih_level; 95 struct intrhand *ih_ipl_next; 96 struct intrhand *ih_evt_next; 97 struct cpu_info *ih_cpu; 98 }; 99 100 101 extern struct intrstub xenev_stubs[]; 102 103 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 104 105 extern void Xspllower(int); 106 107 static __inline int splraise(int); 108 static __inline void spllower(int); 109 static __inline void softintr(int); 110 111 /* 112 * Add a mask to cpl, and return the old value of cpl. 113 */ 114 static __inline int 115 splraise(int nlevel) 116 { 117 int olevel; 118 struct cpu_info *ci = curcpu(); 119 120 olevel = ci->ci_ilevel; 121 if (nlevel > olevel) 122 ci->ci_ilevel = nlevel; 123 __insn_barrier(); 124 return (olevel); 125 } 126 127 /* 128 * Restore a value to cpl (unmasking interrupts). If any unmasked 129 * interrupts are pending, call Xspllower() to process them. 130 */ 131 static __inline void 132 spllower(int nlevel) 133 { 134 struct cpu_info *ci = curcpu(); 135 u_int32_t imask; 136 u_long psl; 137 138 __insn_barrier(); 139 140 imask = IUNMASK(ci, nlevel); 141 psl = read_psl(); 142 disable_intr(); 143 if (ci->ci_ipending & imask) { 144 Xspllower(nlevel); 145 /* Xspllower does enable_intr() */ 146 } else { 147 ci->ci_ilevel = nlevel; 148 write_psl(psl); 149 } 150 } 151 152 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 153 154 /* 155 * Software interrupt masks 156 * 157 * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from 158 * clock to softclock before it calls softclock(). 159 */ 160 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 161 162 #define splsoftxenevt() splraise(IPL_SOFTXENEVT) 163 164 /* 165 * Miscellaneous 166 */ 167 #define spl0() spllower(IPL_NONE) 168 #define splraiseipl(x) splraise(x) 169 #define splx(x) spllower(x) 170 171 #include <sys/spl.h> 172 173 /* 174 * Software interrupt registration 175 * 176 * We hand-code this to ensure that it's atomic. 177 * 178 * XXX always scheduled on the current CPU. 179 */ 180 static __inline void 181 softintr(int sir) 182 { 183 struct cpu_info *ci = curcpu(); 184 185 __asm volatile("lock ; orl %1, %0" : 186 "=m"(ci->ci_ipending) : "ir" (1 << sir)); 187 } 188 189 /* 190 * XXX 191 */ 192 #define setsoftnet() softintr(SIR_NET) 193 194 /* 195 * Stub declarations. 196 */ 197 198 extern void Xsoftclock(void); 199 extern void Xsoftnet(void); 200 extern void Xsoftserial(void); 201 extern void Xsoftxenevt(void); 202 203 struct cpu_info; 204 205 extern char idt_allocmap[]; 206 207 struct pcibus_attach_args; 208 209 void intr_default_setup(void); 210 int x86_nmi(void); 211 void intr_calculatemasks(struct evtsource *); 212 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 213 void intr_disestablish(struct intrhand *); 214 const char *intr_string(int); 215 void cpu_intr_init(struct cpu_info *); 216 #ifdef INTRDEBUG 217 void intr_printconfig(void); 218 #endif 219 220 #endif /* !_LOCORE */ 221 222 /* 223 * Generic software interrupt support. 224 */ 225 226 #define X86_SOFTINTR_SOFTCLOCK 0 227 #define X86_SOFTINTR_SOFTNET 1 228 #define X86_SOFTINTR_SOFTSERIAL 2 229 #define X86_NSOFTINTR 3 230 231 #ifndef _LOCORE 232 #include <sys/queue.h> 233 234 struct x86_soft_intrhand { 235 TAILQ_ENTRY(x86_soft_intrhand) 236 sih_q; 237 struct x86_soft_intr *sih_intrhead; 238 void (*sih_fn)(void *); 239 void *sih_arg; 240 int sih_pending; 241 }; 242 243 struct x86_soft_intr { 244 TAILQ_HEAD(, x86_soft_intrhand) 245 softintr_q; 246 int softintr_ssir; 247 struct simplelock softintr_slock; 248 }; 249 250 #define x86_softintr_lock(si, s) \ 251 do { \ 252 (s) = splhigh(); \ 253 simple_lock(&si->softintr_slock); \ 254 } while (/*CONSTCOND*/ 0) 255 256 #define x86_softintr_unlock(si, s) \ 257 do { \ 258 simple_unlock(&si->softintr_slock); \ 259 splx((s)); \ 260 } while (/*CONSTCOND*/ 0) 261 262 void *softintr_establish(int, void (*)(void *), void *); 263 void softintr_disestablish(void *); 264 void softintr_init(void); 265 void softintr_dispatch(int); 266 267 #define softintr_schedule(arg) \ 268 do { \ 269 struct x86_soft_intrhand *__sih = (arg); \ 270 struct x86_soft_intr *__si = __sih->sih_intrhead; \ 271 int __s; \ 272 \ 273 x86_softintr_lock(__si, __s); \ 274 if (__sih->sih_pending == 0) { \ 275 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 276 __sih->sih_pending = 1; \ 277 softintr(__si->softintr_ssir); \ 278 } \ 279 x86_softintr_unlock(__si, __s); \ 280 } while (/*CONSTCOND*/ 0) 281 #endif /* _LOCORE */ 282 283 #endif /* _XEN_INTR_H_ */ 284
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