Home | History | Annotate | Line # | Download | only in x86
cpu.c revision 1.37
      1  1.37   rmind /*	$NetBSD: cpu.c,v 1.37 2009/11/21 05:54:04 rmind Exp $	*/
      2   1.2  bouyer /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp  */
      3   1.2  bouyer 
      4   1.2  bouyer /*-
      5   1.2  bouyer  * Copyright (c) 2000 The NetBSD Foundation, Inc.
      6  1.19   joerg  * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
      7   1.2  bouyer  * All rights reserved.
      8   1.2  bouyer  *
      9   1.2  bouyer  * This code is derived from software contributed to The NetBSD Foundation
     10   1.2  bouyer  * by RedBack Networks Inc.
     11   1.2  bouyer  *
     12   1.2  bouyer  * Author: Bill Sommerfeld
     13   1.2  bouyer  *
     14   1.2  bouyer  * Redistribution and use in source and binary forms, with or without
     15   1.2  bouyer  * modification, are permitted provided that the following conditions
     16   1.2  bouyer  * are met:
     17   1.2  bouyer  * 1. Redistributions of source code must retain the above copyright
     18   1.2  bouyer  *    notice, this list of conditions and the following disclaimer.
     19   1.2  bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     20   1.2  bouyer  *    notice, this list of conditions and the following disclaimer in the
     21   1.2  bouyer  *    documentation and/or other materials provided with the distribution.
     22   1.2  bouyer  *
     23   1.2  bouyer  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     24   1.2  bouyer  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     25   1.2  bouyer  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     26   1.2  bouyer  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     27   1.2  bouyer  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     28   1.2  bouyer  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     29   1.2  bouyer  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     30   1.2  bouyer  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     31   1.2  bouyer  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     32   1.2  bouyer  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     33   1.2  bouyer  * POSSIBILITY OF SUCH DAMAGE.
     34   1.2  bouyer  */
     35   1.2  bouyer 
     36   1.2  bouyer /*
     37   1.2  bouyer  * Copyright (c) 1999 Stefan Grefen
     38   1.2  bouyer  *
     39   1.2  bouyer  * Redistribution and use in source and binary forms, with or without
     40   1.2  bouyer  * modification, are permitted provided that the following conditions
     41   1.2  bouyer  * are met:
     42   1.2  bouyer  * 1. Redistributions of source code must retain the above copyright
     43   1.2  bouyer  *    notice, this list of conditions and the following disclaimer.
     44   1.2  bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     45   1.2  bouyer  *    notice, this list of conditions and the following disclaimer in the
     46   1.2  bouyer  *    documentation and/or other materials provided with the distribution.
     47   1.2  bouyer  * 3. All advertising materials mentioning features or use of this software
     48   1.2  bouyer  *    must display the following acknowledgement:
     49   1.2  bouyer  *      This product includes software developed by the NetBSD
     50   1.2  bouyer  *      Foundation, Inc. and its contributors.
     51   1.2  bouyer  * 4. Neither the name of The NetBSD Foundation nor the names of its
     52   1.2  bouyer  *    contributors may be used to endorse or promote products derived
     53   1.2  bouyer  *    from this software without specific prior written permission.
     54   1.2  bouyer  *
     55   1.2  bouyer  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
     56   1.2  bouyer  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     57   1.2  bouyer  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     58   1.2  bouyer  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
     59   1.2  bouyer  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     60   1.2  bouyer  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     61   1.2  bouyer  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     62   1.2  bouyer  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     63   1.2  bouyer  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     64   1.2  bouyer  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     65   1.2  bouyer  * SUCH DAMAGE.
     66   1.2  bouyer  */
     67   1.2  bouyer 
     68   1.2  bouyer #include <sys/cdefs.h>
     69  1.37   rmind __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2009/11/21 05:54:04 rmind Exp $");
     70   1.2  bouyer 
     71   1.2  bouyer #include "opt_ddb.h"
     72   1.2  bouyer #include "opt_multiprocessor.h"
     73   1.2  bouyer #include "opt_mpbios.h"		/* for MPDEBUG */
     74   1.2  bouyer #include "opt_mtrr.h"
     75   1.2  bouyer #include "opt_xen.h"
     76   1.2  bouyer 
     77   1.2  bouyer #include "lapic.h"
     78   1.2  bouyer #include "ioapic.h"
     79   1.2  bouyer 
     80   1.2  bouyer #include <sys/param.h>
     81   1.2  bouyer #include <sys/proc.h>
     82   1.2  bouyer #include <sys/user.h>
     83   1.2  bouyer #include <sys/systm.h>
     84   1.2  bouyer #include <sys/device.h>
     85  1.31  cegger #include <sys/kmem.h>
     86  1.11  cegger #include <sys/cpu.h>
     87  1.11  cegger #include <sys/atomic.h>
     88  1.32  cegger #include <sys/reboot.h>
     89   1.2  bouyer 
     90   1.2  bouyer #include <uvm/uvm_extern.h>
     91   1.2  bouyer 
     92   1.2  bouyer #include <machine/cpufunc.h>
     93   1.2  bouyer #include <machine/cpuvar.h>
     94   1.2  bouyer #include <machine/pmap.h>
     95   1.2  bouyer #include <machine/vmparam.h>
     96   1.2  bouyer #include <machine/mpbiosvar.h>
     97   1.2  bouyer #include <machine/pcb.h>
     98   1.2  bouyer #include <machine/specialreg.h>
     99   1.2  bouyer #include <machine/segments.h>
    100   1.2  bouyer #include <machine/gdt.h>
    101   1.2  bouyer #include <machine/mtrr.h>
    102   1.2  bouyer #include <machine/pio.h>
    103   1.2  bouyer 
    104   1.2  bouyer #include <xen/vcpuvar.h>
    105   1.2  bouyer 
    106   1.2  bouyer #if NLAPIC > 0
    107   1.2  bouyer #include <machine/apicvar.h>
    108   1.2  bouyer #include <machine/i82489reg.h>
    109   1.2  bouyer #include <machine/i82489var.h>
    110   1.2  bouyer #endif
    111   1.2  bouyer 
    112   1.2  bouyer #include <dev/ic/mc146818reg.h>
    113   1.2  bouyer #include <dev/isa/isareg.h>
    114   1.2  bouyer 
    115  1.27      ad #define	X86_MAXPROCS	32
    116  1.27      ad 
    117  1.10  cegger int     cpu_match(device_t, cfdata_t, void *);
    118  1.10  cegger void    cpu_attach(device_t, device_t, void *);
    119  1.10  cegger int     vcpu_match(device_t, cfdata_t, void *);
    120  1.10  cegger void    vcpu_attach(device_t, device_t, void *);
    121  1.10  cegger void    cpu_attach_common(device_t, device_t, void *);
    122   1.8  dogcow void	cpu_offline_md(void);
    123   1.2  bouyer 
    124   1.2  bouyer struct cpu_softc {
    125  1.10  cegger 	device_t sc_dev;		/* device tree glue */
    126   1.2  bouyer 	struct cpu_info *sc_info;	/* pointer to CPU info */
    127  1.32  cegger 	bool sc_wasonline;
    128   1.2  bouyer };
    129   1.2  bouyer 
    130   1.5   joerg int mp_cpu_start(struct cpu_info *, paddr_t);
    131   1.2  bouyer void mp_cpu_start_cleanup(struct cpu_info *);
    132   1.2  bouyer const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL,
    133   1.2  bouyer 				      mp_cpu_start_cleanup };
    134   1.2  bouyer 
    135  1.10  cegger CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
    136   1.2  bouyer     cpu_match, cpu_attach, NULL, NULL);
    137  1.10  cegger CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc),
    138   1.2  bouyer     vcpu_match, vcpu_attach, NULL, NULL);
    139   1.2  bouyer 
    140   1.2  bouyer /*
    141   1.2  bouyer  * Statically-allocated CPU info for the primary CPU (or the only
    142   1.2  bouyer  * CPU, on uniprocessors).  The CPU info list is initialized to
    143   1.2  bouyer  * point at it.
    144   1.2  bouyer  */
    145   1.2  bouyer #ifdef TRAPLOG
    146   1.2  bouyer #include <machine/tlog.h>
    147   1.2  bouyer struct tlog tlog_primary;
    148   1.2  bouyer #endif
    149   1.2  bouyer struct cpu_info cpu_info_primary = {
    150   1.7  bouyer 	.ci_dev = 0,
    151   1.2  bouyer 	.ci_self = &cpu_info_primary,
    152   1.4  bouyer 	.ci_idepth = -1,
    153   1.2  bouyer 	.ci_curlwp = &lwp0,
    154  1.25      ad 	.ci_curldt = -1,
    155   1.2  bouyer #ifdef TRAPLOG
    156   1.2  bouyer 	.ci_tlog = &tlog_primary,
    157   1.2  bouyer #endif
    158   1.2  bouyer 
    159   1.2  bouyer };
    160   1.2  bouyer struct cpu_info phycpu_info_primary = {
    161   1.7  bouyer 	.ci_dev = 0,
    162   1.2  bouyer 	.ci_self = &phycpu_info_primary,
    163   1.2  bouyer };
    164   1.2  bouyer 
    165   1.2  bouyer struct cpu_info *cpu_info_list = &cpu_info_primary;
    166   1.2  bouyer 
    167   1.2  bouyer static void	cpu_set_tss_gates(struct cpu_info *ci);
    168   1.2  bouyer 
    169  1.11  cegger uint32_t cpus_attached = 0;
    170  1.11  cegger uint32_t cpus_running = 0;
    171  1.11  cegger 
    172  1.11  cegger bool x86_mp_online;
    173  1.11  cegger paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
    174   1.2  bouyer 
    175   1.2  bouyer struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary };
    176   1.2  bouyer 
    177   1.2  bouyer #ifdef MULTIPROCESSOR
    178   1.2  bouyer /*
    179   1.2  bouyer  * Array of CPU info structures.  Must be statically-allocated because
    180   1.2  bouyer  * curproc, etc. are used early.
    181   1.2  bouyer  */
    182   1.2  bouyer struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary };
    183   1.2  bouyer 
    184   1.2  bouyer void    	cpu_hatch(void *);
    185   1.2  bouyer static void    	cpu_boot_secondary(struct cpu_info *ci);
    186   1.2  bouyer static void    	cpu_start_secondary(struct cpu_info *ci);
    187   1.2  bouyer static void	cpu_copy_trampoline(void);
    188   1.2  bouyer 
    189   1.2  bouyer /*
    190   1.2  bouyer  * Runs once per boot once multiprocessor goo has been detected and
    191   1.2  bouyer  * the local APIC on the boot processor has been mapped.
    192   1.2  bouyer  *
    193   1.2  bouyer  * Called from lapic_boot_init() (from mpbios_scan()).
    194   1.2  bouyer  */
    195   1.2  bouyer void
    196  1.10  cegger cpu_init_first(void)
    197   1.2  bouyer {
    198   1.2  bouyer 	int cpunum = lapic_cpu_number();
    199   1.2  bouyer 
    200   1.2  bouyer 	if (cpunum != 0) {
    201   1.2  bouyer 		cpu_info[0] = NULL;
    202   1.2  bouyer 		cpu_info[cpunum] = &cpu_info_primary;
    203   1.2  bouyer 	}
    204   1.2  bouyer 
    205   1.2  bouyer 	cpu_copy_trampoline();
    206   1.2  bouyer }
    207   1.2  bouyer #endif
    208   1.2  bouyer 
    209   1.2  bouyer int
    210  1.10  cegger cpu_match(device_t parent, cfdata_t match, void *aux)
    211   1.2  bouyer {
    212   1.2  bouyer 
    213   1.2  bouyer 	return 1;
    214   1.2  bouyer }
    215   1.2  bouyer 
    216   1.2  bouyer void
    217  1.10  cegger cpu_attach(device_t parent, device_t self, void *aux)
    218   1.2  bouyer {
    219  1.10  cegger 	struct cpu_softc *sc = device_private(self);
    220   1.2  bouyer 	struct cpu_attach_args *caa = aux;
    221   1.2  bouyer 	struct cpu_info *ci;
    222  1.34  cegger 	uintptr_t ptr;
    223   1.2  bouyer 	int cpunum = caa->cpu_number;
    224   1.2  bouyer 
    225  1.10  cegger 	sc->sc_dev = self;
    226  1.10  cegger 
    227  1.34  cegger 	if (cpus_attached == ~0) {
    228  1.34  cegger 		aprint_error(": increase MAXCPUS\n");
    229  1.34  cegger 		return;
    230  1.34  cegger 	}
    231  1.34  cegger 
    232   1.2  bouyer 	/*
    233   1.2  bouyer 	 * If we're an Application Processor, allocate a cpu_info
    234   1.2  bouyer 	 * structure, otherwise use the primary's.
    235   1.2  bouyer 	 */
    236   1.2  bouyer 	if (caa->cpu_role == CPU_ROLE_AP) {
    237  1.32  cegger 		if ((boothowto & RB_MD1) != 0) {
    238  1.32  cegger 			aprint_error(": multiprocessor boot disabled\n");
    239  1.32  cegger 			if (!pmf_device_register(self, NULL, NULL))
    240  1.32  cegger 				aprint_error_dev(self,
    241  1.32  cegger 				   "couldn't establish power handler\n");
    242  1.32  cegger 			return;
    243  1.32  cegger 		}
    244  1.32  cegger 		aprint_naive(": Application Processor\n");
    245  1.34  cegger 		ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
    246  1.34  cegger 		    KM_SLEEP);
    247  1.34  cegger 		ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) &
    248  1.34  cegger 		    ~(CACHE_LINE_SIZE - 1));
    249  1.24      ad 		ci->ci_curldt = -1;
    250   1.2  bouyer 		if (phycpu_info[cpunum] != NULL)
    251   1.2  bouyer 			panic("cpu at apic id %d already attached?", cpunum);
    252   1.2  bouyer 		phycpu_info[cpunum] = ci;
    253   1.2  bouyer 	} else {
    254  1.32  cegger 		aprint_naive(": %s Processor\n",
    255  1.32  cegger 		    caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
    256   1.2  bouyer 		ci = &phycpu_info_primary;
    257   1.2  bouyer 		if (cpunum != 0) {
    258   1.2  bouyer 			phycpu_info[0] = NULL;
    259   1.2  bouyer 			phycpu_info[cpunum] = ci;
    260   1.2  bouyer 		}
    261   1.2  bouyer 	}
    262   1.2  bouyer 
    263   1.2  bouyer 	ci->ci_self = ci;
    264   1.2  bouyer 	sc->sc_info = ci;
    265   1.2  bouyer 
    266   1.2  bouyer 	ci->ci_dev = self;
    267  1.23      ad 	ci->ci_cpuid = caa->cpu_number;
    268  1.16  cegger 	ci->ci_vcpu = NULL;
    269   1.2  bouyer 
    270   1.2  bouyer 	printf(": ");
    271   1.2  bouyer 	switch (caa->cpu_role) {
    272   1.2  bouyer 	case CPU_ROLE_SP:
    273   1.2  bouyer 		printf("(uniprocessor)\n");
    274  1.34  cegger 		atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY);
    275   1.2  bouyer 		break;
    276   1.2  bouyer 
    277   1.2  bouyer 	case CPU_ROLE_BP:
    278   1.2  bouyer 		printf("(boot processor)\n");
    279  1.34  cegger 		atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY);
    280   1.2  bouyer 		break;
    281   1.2  bouyer 
    282   1.2  bouyer 	case CPU_ROLE_AP:
    283   1.2  bouyer 		/*
    284   1.2  bouyer 		 * report on an AP
    285   1.2  bouyer 		 */
    286   1.2  bouyer 		printf("(application processor)\n");
    287   1.2  bouyer 		break;
    288   1.2  bouyer 
    289   1.2  bouyer 	default:
    290   1.2  bouyer 		panic("unknown processor type??\n");
    291   1.2  bouyer 	}
    292  1.34  cegger 
    293  1.34  cegger 	atomic_or_32(&cpus_attached, ci->ci_cpumask);
    294  1.34  cegger 
    295   1.2  bouyer 	return;
    296   1.2  bouyer }
    297   1.2  bouyer 
    298   1.2  bouyer int
    299  1.10  cegger vcpu_match(device_t parent, cfdata_t match, void *aux)
    300   1.2  bouyer {
    301   1.2  bouyer 	struct vcpu_attach_args *vcaa = aux;
    302   1.2  bouyer 
    303   1.2  bouyer 	if (strcmp(vcaa->vcaa_name, match->cf_name) == 0)
    304   1.2  bouyer 		return 1;
    305   1.2  bouyer 	return 0;
    306   1.2  bouyer }
    307   1.2  bouyer 
    308   1.2  bouyer void
    309  1.10  cegger vcpu_attach(device_t parent, device_t self, void *aux)
    310   1.2  bouyer {
    311   1.2  bouyer 	struct vcpu_attach_args *vcaa = aux;
    312   1.2  bouyer 
    313   1.2  bouyer 	cpu_attach_common(parent, self, &vcaa->vcaa_caa);
    314   1.2  bouyer }
    315   1.2  bouyer 
    316   1.2  bouyer static void
    317   1.2  bouyer cpu_vm_init(struct cpu_info *ci)
    318   1.2  bouyer {
    319   1.2  bouyer 	int ncolors = 2, i;
    320   1.2  bouyer 
    321   1.2  bouyer 	for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
    322   1.2  bouyer 		struct x86_cache_info *cai;
    323   1.2  bouyer 		int tcolors;
    324   1.2  bouyer 
    325   1.2  bouyer 		cai = &ci->ci_cinfo[i];
    326   1.2  bouyer 
    327   1.2  bouyer 		tcolors = atop(cai->cai_totalsize);
    328   1.2  bouyer 		switch(cai->cai_associativity) {
    329   1.2  bouyer 		case 0xff:
    330   1.2  bouyer 			tcolors = 1; /* fully associative */
    331   1.2  bouyer 			break;
    332   1.2  bouyer 		case 0:
    333   1.2  bouyer 		case 1:
    334   1.2  bouyer 			break;
    335   1.2  bouyer 		default:
    336   1.2  bouyer 			tcolors /= cai->cai_associativity;
    337   1.2  bouyer 		}
    338   1.2  bouyer 		ncolors = max(ncolors, tcolors);
    339   1.2  bouyer 	}
    340   1.2  bouyer 
    341   1.2  bouyer 	/*
    342   1.2  bouyer 	 * Knowing the size of the largest cache on this CPU, re-color
    343   1.2  bouyer 	 * our pages.
    344   1.2  bouyer 	 */
    345   1.2  bouyer 	if (ncolors <= uvmexp.ncolors)
    346   1.2  bouyer 		return;
    347  1.28  bouyer 	aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors);
    348   1.2  bouyer 	uvm_page_recolor(ncolors);
    349   1.2  bouyer }
    350   1.2  bouyer 
    351   1.2  bouyer void
    352  1.11  cegger cpu_attach_common(device_t parent, device_t self, void *aux)
    353   1.2  bouyer {
    354  1.10  cegger 	struct cpu_softc *sc = device_private(self);
    355   1.2  bouyer 	struct cpu_attach_args *caa = aux;
    356   1.2  bouyer 	struct cpu_info *ci;
    357  1.12  cegger 	uintptr_t ptr;
    358   1.2  bouyer 	int cpunum = caa->cpu_number;
    359   1.2  bouyer 
    360  1.10  cegger 	sc->sc_dev = self;
    361  1.10  cegger 
    362   1.2  bouyer 	/*
    363   1.2  bouyer 	 * If we're an Application Processor, allocate a cpu_info
    364   1.2  bouyer 	 * structure, otherwise use the primary's.
    365   1.2  bouyer 	 */
    366   1.2  bouyer 	if (caa->cpu_role == CPU_ROLE_AP) {
    367  1.17  cegger 		if (cpunum >= X86_MAXPROCS) {
    368  1.17  cegger 			aprint_error(": apic id %d ignored, "
    369  1.17  cegger 				"please increase X86_MAXPROCS\n", cpunum);
    370  1.17  cegger 		}
    371  1.17  cegger 
    372  1.12  cegger 		aprint_naive(": Application Processor\n");
    373  1.31  cegger 		ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
    374  1.31  cegger 		    KM_SLEEP);
    375  1.12  cegger 		ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) &
    376  1.12  cegger 		    ~(CACHE_LINE_SIZE - 1));
    377  1.12  cegger 		memset(ci, 0, sizeof(*ci));
    378   1.2  bouyer #if defined(MULTIPROCESSOR)
    379   1.2  bouyer 		if (cpu_info[cpunum] != NULL)
    380   1.2  bouyer 			panic("cpu at apic id %d already attached?", cpunum);
    381   1.2  bouyer 		cpu_info[cpunum] = ci;
    382   1.2  bouyer #endif
    383   1.2  bouyer #ifdef TRAPLOG
    384  1.31  cegger 		ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP);
    385   1.2  bouyer #endif
    386   1.2  bouyer 	} else {
    387  1.12  cegger 		aprint_naive(": %s Processor\n",
    388  1.12  cegger 		    caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
    389   1.2  bouyer 		ci = &cpu_info_primary;
    390   1.2  bouyer #if defined(MULTIPROCESSOR)
    391   1.2  bouyer 		if (cpunum != lapic_cpu_number()) {
    392   1.2  bouyer 			panic("%s: running CPU is at apic %d"
    393   1.2  bouyer 			    " instead of at expected %d",
    394   1.9  cegger 			    device_xname(sc->sc_dev), lapic_cpu_number(), cpunum);
    395   1.2  bouyer 		}
    396   1.2  bouyer #endif
    397   1.2  bouyer 	}
    398   1.2  bouyer 
    399   1.2  bouyer 	ci->ci_self = ci;
    400   1.2  bouyer 	sc->sc_info = ci;
    401   1.2  bouyer 
    402   1.2  bouyer 	ci->ci_dev = self;
    403  1.23      ad 	ci->ci_cpuid = cpunum;
    404  1.16  cegger 
    405  1.16  cegger 	KASSERT(HYPERVISOR_shared_info != NULL);
    406  1.16  cegger 	ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum];
    407  1.16  cegger 
    408   1.2  bouyer 	ci->ci_func = caa->cpu_func;
    409   1.2  bouyer 
    410   1.2  bouyer 	if (caa->cpu_role == CPU_ROLE_AP) {
    411   1.2  bouyer #if defined(MULTIPROCESSOR)
    412   1.2  bouyer 		int error;
    413   1.2  bouyer 
    414   1.2  bouyer 		error = mi_cpu_attach(ci);
    415   1.2  bouyer 		if (error != 0) {
    416   1.2  bouyer 			aprint_normal("\n");
    417  1.10  cegger 			aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n",
    418   1.9  cegger 			    error);
    419   1.2  bouyer 			return;
    420   1.2  bouyer 		}
    421   1.2  bouyer #endif
    422   1.2  bouyer 	} else {
    423   1.2  bouyer 		KASSERT(ci->ci_data.cpu_idlelwp != NULL);
    424   1.2  bouyer 	}
    425   1.2  bouyer 
    426  1.23      ad 	ci->ci_cpumask = (1 << cpu_index(ci));
    427   1.2  bouyer 	pmap_reference(pmap_kernel());
    428   1.2  bouyer 	ci->ci_pmap = pmap_kernel();
    429   1.2  bouyer 	ci->ci_tlbstate = TLBSTATE_STALE;
    430   1.2  bouyer 
    431   1.2  bouyer 	/* further PCB init done later. */
    432   1.2  bouyer 
    433   1.2  bouyer 	switch (caa->cpu_role) {
    434   1.2  bouyer 	case CPU_ROLE_SP:
    435  1.12  cegger 		atomic_or_32(&ci->ci_flags,
    436  1.12  cegger 		     CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY);
    437   1.2  bouyer 		cpu_intr_init(ci);
    438  1.21      ad 		cpu_get_tsc_freq(ci);
    439  1.21      ad 		cpu_identify(ci);
    440   1.2  bouyer 		cpu_init(ci);
    441   1.2  bouyer 		cpu_set_tss_gates(ci);
    442  1.12  cegger 		pmap_cpu_init_late(ci);
    443  1.26  bouyer 		x86_cpu_idle_init();
    444  1.12  cegger #if 0
    445  1.12  cegger 		x86_errata();
    446  1.12  cegger #endif
    447   1.2  bouyer 		break;
    448   1.2  bouyer 
    449   1.2  bouyer 	case CPU_ROLE_BP:
    450  1.12  cegger 		atomic_or_32(&ci->ci_flags,
    451  1.12  cegger 		    CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY);
    452   1.2  bouyer 		cpu_intr_init(ci);
    453  1.21      ad 		cpu_get_tsc_freq(ci);
    454  1.21      ad 		cpu_identify(ci);
    455   1.2  bouyer 		cpu_init(ci);
    456   1.2  bouyer 		cpu_set_tss_gates(ci);
    457  1.12  cegger 		pmap_cpu_init_late(ci);
    458  1.26  bouyer 		x86_cpu_idle_init();
    459  1.12  cegger #if NLAPIC > 0
    460  1.12  cegger 		/*
    461  1.12  cegger 		 * Enable local apic
    462  1.12  cegger 		 */
    463  1.12  cegger 		lapic_enable();
    464  1.12  cegger 		lapic_set_lvt();
    465  1.12  cegger 		lapic_calibrate_timer(ci);
    466  1.12  cegger #endif
    467  1.14  bouyer #if 0
    468  1.12  cegger 		x86_errata();
    469  1.12  cegger #endif
    470   1.2  bouyer 		break;
    471   1.2  bouyer 
    472   1.2  bouyer 	case CPU_ROLE_AP:
    473   1.2  bouyer 		/*
    474   1.2  bouyer 		 * report on an AP
    475   1.2  bouyer 		 */
    476   1.2  bouyer 
    477   1.2  bouyer #if defined(MULTIPROCESSOR)
    478   1.2  bouyer 		cpu_intr_init(ci);
    479   1.2  bouyer 		gdt_alloc_cpu(ci);
    480   1.2  bouyer 		cpu_set_tss_gates(ci);
    481  1.12  cegger 		pmap_cpu_init_early(ci);
    482  1.12  cegger 		pmap_cpu_init_late(ci);
    483   1.2  bouyer 		cpu_start_secondary(ci);
    484   1.2  bouyer 		if (ci->ci_flags & CPUF_PRESENT) {
    485  1.30  cegger 			struct cpu_info *tmp;
    486  1.30  cegger 
    487   1.2  bouyer 			identifycpu(ci);
    488  1.30  cegger 			tmp = cpu_info_list;
    489  1.30  cegger 			while (tmp->ci_next)
    490  1.30  cegger 				tmp = tmp->ci_next;
    491  1.30  cegger 
    492  1.30  cegger 			tmp->ci_next = ci;
    493   1.2  bouyer 		}
    494   1.2  bouyer #else
    495  1.12  cegger 		aprint_normal_dev(sc->sc_dev, "not started\n");
    496   1.2  bouyer #endif
    497   1.2  bouyer 		break;
    498   1.2  bouyer 
    499   1.2  bouyer 	default:
    500  1.12  cegger 		aprint_normal("\n");
    501   1.2  bouyer 		panic("unknown processor type??\n");
    502   1.2  bouyer 	}
    503   1.2  bouyer 	cpu_vm_init(ci);
    504   1.2  bouyer 
    505  1.34  cegger 	atomic_or_32(&cpus_attached, ci->ci_cpumask);
    506   1.2  bouyer 
    507  1.12  cegger #if 0
    508  1.12  cegger 	if (!pmf_device_register(self, cpu_suspend, cpu_resume))
    509  1.12  cegger 		aprint_error_dev(self, "couldn't establish power handler\n");
    510  1.12  cegger #endif
    511  1.12  cegger 
    512   1.2  bouyer #if defined(MULTIPROCESSOR)
    513   1.2  bouyer 	if (mp_verbose) {
    514   1.2  bouyer 		struct lwp *l = ci->ci_data.cpu_idlelwp;
    515  1.37   rmind 		struct pcb *pcb = lwp_getpcb(l);
    516   1.2  bouyer 
    517  1.12  cegger 		aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n",
    518  1.12  cegger 		    l,
    519  1.12  cegger #ifdef i386
    520  1.37   rmind 		    (void *)pcb->pcb_esp
    521  1.12  cegger #else
    522  1.37   rmind 		    (void *)pcb->pcb_rsp
    523  1.12  cegger #endif
    524  1.12  cegger 		);
    525  1.12  cegger 
    526   1.2  bouyer 	}
    527   1.2  bouyer #endif
    528   1.2  bouyer }
    529   1.2  bouyer 
    530   1.2  bouyer /*
    531   1.2  bouyer  * Initialize the processor appropriately.
    532   1.2  bouyer  */
    533   1.2  bouyer 
    534   1.2  bouyer void
    535  1.10  cegger cpu_init(struct cpu_info *ci)
    536   1.2  bouyer {
    537   1.2  bouyer 
    538   1.2  bouyer 	/*
    539   1.2  bouyer 	 * On a P6 or above, enable global TLB caching if the
    540   1.2  bouyer 	 * hardware supports it.
    541   1.2  bouyer 	 */
    542   1.2  bouyer 	if (cpu_feature & CPUID_PGE)
    543   1.2  bouyer 		lcr4(rcr4() | CR4_PGE);	/* enable global TLB caching */
    544   1.2  bouyer 
    545   1.2  bouyer #ifdef XXXMTRR
    546   1.2  bouyer 	/*
    547   1.2  bouyer 	 * On a P6 or above, initialize MTRR's if the hardware supports them.
    548   1.2  bouyer 	 */
    549   1.2  bouyer 	if (cpu_feature & CPUID_MTRR) {
    550   1.2  bouyer 		if ((ci->ci_flags & CPUF_AP) == 0)
    551   1.2  bouyer 			i686_mtrr_init_first();
    552   1.2  bouyer 		mtrr_init_cpu(ci);
    553   1.2  bouyer 	}
    554   1.2  bouyer #endif
    555   1.2  bouyer 	/*
    556   1.2  bouyer 	 * If we have FXSAVE/FXRESTOR, use them.
    557   1.2  bouyer 	 */
    558   1.2  bouyer 	if (cpu_feature & CPUID_FXSR) {
    559   1.2  bouyer 		lcr4(rcr4() | CR4_OSFXSR);
    560   1.2  bouyer 
    561   1.2  bouyer 		/*
    562   1.2  bouyer 		 * If we have SSE/SSE2, enable XMM exceptions.
    563   1.2  bouyer 		 */
    564   1.2  bouyer 		if (cpu_feature & (CPUID_SSE|CPUID_SSE2))
    565   1.2  bouyer 			lcr4(rcr4() | CR4_OSXMMEXCPT);
    566   1.2  bouyer 	}
    567   1.2  bouyer 
    568  1.34  cegger 	atomic_or_32(&cpus_running, ci->ci_cpumask);
    569  1.11  cegger 	atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
    570   1.2  bouyer }
    571   1.2  bouyer 
    572   1.2  bouyer 
    573   1.2  bouyer #ifdef MULTIPROCESSOR
    574   1.2  bouyer void
    575  1.10  cegger cpu_boot_secondary_processors(void)
    576   1.2  bouyer {
    577   1.2  bouyer 	struct cpu_info *ci;
    578   1.2  bouyer 	u_long i;
    579   1.2  bouyer 
    580  1.11  cegger 	for (i = 0; i < X86_MAXPROCS; i++) {
    581   1.2  bouyer 		ci = cpu_info[i];
    582   1.2  bouyer 		if (ci == NULL)
    583   1.2  bouyer 			continue;
    584   1.2  bouyer 		if (ci->ci_data.cpu_idlelwp == NULL)
    585   1.2  bouyer 			continue;
    586   1.2  bouyer 		if ((ci->ci_flags & CPUF_PRESENT) == 0)
    587   1.2  bouyer 			continue;
    588   1.2  bouyer 		if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY))
    589   1.2  bouyer 			continue;
    590   1.2  bouyer 		cpu_boot_secondary(ci);
    591   1.2  bouyer 	}
    592  1.11  cegger 
    593  1.11  cegger 	x86_mp_online = true;
    594   1.2  bouyer }
    595   1.2  bouyer 
    596   1.2  bouyer static void
    597   1.2  bouyer cpu_init_idle_lwp(struct cpu_info *ci)
    598   1.2  bouyer {
    599   1.2  bouyer 	struct lwp *l = ci->ci_data.cpu_idlelwp;
    600  1.37   rmind 	struct pcb *pcb = lwp_getpcb(l);
    601   1.2  bouyer 
    602   1.2  bouyer 	pcb->pcb_cr0 = rcr0();
    603   1.2  bouyer }
    604   1.2  bouyer 
    605   1.2  bouyer void
    606  1.10  cegger cpu_init_idle_lwps(void)
    607   1.2  bouyer {
    608   1.2  bouyer 	struct cpu_info *ci;
    609   1.2  bouyer 	u_long i;
    610   1.2  bouyer 
    611   1.2  bouyer 	for (i = 0; i < X86_MAXPROCS; i++) {
    612   1.2  bouyer 		ci = cpu_info[i];
    613   1.2  bouyer 		if (ci == NULL)
    614   1.2  bouyer 			continue;
    615   1.2  bouyer 		if (ci->ci_data.cpu_idlelwp == NULL)
    616   1.2  bouyer 			continue;
    617   1.2  bouyer 		if ((ci->ci_flags & CPUF_PRESENT) == 0)
    618   1.2  bouyer 			continue;
    619   1.2  bouyer 		cpu_init_idle_lwp(ci);
    620   1.2  bouyer 	}
    621   1.2  bouyer }
    622   1.2  bouyer 
    623   1.2  bouyer void
    624  1.10  cegger cpu_start_secondary(struct cpu_info *ci)
    625   1.2  bouyer {
    626   1.2  bouyer 	int i;
    627   1.2  bouyer 	struct pmap *kpm = pmap_kernel();
    628  1.11  cegger 	extern uint32_t mp_pdirpa;
    629   1.2  bouyer 
    630   1.2  bouyer 	mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */
    631   1.2  bouyer 
    632  1.11  cegger 	atomic_or_32(&ci->ci_flags, CPUF_AP);
    633   1.2  bouyer 
    634  1.11  cegger 	aprint_debug_dev(ci->ci_dev, "starting\n");
    635   1.2  bouyer 
    636   1.2  bouyer 	ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
    637  1.11  cegger 	if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0)
    638  1.11  cegger 		return;
    639   1.2  bouyer 
    640   1.2  bouyer 	/*
    641   1.2  bouyer 	 * wait for it to become ready
    642   1.2  bouyer 	 */
    643  1.11  cegger 	for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) {
    644  1.11  cegger #ifdef MPDEBUG
    645  1.11  cegger 		extern int cpu_trace[3];
    646  1.11  cegger 		static int otrace[3];
    647  1.11  cegger 		if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) {
    648  1.11  cegger 			aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n",
    649  1.11  cegger 				cpu_trace[0], cpu_trace[1], cpu_trace[2]);
    650  1.11  cegger 			memcpy(otrace, cpu_trace, sizeof(otrace));
    651  1.11  cegger 		}
    652  1.11  cegger #endif
    653   1.2  bouyer 		delay(10);
    654   1.2  bouyer 	}
    655  1.11  cegger 	if ((ci->ci_flags & CPUF_PRESENT) == 0) {
    656   1.9  cegger 		aprint_error_dev(ci->ci_dev, "failed to become ready\n");
    657   1.2  bouyer #if defined(MPDEBUG) && defined(DDB)
    658   1.2  bouyer 		printf("dropping into debugger; continue from here to resume boot\n");
    659   1.2  bouyer 		Debugger();
    660   1.2  bouyer #endif
    661   1.2  bouyer 	}
    662   1.2  bouyer 
    663   1.2  bouyer 	CPU_START_CLEANUP(ci);
    664   1.2  bouyer }
    665   1.2  bouyer 
    666   1.2  bouyer void
    667  1.10  cegger cpu_boot_secondary(struct cpu_info *ci)
    668   1.2  bouyer {
    669   1.2  bouyer 	int i;
    670   1.2  bouyer 
    671  1.11  cegger 	atomic_or_32(&ci->ci_flags, CPUF_GO);
    672  1.11  cegger 	for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) {
    673   1.2  bouyer 		delay(10);
    674   1.2  bouyer 	}
    675  1.11  cegger 	if ((ci->ci_flags & CPUF_RUNNING) == 0) {
    676  1.11  cegger 		aprint_error_dev(ci->ci_dev, "CPU failed to start\n");
    677   1.2  bouyer #if defined(MPDEBUG) && defined(DDB)
    678   1.2  bouyer 		printf("dropping into debugger; continue from here to resume boot\n");
    679   1.2  bouyer 		Debugger();
    680   1.2  bouyer #endif
    681   1.2  bouyer 	}
    682   1.2  bouyer }
    683   1.2  bouyer 
    684   1.2  bouyer /*
    685   1.2  bouyer  * The CPU ends up here when its ready to run
    686   1.2  bouyer  * This is called from code in mptramp.s; at this point, we are running
    687   1.2  bouyer  * in the idle pcb/idle stack of the new CPU.  When this function returns,
    688   1.2  bouyer  * this processor will enter the idle loop and start looking for work.
    689   1.2  bouyer  *
    690   1.2  bouyer  * XXX should share some of this with init386 in machdep.c
    691   1.2  bouyer  */
    692   1.2  bouyer void
    693   1.2  bouyer cpu_hatch(void *v)
    694   1.2  bouyer {
    695   1.2  bouyer 	struct cpu_info *ci = (struct cpu_info *)v;
    696  1.37   rmind 	struct pcb *pcb;
    697  1.37   rmind 	uint32_t blacklist_features;
    698  1.11  cegger 	int s, i;
    699  1.11  cegger 
    700   1.2  bouyer #ifdef __x86_64__
    701  1.11  cegger         cpu_init_msrs(ci, true);
    702   1.2  bouyer #endif
    703   1.2  bouyer 
    704  1.21      ad 	cpu_probe(ci);
    705  1.11  cegger 
    706   1.2  bouyer 	/* not on Xen... */
    707  1.11  cegger 	blacklist_features = ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); /* XXX add CPUID_SVM */
    708   1.2  bouyer 
    709  1.11  cegger 	cpu_feature &= blacklist_features;
    710   1.2  bouyer 
    711  1.11  cegger 	KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
    712  1.11  cegger 	atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
    713  1.11  cegger 	while ((ci->ci_flags & CPUF_GO) == 0) {
    714  1.11  cegger 		/* Don't use delay, boot CPU may be patching the text. */
    715  1.11  cegger 		for (i = 10000; i != 0; i--)
    716  1.11  cegger 			x86_pause();
    717  1.11  cegger 	}
    718   1.2  bouyer 
    719  1.11  cegger 	/* Because the text may have been patched in x86_patch(). */
    720  1.11  cegger 	wbinvd();
    721  1.11  cegger 	x86_flush();
    722   1.2  bouyer 
    723  1.11  cegger 	KASSERT((ci->ci_flags & CPUF_RUNNING) == 0);
    724   1.2  bouyer 
    725  1.37   rmind 	pcb = lwp_getpcb(curlwp);
    726  1.12  cegger 	lcr3(pmap_kernel()->pm_pdirpa);
    727  1.37   rmind 	pcb->pcb_cr3 = pmap_kernel()->pm_pdirpa;
    728  1.37   rmind 	pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp);
    729  1.37   rmind 	lcr0(pcb->pcb_cr0);
    730  1.37   rmind 
    731   1.2  bouyer 	cpu_init_idt();
    732  1.11  cegger 	gdt_init_cpu(ci);
    733  1.11  cegger 	lapic_enable();
    734   1.2  bouyer 	lapic_set_lvt();
    735  1.11  cegger 	lapic_initclocks();
    736  1.11  cegger 
    737  1.12  cegger #ifdef i386
    738   1.2  bouyer 	npxinit(ci);
    739  1.12  cegger #else
    740  1.12  cegger 	fpuinit(ci);
    741  1.12  cegger #endif
    742   1.2  bouyer 
    743   1.2  bouyer 	lldt(GSEL(GLDT_SEL, SEL_KPL));
    744  1.12  cegger 	ltr(ci->ci_tss_sel);
    745   1.2  bouyer 
    746   1.2  bouyer 	cpu_init(ci);
    747  1.11  cegger 	cpu_get_tsc_freq(ci);
    748   1.2  bouyer 
    749   1.2  bouyer 	s = splhigh();
    750  1.11  cegger #ifdef i386
    751   1.2  bouyer 	lapic_tpr = 0;
    752  1.11  cegger #else
    753  1.11  cegger 	lcr8(0);
    754  1.11  cegger #endif
    755  1.11  cegger 	x86_enable_intr();
    756  1.11  cegger 	splx(s);
    757  1.12  cegger #if 0
    758  1.11  cegger 	x86_errata();
    759  1.11  cegger #endif
    760   1.2  bouyer 
    761  1.11  cegger 	aprint_debug_dev(ci->ci_dev, "CPU %ld running\n",
    762  1.11  cegger 		(long)ci->ci_cpuid);
    763   1.2  bouyer }
    764   1.2  bouyer 
    765   1.2  bouyer #if defined(DDB)
    766   1.2  bouyer 
    767   1.2  bouyer #include <ddb/db_output.h>
    768   1.2  bouyer #include <machine/db_machdep.h>
    769   1.2  bouyer 
    770   1.2  bouyer /*
    771   1.2  bouyer  * Dump CPU information from ddb.
    772   1.2  bouyer  */
    773   1.2  bouyer void
    774   1.2  bouyer cpu_debug_dump(void)
    775   1.2  bouyer {
    776   1.2  bouyer 	struct cpu_info *ci;
    777   1.2  bouyer 	CPU_INFO_ITERATOR cii;
    778   1.2  bouyer 
    779  1.13    yamt 	db_printf("addr		dev	id	flags	ipis	curlwp 		fpcurlwp\n");
    780   1.2  bouyer 	for (CPU_INFO_FOREACH(cii, ci)) {
    781   1.2  bouyer 		db_printf("%p	%s	%ld	%x	%x	%10p	%10p\n",
    782   1.2  bouyer 		    ci,
    783   1.9  cegger 		    ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev),
    784  1.12  cegger 		    (long)ci->ci_cpuid,
    785   1.2  bouyer 		    ci->ci_flags, ci->ci_ipis,
    786   1.2  bouyer 		    ci->ci_curlwp,
    787   1.2  bouyer 		    ci->ci_fpcurlwp);
    788   1.2  bouyer 	}
    789   1.2  bouyer }
    790   1.2  bouyer #endif
    791   1.2  bouyer 
    792   1.2  bouyer static void
    793  1.10  cegger cpu_copy_trampoline(void)
    794   1.2  bouyer {
    795   1.2  bouyer 	/*
    796   1.2  bouyer 	 * Copy boot code.
    797   1.2  bouyer 	 */
    798   1.2  bouyer 	extern u_char cpu_spinup_trampoline[];
    799   1.2  bouyer 	extern u_char cpu_spinup_trampoline_end[];
    800  1.11  cegger 
    801  1.11  cegger 	vaddr_t mp_trampoline_vaddr;
    802  1.11  cegger 
    803  1.11  cegger 	mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
    804  1.11  cegger 		UVM_KMF_VAONLY);
    805  1.11  cegger 
    806  1.11  cegger 	pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr,
    807  1.36  cegger 		VM_PROT_READ | VM_PROT_WRITE, 0);
    808  1.11  cegger 	pmap_update(pmap_kernel());
    809  1.11  cegger 	memcpy((void *)mp_trampoline_vaddr,
    810  1.11  cegger 		cpu_spinup_trampoline,
    811  1.11  cegger 		cpu_spinup_trampoline_end - cpu_spinup_trampoline);
    812  1.11  cegger 
    813  1.11  cegger 	pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE);
    814  1.11  cegger 	pmap_update(pmap_kernel());
    815  1.11  cegger 	uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
    816   1.2  bouyer }
    817   1.2  bouyer 
    818   1.2  bouyer #endif
    819   1.2  bouyer 
    820  1.11  cegger #ifdef i386
    821  1.11  cegger #if 0
    822  1.11  cegger static void
    823  1.11  cegger tss_init(struct i386tss *tss, void *stack, void *func)
    824  1.11  cegger {
    825  1.11  cegger 	memset(tss, 0, sizeof *tss);
    826  1.11  cegger 	tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
    827  1.11  cegger 	tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
    828  1.11  cegger 	tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
    829  1.11  cegger 	tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
    830  1.11  cegger 	tss->tss_gs = tss->__tss_es = tss->__tss_ds =
    831  1.11  cegger 	    tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
    832  1.11  cegger 	tss->tss_cr3 = pmap_kernel()->pm_pdirpa;
    833  1.11  cegger 	tss->tss_esp = (int)((char *)stack + USPACE - 16);
    834  1.11  cegger 	tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
    835  1.11  cegger 	tss->__tss_eflags = PSL_MBO | PSL_NT;   /* XXX not needed? */
    836  1.11  cegger 	tss->__tss_eip = (int)func;
    837  1.11  cegger }
    838  1.11  cegger #endif
    839   1.2  bouyer 
    840   1.2  bouyer /* XXX */
    841   1.2  bouyer #define IDTVEC(name)	__CONCAT(X, name)
    842   1.2  bouyer typedef void (vector)(void);
    843   1.2  bouyer extern vector IDTVEC(tss_trap08);
    844   1.2  bouyer #ifdef DDB
    845   1.2  bouyer extern vector Xintrddbipi;
    846   1.2  bouyer extern int ddb_vec;
    847   1.2  bouyer #endif
    848   1.2  bouyer 
    849   1.2  bouyer static void
    850   1.2  bouyer cpu_set_tss_gates(struct cpu_info *ci)
    851   1.2  bouyer {
    852  1.11  cegger #if 0
    853  1.11  cegger 	struct segment_descriptor sd;
    854  1.11  cegger 
    855  1.11  cegger 	ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
    856  1.11  cegger 	    UVM_KMF_WIRED);
    857  1.11  cegger 	tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
    858  1.11  cegger 	    IDTVEC(tss_trap08));
    859  1.11  cegger 	setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
    860  1.11  cegger 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
    861  1.11  cegger 	ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
    862  1.11  cegger 	setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
    863  1.11  cegger 	    GSEL(GTRAPTSS_SEL, SEL_KPL));
    864  1.11  cegger #endif
    865  1.11  cegger 
    866   1.2  bouyer #if defined(DDB) && defined(MULTIPROCESSOR)
    867   1.2  bouyer 	/*
    868   1.2  bouyer 	 * Set up separate handler for the DDB IPI, so that it doesn't
    869   1.2  bouyer 	 * stomp on a possibly corrupted stack.
    870   1.2  bouyer 	 *
    871   1.2  bouyer 	 * XXX overwriting the gate set in db_machine_init.
    872   1.2  bouyer 	 * Should rearrange the code so that it's set only once.
    873   1.2  bouyer 	 */
    874   1.2  bouyer 	ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
    875   1.2  bouyer 	    UVM_KMF_WIRED);
    876   1.6    yamt 	tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack,
    877   1.2  bouyer 	    Xintrddbipi);
    878   1.2  bouyer 
    879   1.2  bouyer 	setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
    880   1.2  bouyer 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
    881   1.2  bouyer 	ci->ci_gdt[GIPITSS_SEL].sd = sd;
    882   1.2  bouyer 
    883   1.2  bouyer 	setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
    884   1.2  bouyer 	    GSEL(GIPITSS_SEL, SEL_KPL));
    885   1.2  bouyer #endif
    886   1.2  bouyer }
    887  1.11  cegger #else
    888  1.11  cegger static void
    889  1.11  cegger cpu_set_tss_gates(struct cpu_info *ci)
    890  1.11  cegger {
    891  1.11  cegger 
    892  1.11  cegger }
    893  1.11  cegger #endif	/* i386 */
    894   1.2  bouyer 
    895   1.2  bouyer int
    896   1.5   joerg mp_cpu_start(struct cpu_info *ci, paddr_t target)
    897   1.2  bouyer {
    898   1.2  bouyer #if 0
    899   1.2  bouyer #if NLAPIC > 0
    900   1.2  bouyer 	int error;
    901   1.2  bouyer #endif
    902   1.2  bouyer 	unsigned short dwordptr[2];
    903   1.2  bouyer 
    904   1.2  bouyer 	/*
    905  1.11  cegger 	 * Bootstrap code must be addressable in real mode
    906  1.11  cegger 	 * and it must be page aligned.
    907  1.11  cegger 	 */
    908  1.11  cegger 	KASSERT(target < 0x10000 && target % PAGE_SIZE == 0);
    909  1.11  cegger 
    910  1.11  cegger 	/*
    911   1.2  bouyer 	 * "The BSP must initialize CMOS shutdown code to 0Ah ..."
    912   1.2  bouyer 	 */
    913   1.2  bouyer 
    914   1.2  bouyer 	outb(IO_RTC, NVRAM_RESET);
    915   1.2  bouyer 	outb(IO_RTC+1, NVRAM_RESET_JUMP);
    916   1.2  bouyer 
    917   1.2  bouyer 	/*
    918   1.2  bouyer 	 * "and the warm reset vector (DWORD based at 40:67) to point
    919   1.2  bouyer 	 * to the AP startup code ..."
    920   1.2  bouyer 	 */
    921   1.2  bouyer 
    922   1.2  bouyer 	dwordptr[0] = 0;
    923   1.5   joerg 	dwordptr[1] = target >> 4;
    924   1.2  bouyer 
    925  1.36  cegger 	pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE, 0);
    926  1.11  cegger 	memcpy ((uint8_t *) 0x467, dwordptr, 4);
    927   1.2  bouyer 	pmap_kremove (0, PAGE_SIZE);
    928   1.2  bouyer 
    929   1.2  bouyer #if NLAPIC > 0
    930   1.2  bouyer 	/*
    931   1.2  bouyer 	 * ... prior to executing the following sequence:"
    932   1.2  bouyer 	 */
    933   1.2  bouyer 
    934   1.2  bouyer 	if (ci->ci_flags & CPUF_AP) {
    935  1.23      ad 		if ((error = x86_ipi_init(ci->ci_cpuid)) != 0)
    936   1.2  bouyer 			return error;
    937   1.2  bouyer 
    938   1.2  bouyer 		delay(10000);
    939   1.2  bouyer 
    940   1.2  bouyer 		if (cpu_feature & CPUID_APIC) {
    941  1.23      ad 			error = x86_ipi_init(ci->ci_cpuid);
    942  1.11  cegger 			if (error != 0) {
    943  1.11  cegger 				aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n",
    944  1.11  cegger 						__func__);
    945  1.11  cegger 				return error;
    946  1.11  cegger 			}
    947  1.11  cegger 
    948  1.11  cegger 			delay(10000);
    949   1.2  bouyer 
    950  1.23      ad 			error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
    951  1.11  cegger 					LAPIC_DLMODE_STARTUP);
    952  1.11  cegger 			if (error != 0) {
    953  1.11  cegger 				aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n",
    954  1.11  cegger 						__func__);
    955   1.2  bouyer 				return error;
    956  1.11  cegger 			}
    957   1.2  bouyer 			delay(200);
    958   1.2  bouyer 
    959  1.23      ad 			error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
    960  1.11  cegger 					LAPIC_DLMODE_STARTUP);
    961  1.11  cegger 			if (error != 0) {
    962  1.11  cegger 				aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n",
    963  1.11  cegger 						__func__);
    964   1.2  bouyer 				return error;
    965  1.11  cegger 			}
    966   1.2  bouyer 			delay(200);
    967   1.2  bouyer 		}
    968   1.2  bouyer 	}
    969   1.2  bouyer #endif
    970   1.2  bouyer #endif /* 0 */
    971   1.2  bouyer 	return 0;
    972   1.2  bouyer }
    973   1.2  bouyer 
    974   1.2  bouyer void
    975   1.2  bouyer mp_cpu_start_cleanup(struct cpu_info *ci)
    976   1.2  bouyer {
    977   1.2  bouyer #if 0
    978   1.2  bouyer 	/*
    979   1.2  bouyer 	 * Ensure the NVRAM reset byte contains something vaguely sane.
    980   1.2  bouyer 	 */
    981   1.2  bouyer 
    982   1.2  bouyer 	outb(IO_RTC, NVRAM_RESET);
    983   1.2  bouyer 	outb(IO_RTC+1, NVRAM_RESET_RST);
    984   1.2  bouyer #endif
    985   1.2  bouyer }
    986   1.2  bouyer 
    987   1.2  bouyer #ifdef __x86_64__
    988   1.2  bouyer 
    989   1.2  bouyer void
    990   1.3  bouyer cpu_init_msrs(struct cpu_info *ci, bool full)
    991   1.2  bouyer {
    992   1.3  bouyer 	if (full) {
    993   1.3  bouyer 		HYPERVISOR_set_segment_base (SEGBASE_FS, 0);
    994  1.11  cegger 		HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci);
    995   1.3  bouyer 		HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0);
    996   1.3  bouyer 	}
    997   1.2  bouyer }
    998   1.2  bouyer #endif	/* __x86_64__ */
    999   1.2  bouyer 
   1000  1.11  cegger void
   1001  1.11  cegger cpu_offline_md(void)
   1002  1.11  cegger {
   1003  1.11  cegger         int s;
   1004  1.11  cegger 
   1005  1.11  cegger         s = splhigh();
   1006  1.11  cegger #ifdef __i386__
   1007  1.11  cegger         npxsave_cpu(true);
   1008  1.11  cegger #else
   1009  1.11  cegger         fpusave_cpu(true);
   1010  1.11  cegger #endif
   1011  1.11  cegger         splx(s);
   1012  1.11  cegger }
   1013  1.11  cegger 
   1014  1.11  cegger #if 0
   1015  1.11  cegger /* XXX joerg restructure and restart CPUs individually */
   1016  1.11  cegger static bool
   1017  1.11  cegger cpu_suspend(device_t dv PMF_FN_ARGS)
   1018  1.11  cegger {
   1019  1.11  cegger 	struct cpu_softc *sc = device_private(dv);
   1020  1.11  cegger 	struct cpu_info *ci = sc->sc_info;
   1021  1.11  cegger 	int err;
   1022  1.11  cegger 
   1023  1.11  cegger 	if (ci->ci_flags & CPUF_PRIMARY)
   1024  1.11  cegger 		return true;
   1025  1.11  cegger 	if (ci->ci_data.cpu_idlelwp == NULL)
   1026  1.11  cegger 		return true;
   1027  1.11  cegger 	if ((ci->ci_flags & CPUF_PRESENT) == 0)
   1028  1.11  cegger 		return true;
   1029  1.11  cegger 
   1030  1.11  cegger 	sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE);
   1031  1.11  cegger 
   1032  1.11  cegger 	if (sc->sc_wasonline) {
   1033  1.11  cegger 		mutex_enter(&cpu_lock);
   1034  1.29   rmind 		err = cpu_setstate(ci, false);
   1035  1.11  cegger 		mutex_exit(&cpu_lock);
   1036  1.11  cegger 
   1037  1.11  cegger 		if (err)
   1038  1.11  cegger 			return false;
   1039  1.11  cegger 	}
   1040  1.11  cegger 
   1041  1.11  cegger 	return true;
   1042  1.11  cegger }
   1043  1.11  cegger 
   1044  1.11  cegger static bool
   1045  1.11  cegger cpu_resume(device_t dv PMF_FN_ARGS)
   1046  1.11  cegger {
   1047  1.11  cegger 	struct cpu_softc *sc = device_private(dv);
   1048  1.11  cegger 	struct cpu_info *ci = sc->sc_info;
   1049  1.11  cegger 	int err = 0;
   1050  1.11  cegger 
   1051  1.11  cegger 	if (ci->ci_flags & CPUF_PRIMARY)
   1052  1.11  cegger 		return true;
   1053  1.11  cegger 	if (ci->ci_data.cpu_idlelwp == NULL)
   1054  1.11  cegger 		return true;
   1055  1.11  cegger 	if ((ci->ci_flags & CPUF_PRESENT) == 0)
   1056  1.11  cegger 		return true;
   1057  1.11  cegger 
   1058  1.11  cegger 	if (sc->sc_wasonline) {
   1059  1.11  cegger 		mutex_enter(&cpu_lock);
   1060  1.29   rmind 		err = cpu_setstate(ci, true);
   1061  1.11  cegger 		mutex_exit(&cpu_lock);
   1062  1.11  cegger 	}
   1063  1.11  cegger 
   1064  1.11  cegger 	return err == 0;
   1065  1.11  cegger }
   1066  1.11  cegger #endif
   1067  1.11  cegger 
   1068   1.2  bouyer void
   1069   1.2  bouyer cpu_get_tsc_freq(struct cpu_info *ci)
   1070   1.2  bouyer {
   1071  1.16  cegger 	const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time;
   1072   1.2  bouyer 	delay(1000000);
   1073   1.2  bouyer 	uint64_t freq = 1000000000ULL << 32;
   1074   1.2  bouyer 	freq = freq / (uint64_t)tinfo->tsc_to_system_mul;
   1075   1.2  bouyer 	if ( tinfo->tsc_shift < 0 )
   1076   1.2  bouyer 		freq = freq << -tinfo->tsc_shift;
   1077   1.2  bouyer 	else
   1078   1.2  bouyer 		freq = freq >> tinfo->tsc_shift;
   1079  1.20      ad 	ci->ci_data.cpu_cc_freq = freq;
   1080   1.2  bouyer }
   1081  1.19   joerg 
   1082  1.19   joerg void
   1083  1.19   joerg x86_cpu_idle_xen(void)
   1084  1.19   joerg {
   1085  1.19   joerg 	struct cpu_info *ci = curcpu();
   1086  1.19   joerg 
   1087  1.19   joerg 	KASSERT(ci->ci_ilevel == IPL_NONE);
   1088  1.19   joerg 
   1089  1.19   joerg 	x86_disable_intr();
   1090  1.19   joerg 	if (!__predict_false(ci->ci_want_resched)) {
   1091  1.19   joerg 		idle_block();
   1092  1.19   joerg 	} else {
   1093  1.19   joerg 		x86_enable_intr();
   1094  1.19   joerg 	}
   1095  1.19   joerg }
   1096