cpu.c revision 1.52 1 1.52 bouyer /* $NetBSD: cpu.c,v 1.52 2010/11/14 13:43:04 bouyer Exp $ */
2 1.2 bouyer /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */
3 1.2 bouyer
4 1.2 bouyer /*-
5 1.2 bouyer * Copyright (c) 2000 The NetBSD Foundation, Inc.
6 1.19 joerg * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
7 1.2 bouyer * All rights reserved.
8 1.2 bouyer *
9 1.2 bouyer * This code is derived from software contributed to The NetBSD Foundation
10 1.2 bouyer * by RedBack Networks Inc.
11 1.2 bouyer *
12 1.2 bouyer * Author: Bill Sommerfeld
13 1.2 bouyer *
14 1.2 bouyer * Redistribution and use in source and binary forms, with or without
15 1.2 bouyer * modification, are permitted provided that the following conditions
16 1.2 bouyer * are met:
17 1.2 bouyer * 1. Redistributions of source code must retain the above copyright
18 1.2 bouyer * notice, this list of conditions and the following disclaimer.
19 1.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright
20 1.2 bouyer * notice, this list of conditions and the following disclaimer in the
21 1.2 bouyer * documentation and/or other materials provided with the distribution.
22 1.2 bouyer *
23 1.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.2 bouyer * POSSIBILITY OF SUCH DAMAGE.
34 1.2 bouyer */
35 1.2 bouyer
36 1.2 bouyer /*
37 1.2 bouyer * Copyright (c) 1999 Stefan Grefen
38 1.2 bouyer *
39 1.2 bouyer * Redistribution and use in source and binary forms, with or without
40 1.2 bouyer * modification, are permitted provided that the following conditions
41 1.2 bouyer * are met:
42 1.2 bouyer * 1. Redistributions of source code must retain the above copyright
43 1.2 bouyer * notice, this list of conditions and the following disclaimer.
44 1.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright
45 1.2 bouyer * notice, this list of conditions and the following disclaimer in the
46 1.2 bouyer * documentation and/or other materials provided with the distribution.
47 1.2 bouyer * 3. All advertising materials mentioning features or use of this software
48 1.2 bouyer * must display the following acknowledgement:
49 1.2 bouyer * This product includes software developed by the NetBSD
50 1.2 bouyer * Foundation, Inc. and its contributors.
51 1.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its
52 1.2 bouyer * contributors may be used to endorse or promote products derived
53 1.2 bouyer * from this software without specific prior written permission.
54 1.2 bouyer *
55 1.2 bouyer * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
56 1.2 bouyer * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 1.2 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
58 1.2 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
59 1.2 bouyer * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 1.2 bouyer * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
61 1.2 bouyer * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 1.2 bouyer * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
63 1.2 bouyer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
64 1.2 bouyer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 1.2 bouyer * SUCH DAMAGE.
66 1.2 bouyer */
67 1.2 bouyer
68 1.2 bouyer #include <sys/cdefs.h>
69 1.52 bouyer __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.52 2010/11/14 13:43:04 bouyer Exp $");
70 1.2 bouyer
71 1.2 bouyer #include "opt_ddb.h"
72 1.2 bouyer #include "opt_multiprocessor.h"
73 1.2 bouyer #include "opt_mpbios.h" /* for MPDEBUG */
74 1.2 bouyer #include "opt_mtrr.h"
75 1.2 bouyer #include "opt_xen.h"
76 1.2 bouyer
77 1.2 bouyer #include "lapic.h"
78 1.2 bouyer #include "ioapic.h"
79 1.2 bouyer
80 1.2 bouyer #include <sys/param.h>
81 1.2 bouyer #include <sys/proc.h>
82 1.2 bouyer #include <sys/systm.h>
83 1.2 bouyer #include <sys/device.h>
84 1.31 cegger #include <sys/kmem.h>
85 1.11 cegger #include <sys/cpu.h>
86 1.11 cegger #include <sys/atomic.h>
87 1.32 cegger #include <sys/reboot.h>
88 1.2 bouyer
89 1.51 uebayasi #include <uvm/uvm.h>
90 1.2 bouyer
91 1.2 bouyer #include <machine/cpufunc.h>
92 1.2 bouyer #include <machine/cpuvar.h>
93 1.2 bouyer #include <machine/pmap.h>
94 1.2 bouyer #include <machine/vmparam.h>
95 1.2 bouyer #include <machine/mpbiosvar.h>
96 1.2 bouyer #include <machine/pcb.h>
97 1.2 bouyer #include <machine/specialreg.h>
98 1.2 bouyer #include <machine/segments.h>
99 1.2 bouyer #include <machine/gdt.h>
100 1.2 bouyer #include <machine/mtrr.h>
101 1.2 bouyer #include <machine/pio.h>
102 1.2 bouyer
103 1.2 bouyer #include <xen/vcpuvar.h>
104 1.2 bouyer
105 1.2 bouyer #if NLAPIC > 0
106 1.2 bouyer #include <machine/apicvar.h>
107 1.2 bouyer #include <machine/i82489reg.h>
108 1.2 bouyer #include <machine/i82489var.h>
109 1.2 bouyer #endif
110 1.2 bouyer
111 1.2 bouyer #include <dev/ic/mc146818reg.h>
112 1.2 bouyer #include <dev/isa/isareg.h>
113 1.2 bouyer
114 1.38 cegger #if MAXCPUS > 32
115 1.38 cegger #error cpu_info contains 32bit bitmasks
116 1.38 cegger #endif
117 1.27 ad
118 1.10 cegger int cpu_match(device_t, cfdata_t, void *);
119 1.10 cegger void cpu_attach(device_t, device_t, void *);
120 1.10 cegger int vcpu_match(device_t, cfdata_t, void *);
121 1.10 cegger void vcpu_attach(device_t, device_t, void *);
122 1.10 cegger void cpu_attach_common(device_t, device_t, void *);
123 1.8 dogcow void cpu_offline_md(void);
124 1.2 bouyer
125 1.2 bouyer struct cpu_softc {
126 1.10 cegger device_t sc_dev; /* device tree glue */
127 1.2 bouyer struct cpu_info *sc_info; /* pointer to CPU info */
128 1.32 cegger bool sc_wasonline;
129 1.2 bouyer };
130 1.2 bouyer
131 1.5 joerg int mp_cpu_start(struct cpu_info *, paddr_t);
132 1.2 bouyer void mp_cpu_start_cleanup(struct cpu_info *);
133 1.2 bouyer const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL,
134 1.2 bouyer mp_cpu_start_cleanup };
135 1.2 bouyer
136 1.10 cegger CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
137 1.2 bouyer cpu_match, cpu_attach, NULL, NULL);
138 1.10 cegger CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc),
139 1.2 bouyer vcpu_match, vcpu_attach, NULL, NULL);
140 1.2 bouyer
141 1.2 bouyer /*
142 1.2 bouyer * Statically-allocated CPU info for the primary CPU (or the only
143 1.2 bouyer * CPU, on uniprocessors). The CPU info list is initialized to
144 1.2 bouyer * point at it.
145 1.2 bouyer */
146 1.2 bouyer #ifdef TRAPLOG
147 1.2 bouyer #include <machine/tlog.h>
148 1.2 bouyer struct tlog tlog_primary;
149 1.2 bouyer #endif
150 1.38 cegger struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
151 1.7 bouyer .ci_dev = 0,
152 1.2 bouyer .ci_self = &cpu_info_primary,
153 1.4 bouyer .ci_idepth = -1,
154 1.2 bouyer .ci_curlwp = &lwp0,
155 1.25 ad .ci_curldt = -1,
156 1.2 bouyer #ifdef TRAPLOG
157 1.2 bouyer .ci_tlog = &tlog_primary,
158 1.2 bouyer #endif
159 1.2 bouyer
160 1.2 bouyer };
161 1.38 cegger struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = {
162 1.7 bouyer .ci_dev = 0,
163 1.2 bouyer .ci_self = &phycpu_info_primary,
164 1.2 bouyer };
165 1.2 bouyer
166 1.2 bouyer struct cpu_info *cpu_info_list = &cpu_info_primary;
167 1.38 cegger struct cpu_info *phycpu_info_list = &phycpu_info_primary;
168 1.2 bouyer
169 1.2 bouyer static void cpu_set_tss_gates(struct cpu_info *ci);
170 1.2 bouyer
171 1.11 cegger uint32_t cpus_attached = 0;
172 1.11 cegger uint32_t cpus_running = 0;
173 1.11 cegger
174 1.38 cegger uint32_t phycpus_attached = 0;
175 1.38 cegger uint32_t phycpus_running = 0;
176 1.38 cegger
177 1.43 jym uint32_t cpu_feature[5]; /* X86 CPUID feature bits
178 1.43 jym * [0] basic features %edx
179 1.43 jym * [1] basic features %ecx
180 1.43 jym * [2] extended features %edx
181 1.43 jym * [3] extended features %ecx
182 1.43 jym * [4] VIA padlock features
183 1.43 jym */
184 1.43 jym
185 1.11 cegger bool x86_mp_online;
186 1.11 cegger paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
187 1.2 bouyer
188 1.38 cegger #if defined(MULTIPROCESSOR)
189 1.2 bouyer void cpu_hatch(void *);
190 1.2 bouyer static void cpu_boot_secondary(struct cpu_info *ci);
191 1.2 bouyer static void cpu_start_secondary(struct cpu_info *ci);
192 1.2 bouyer static void cpu_copy_trampoline(void);
193 1.2 bouyer
194 1.2 bouyer /*
195 1.2 bouyer * Runs once per boot once multiprocessor goo has been detected and
196 1.2 bouyer * the local APIC on the boot processor has been mapped.
197 1.2 bouyer *
198 1.2 bouyer * Called from lapic_boot_init() (from mpbios_scan()).
199 1.2 bouyer */
200 1.2 bouyer void
201 1.10 cegger cpu_init_first(void)
202 1.2 bouyer {
203 1.2 bouyer
204 1.38 cegger cpu_info_primary.ci_cpuid = lapic_cpu_number();
205 1.2 bouyer cpu_copy_trampoline();
206 1.2 bouyer }
207 1.38 cegger #endif /* MULTIPROCESSOR */
208 1.2 bouyer
209 1.2 bouyer int
210 1.10 cegger cpu_match(device_t parent, cfdata_t match, void *aux)
211 1.2 bouyer {
212 1.2 bouyer
213 1.2 bouyer return 1;
214 1.2 bouyer }
215 1.2 bouyer
216 1.2 bouyer void
217 1.10 cegger cpu_attach(device_t parent, device_t self, void *aux)
218 1.2 bouyer {
219 1.10 cegger struct cpu_softc *sc = device_private(self);
220 1.2 bouyer struct cpu_attach_args *caa = aux;
221 1.2 bouyer struct cpu_info *ci;
222 1.34 cegger uintptr_t ptr;
223 1.52 bouyer static int nphycpu = 0;
224 1.2 bouyer
225 1.10 cegger sc->sc_dev = self;
226 1.10 cegger
227 1.38 cegger if (phycpus_attached == ~0) {
228 1.34 cegger aprint_error(": increase MAXCPUS\n");
229 1.34 cegger return;
230 1.34 cegger }
231 1.34 cegger
232 1.2 bouyer /*
233 1.2 bouyer * If we're an Application Processor, allocate a cpu_info
234 1.52 bouyer * If we're the first attached CPU use the primary cpu_info,
235 1.52 bouyer * otherwise allocate a new one
236 1.2 bouyer */
237 1.52 bouyer aprint_naive("\n");
238 1.52 bouyer aprint_normal("\n");
239 1.52 bouyer if (nphycpu > 0) {
240 1.52 bouyer struct cpu_info *tmp;
241 1.34 cegger ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
242 1.34 cegger KM_SLEEP);
243 1.42 jym ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE);
244 1.24 ad ci->ci_curldt = -1;
245 1.52 bouyer
246 1.52 bouyer tmp = phycpu_info_list;
247 1.52 bouyer while (tmp->ci_next)
248 1.52 bouyer tmp = tmp->ci_next;
249 1.52 bouyer
250 1.52 bouyer tmp->ci_next = ci;
251 1.2 bouyer } else {
252 1.2 bouyer ci = &phycpu_info_primary;
253 1.2 bouyer }
254 1.2 bouyer
255 1.2 bouyer ci->ci_self = ci;
256 1.2 bouyer sc->sc_info = ci;
257 1.2 bouyer
258 1.2 bouyer ci->ci_dev = self;
259 1.50 jruoho ci->ci_acpiid = caa->cpu_id;
260 1.23 ad ci->ci_cpuid = caa->cpu_number;
261 1.16 cegger ci->ci_vcpu = NULL;
262 1.52 bouyer ci->ci_index = nphycpu++;
263 1.52 bouyer ci->ci_cpumask = (1 << cpu_index(ci));
264 1.2 bouyer
265 1.52 bouyer atomic_or_32(&phycpus_attached, ci->ci_cpumask);
266 1.38 cegger
267 1.52 bouyer if (!pmf_device_register(self, NULL, NULL))
268 1.52 bouyer aprint_error_dev(self, "couldn't establish power handler\n");
269 1.34 cegger
270 1.2 bouyer return;
271 1.2 bouyer }
272 1.2 bouyer
273 1.2 bouyer int
274 1.10 cegger vcpu_match(device_t parent, cfdata_t match, void *aux)
275 1.2 bouyer {
276 1.2 bouyer struct vcpu_attach_args *vcaa = aux;
277 1.2 bouyer
278 1.2 bouyer if (strcmp(vcaa->vcaa_name, match->cf_name) == 0)
279 1.2 bouyer return 1;
280 1.2 bouyer return 0;
281 1.2 bouyer }
282 1.2 bouyer
283 1.2 bouyer void
284 1.10 cegger vcpu_attach(device_t parent, device_t self, void *aux)
285 1.2 bouyer {
286 1.2 bouyer struct vcpu_attach_args *vcaa = aux;
287 1.2 bouyer
288 1.2 bouyer cpu_attach_common(parent, self, &vcaa->vcaa_caa);
289 1.2 bouyer }
290 1.2 bouyer
291 1.2 bouyer static void
292 1.2 bouyer cpu_vm_init(struct cpu_info *ci)
293 1.2 bouyer {
294 1.2 bouyer int ncolors = 2, i;
295 1.2 bouyer
296 1.2 bouyer for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
297 1.2 bouyer struct x86_cache_info *cai;
298 1.2 bouyer int tcolors;
299 1.2 bouyer
300 1.2 bouyer cai = &ci->ci_cinfo[i];
301 1.2 bouyer
302 1.2 bouyer tcolors = atop(cai->cai_totalsize);
303 1.2 bouyer switch(cai->cai_associativity) {
304 1.2 bouyer case 0xff:
305 1.2 bouyer tcolors = 1; /* fully associative */
306 1.2 bouyer break;
307 1.2 bouyer case 0:
308 1.2 bouyer case 1:
309 1.2 bouyer break;
310 1.2 bouyer default:
311 1.2 bouyer tcolors /= cai->cai_associativity;
312 1.2 bouyer }
313 1.2 bouyer ncolors = max(ncolors, tcolors);
314 1.2 bouyer }
315 1.2 bouyer
316 1.2 bouyer /*
317 1.2 bouyer * Knowing the size of the largest cache on this CPU, re-color
318 1.2 bouyer * our pages.
319 1.2 bouyer */
320 1.2 bouyer if (ncolors <= uvmexp.ncolors)
321 1.2 bouyer return;
322 1.28 bouyer aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors);
323 1.2 bouyer uvm_page_recolor(ncolors);
324 1.2 bouyer }
325 1.2 bouyer
326 1.2 bouyer void
327 1.11 cegger cpu_attach_common(device_t parent, device_t self, void *aux)
328 1.2 bouyer {
329 1.10 cegger struct cpu_softc *sc = device_private(self);
330 1.2 bouyer struct cpu_attach_args *caa = aux;
331 1.2 bouyer struct cpu_info *ci;
332 1.12 cegger uintptr_t ptr;
333 1.2 bouyer int cpunum = caa->cpu_number;
334 1.38 cegger static bool again = false;
335 1.2 bouyer
336 1.10 cegger sc->sc_dev = self;
337 1.10 cegger
338 1.2 bouyer /*
339 1.2 bouyer * If we're an Application Processor, allocate a cpu_info
340 1.2 bouyer * structure, otherwise use the primary's.
341 1.2 bouyer */
342 1.2 bouyer if (caa->cpu_role == CPU_ROLE_AP) {
343 1.12 cegger aprint_naive(": Application Processor\n");
344 1.31 cegger ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
345 1.31 cegger KM_SLEEP);
346 1.42 jym ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE);
347 1.12 cegger memset(ci, 0, sizeof(*ci));
348 1.2 bouyer #ifdef TRAPLOG
349 1.31 cegger ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP);
350 1.2 bouyer #endif
351 1.2 bouyer } else {
352 1.12 cegger aprint_naive(": %s Processor\n",
353 1.12 cegger caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
354 1.2 bouyer ci = &cpu_info_primary;
355 1.38 cegger #if NLAPIC > 0
356 1.38 cegger if (cpunum != lapic_cpu_number()) {
357 1.38 cegger /* XXX should be done earlier */
358 1.38 cegger uint32_t reg;
359 1.38 cegger aprint_verbose("\n");
360 1.38 cegger aprint_verbose_dev(self, "running CPU at apic %d"
361 1.38 cegger " instead of at expected %d", lapic_cpu_number(),
362 1.38 cegger cpunum);
363 1.38 cegger reg = i82489_readreg(LAPIC_ID);
364 1.38 cegger i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) |
365 1.38 cegger (cpunum << LAPIC_ID_SHIFT));
366 1.38 cegger }
367 1.2 bouyer if (cpunum != lapic_cpu_number()) {
368 1.38 cegger aprint_error_dev(self, "unable to reset apic id\n");
369 1.2 bouyer }
370 1.2 bouyer #endif
371 1.2 bouyer }
372 1.2 bouyer
373 1.2 bouyer ci->ci_self = ci;
374 1.2 bouyer sc->sc_info = ci;
375 1.2 bouyer ci->ci_dev = self;
376 1.23 ad ci->ci_cpuid = cpunum;
377 1.16 cegger
378 1.16 cegger KASSERT(HYPERVISOR_shared_info != NULL);
379 1.16 cegger ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum];
380 1.16 cegger
381 1.2 bouyer ci->ci_func = caa->cpu_func;
382 1.2 bouyer
383 1.38 cegger /* Must be called before mi_cpu_attach(). */
384 1.38 cegger cpu_vm_init(ci);
385 1.38 cegger
386 1.2 bouyer if (caa->cpu_role == CPU_ROLE_AP) {
387 1.2 bouyer int error;
388 1.2 bouyer
389 1.2 bouyer error = mi_cpu_attach(ci);
390 1.2 bouyer if (error != 0) {
391 1.2 bouyer aprint_normal("\n");
392 1.38 cegger aprint_error_dev(self,
393 1.38 cegger "mi_cpu_attach failed with %d\n", error);
394 1.2 bouyer return;
395 1.2 bouyer }
396 1.2 bouyer } else {
397 1.2 bouyer KASSERT(ci->ci_data.cpu_idlelwp != NULL);
398 1.2 bouyer }
399 1.2 bouyer
400 1.23 ad ci->ci_cpumask = (1 << cpu_index(ci));
401 1.2 bouyer pmap_reference(pmap_kernel());
402 1.2 bouyer ci->ci_pmap = pmap_kernel();
403 1.2 bouyer ci->ci_tlbstate = TLBSTATE_STALE;
404 1.2 bouyer
405 1.38 cegger /*
406 1.38 cegger * Boot processor may not be attached first, but the below
407 1.38 cegger * must be done to allow booting other processors.
408 1.38 cegger */
409 1.38 cegger if (!again) {
410 1.38 cegger atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
411 1.38 cegger /* Basic init. */
412 1.38 cegger cpu_intr_init(ci);
413 1.38 cegger cpu_get_tsc_freq(ci);
414 1.38 cegger cpu_init(ci);
415 1.38 cegger cpu_set_tss_gates(ci);
416 1.38 cegger pmap_cpu_init_late(ci);
417 1.38 cegger #if NLAPIC > 0
418 1.38 cegger if (caa->cpu_role != CPU_ROLE_SP) {
419 1.38 cegger /* Enable lapic. */
420 1.38 cegger lapic_enable();
421 1.38 cegger lapic_set_lvt();
422 1.38 cegger lapic_calibrate_timer();
423 1.38 cegger }
424 1.38 cegger #endif
425 1.38 cegger /* Make sure DELAY() is initialized. */
426 1.38 cegger DELAY(1);
427 1.38 cegger again = true;
428 1.38 cegger }
429 1.38 cegger
430 1.2 bouyer /* further PCB init done later. */
431 1.2 bouyer
432 1.2 bouyer switch (caa->cpu_role) {
433 1.2 bouyer case CPU_ROLE_SP:
434 1.38 cegger atomic_or_32(&ci->ci_flags, CPUF_SP);
435 1.21 ad cpu_identify(ci);
436 1.12 cegger #if 0
437 1.12 cegger x86_errata();
438 1.12 cegger #endif
439 1.38 cegger x86_cpu_idle_init();
440 1.2 bouyer break;
441 1.2 bouyer
442 1.2 bouyer case CPU_ROLE_BP:
443 1.38 cegger atomic_or_32(&ci->ci_flags, CPUF_BSP);
444 1.21 ad cpu_identify(ci);
445 1.2 bouyer cpu_init(ci);
446 1.14 bouyer #if 0
447 1.12 cegger x86_errata();
448 1.12 cegger #endif
449 1.38 cegger x86_cpu_idle_init();
450 1.2 bouyer break;
451 1.2 bouyer
452 1.2 bouyer case CPU_ROLE_AP:
453 1.2 bouyer /*
454 1.2 bouyer * report on an AP
455 1.2 bouyer */
456 1.2 bouyer
457 1.2 bouyer #if defined(MULTIPROCESSOR)
458 1.2 bouyer cpu_intr_init(ci);
459 1.2 bouyer gdt_alloc_cpu(ci);
460 1.2 bouyer cpu_set_tss_gates(ci);
461 1.12 cegger pmap_cpu_init_early(ci);
462 1.12 cegger pmap_cpu_init_late(ci);
463 1.2 bouyer cpu_start_secondary(ci);
464 1.2 bouyer if (ci->ci_flags & CPUF_PRESENT) {
465 1.30 cegger struct cpu_info *tmp;
466 1.30 cegger
467 1.2 bouyer identifycpu(ci);
468 1.30 cegger tmp = cpu_info_list;
469 1.30 cegger while (tmp->ci_next)
470 1.30 cegger tmp = tmp->ci_next;
471 1.30 cegger
472 1.30 cegger tmp->ci_next = ci;
473 1.2 bouyer }
474 1.2 bouyer #else
475 1.38 cegger aprint_error_dev(self, "not started\n");
476 1.2 bouyer #endif
477 1.2 bouyer break;
478 1.2 bouyer
479 1.2 bouyer default:
480 1.12 cegger aprint_normal("\n");
481 1.2 bouyer panic("unknown processor type??\n");
482 1.2 bouyer }
483 1.2 bouyer
484 1.46 cegger pat_init(ci);
485 1.34 cegger atomic_or_32(&cpus_attached, ci->ci_cpumask);
486 1.2 bouyer
487 1.12 cegger #if 0
488 1.12 cegger if (!pmf_device_register(self, cpu_suspend, cpu_resume))
489 1.12 cegger aprint_error_dev(self, "couldn't establish power handler\n");
490 1.12 cegger #endif
491 1.12 cegger
492 1.2 bouyer #if defined(MULTIPROCESSOR)
493 1.2 bouyer if (mp_verbose) {
494 1.2 bouyer struct lwp *l = ci->ci_data.cpu_idlelwp;
495 1.37 rmind struct pcb *pcb = lwp_getpcb(l);
496 1.2 bouyer
497 1.38 cegger aprint_verbose_dev(self,
498 1.38 cegger "idle lwp at %p, idle sp at 0x%p\n",
499 1.12 cegger l,
500 1.12 cegger #ifdef i386
501 1.37 rmind (void *)pcb->pcb_esp
502 1.12 cegger #else
503 1.37 rmind (void *)pcb->pcb_rsp
504 1.12 cegger #endif
505 1.12 cegger );
506 1.12 cegger
507 1.2 bouyer }
508 1.2 bouyer #endif
509 1.2 bouyer }
510 1.2 bouyer
511 1.2 bouyer /*
512 1.2 bouyer * Initialize the processor appropriately.
513 1.2 bouyer */
514 1.2 bouyer
515 1.2 bouyer void
516 1.10 cegger cpu_init(struct cpu_info *ci)
517 1.2 bouyer {
518 1.2 bouyer
519 1.2 bouyer /*
520 1.2 bouyer * On a P6 or above, enable global TLB caching if the
521 1.2 bouyer * hardware supports it.
522 1.2 bouyer */
523 1.43 jym if (cpu_feature[0] & CPUID_PGE)
524 1.2 bouyer lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */
525 1.2 bouyer
526 1.2 bouyer #ifdef XXXMTRR
527 1.2 bouyer /*
528 1.2 bouyer * On a P6 or above, initialize MTRR's if the hardware supports them.
529 1.2 bouyer */
530 1.43 jym if (cpu_feature[0] & CPUID_MTRR) {
531 1.2 bouyer if ((ci->ci_flags & CPUF_AP) == 0)
532 1.2 bouyer i686_mtrr_init_first();
533 1.2 bouyer mtrr_init_cpu(ci);
534 1.2 bouyer }
535 1.2 bouyer #endif
536 1.2 bouyer /*
537 1.2 bouyer * If we have FXSAVE/FXRESTOR, use them.
538 1.2 bouyer */
539 1.43 jym if (cpu_feature[0] & CPUID_FXSR) {
540 1.2 bouyer lcr4(rcr4() | CR4_OSFXSR);
541 1.2 bouyer
542 1.2 bouyer /*
543 1.2 bouyer * If we have SSE/SSE2, enable XMM exceptions.
544 1.2 bouyer */
545 1.43 jym if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2))
546 1.2 bouyer lcr4(rcr4() | CR4_OSXMMEXCPT);
547 1.2 bouyer }
548 1.2 bouyer
549 1.47 jym #ifdef __x86_64__
550 1.47 jym /* No user PGD mapped for this CPU yet */
551 1.47 jym ci->ci_xen_current_user_pgd = 0;
552 1.47 jym #endif
553 1.47 jym
554 1.34 cegger atomic_or_32(&cpus_running, ci->ci_cpumask);
555 1.11 cegger atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
556 1.2 bouyer }
557 1.2 bouyer
558 1.2 bouyer
559 1.2 bouyer #ifdef MULTIPROCESSOR
560 1.2 bouyer void
561 1.10 cegger cpu_boot_secondary_processors(void)
562 1.2 bouyer {
563 1.2 bouyer struct cpu_info *ci;
564 1.2 bouyer u_long i;
565 1.2 bouyer
566 1.38 cegger for (i = 0; i < maxcpus; i++) {
567 1.38 cegger ci = cpu_lookup(i);
568 1.2 bouyer if (ci == NULL)
569 1.2 bouyer continue;
570 1.2 bouyer if (ci->ci_data.cpu_idlelwp == NULL)
571 1.2 bouyer continue;
572 1.2 bouyer if ((ci->ci_flags & CPUF_PRESENT) == 0)
573 1.2 bouyer continue;
574 1.2 bouyer if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY))
575 1.2 bouyer continue;
576 1.2 bouyer cpu_boot_secondary(ci);
577 1.2 bouyer }
578 1.11 cegger
579 1.11 cegger x86_mp_online = true;
580 1.2 bouyer }
581 1.2 bouyer
582 1.2 bouyer static void
583 1.2 bouyer cpu_init_idle_lwp(struct cpu_info *ci)
584 1.2 bouyer {
585 1.2 bouyer struct lwp *l = ci->ci_data.cpu_idlelwp;
586 1.37 rmind struct pcb *pcb = lwp_getpcb(l);
587 1.2 bouyer
588 1.2 bouyer pcb->pcb_cr0 = rcr0();
589 1.2 bouyer }
590 1.2 bouyer
591 1.2 bouyer void
592 1.10 cegger cpu_init_idle_lwps(void)
593 1.2 bouyer {
594 1.2 bouyer struct cpu_info *ci;
595 1.2 bouyer u_long i;
596 1.2 bouyer
597 1.38 cegger for (i = 0; i < maxcpus; i++) {
598 1.38 cegger ci = cpu_lookup(i);
599 1.2 bouyer if (ci == NULL)
600 1.2 bouyer continue;
601 1.2 bouyer if (ci->ci_data.cpu_idlelwp == NULL)
602 1.2 bouyer continue;
603 1.2 bouyer if ((ci->ci_flags & CPUF_PRESENT) == 0)
604 1.2 bouyer continue;
605 1.2 bouyer cpu_init_idle_lwp(ci);
606 1.2 bouyer }
607 1.2 bouyer }
608 1.2 bouyer
609 1.2 bouyer void
610 1.10 cegger cpu_start_secondary(struct cpu_info *ci)
611 1.2 bouyer {
612 1.2 bouyer int i;
613 1.2 bouyer struct pmap *kpm = pmap_kernel();
614 1.11 cegger extern uint32_t mp_pdirpa;
615 1.2 bouyer
616 1.2 bouyer mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */
617 1.2 bouyer
618 1.11 cegger atomic_or_32(&ci->ci_flags, CPUF_AP);
619 1.2 bouyer
620 1.11 cegger aprint_debug_dev(ci->ci_dev, "starting\n");
621 1.2 bouyer
622 1.2 bouyer ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
623 1.11 cegger if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0)
624 1.11 cegger return;
625 1.2 bouyer
626 1.2 bouyer /*
627 1.2 bouyer * wait for it to become ready
628 1.2 bouyer */
629 1.11 cegger for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) {
630 1.11 cegger #ifdef MPDEBUG
631 1.11 cegger extern int cpu_trace[3];
632 1.11 cegger static int otrace[3];
633 1.11 cegger if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) {
634 1.11 cegger aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n",
635 1.11 cegger cpu_trace[0], cpu_trace[1], cpu_trace[2]);
636 1.11 cegger memcpy(otrace, cpu_trace, sizeof(otrace));
637 1.11 cegger }
638 1.11 cegger #endif
639 1.2 bouyer delay(10);
640 1.2 bouyer }
641 1.11 cegger if ((ci->ci_flags & CPUF_PRESENT) == 0) {
642 1.9 cegger aprint_error_dev(ci->ci_dev, "failed to become ready\n");
643 1.2 bouyer #if defined(MPDEBUG) && defined(DDB)
644 1.2 bouyer printf("dropping into debugger; continue from here to resume boot\n");
645 1.2 bouyer Debugger();
646 1.2 bouyer #endif
647 1.2 bouyer }
648 1.2 bouyer
649 1.2 bouyer CPU_START_CLEANUP(ci);
650 1.2 bouyer }
651 1.2 bouyer
652 1.2 bouyer void
653 1.10 cegger cpu_boot_secondary(struct cpu_info *ci)
654 1.2 bouyer {
655 1.2 bouyer int i;
656 1.2 bouyer
657 1.11 cegger atomic_or_32(&ci->ci_flags, CPUF_GO);
658 1.11 cegger for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) {
659 1.2 bouyer delay(10);
660 1.2 bouyer }
661 1.11 cegger if ((ci->ci_flags & CPUF_RUNNING) == 0) {
662 1.11 cegger aprint_error_dev(ci->ci_dev, "CPU failed to start\n");
663 1.2 bouyer #if defined(MPDEBUG) && defined(DDB)
664 1.2 bouyer printf("dropping into debugger; continue from here to resume boot\n");
665 1.2 bouyer Debugger();
666 1.2 bouyer #endif
667 1.2 bouyer }
668 1.2 bouyer }
669 1.2 bouyer
670 1.2 bouyer /*
671 1.2 bouyer * The CPU ends up here when its ready to run
672 1.2 bouyer * This is called from code in mptramp.s; at this point, we are running
673 1.2 bouyer * in the idle pcb/idle stack of the new CPU. When this function returns,
674 1.2 bouyer * this processor will enter the idle loop and start looking for work.
675 1.2 bouyer *
676 1.2 bouyer * XXX should share some of this with init386 in machdep.c
677 1.2 bouyer */
678 1.2 bouyer void
679 1.2 bouyer cpu_hatch(void *v)
680 1.2 bouyer {
681 1.2 bouyer struct cpu_info *ci = (struct cpu_info *)v;
682 1.37 rmind struct pcb *pcb;
683 1.11 cegger int s, i;
684 1.11 cegger
685 1.21 ad cpu_probe(ci);
686 1.11 cegger
687 1.43 jym cpu_feature[0] &= ~CPUID_FEAT_BLACKLIST;
688 1.43 jym cpu_feature[2] &= ~CPUID_FEAT_EXT_BLACKLIST;
689 1.2 bouyer
690 1.43 jym cpu_init_msrs(ci, true);
691 1.2 bouyer
692 1.11 cegger KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
693 1.11 cegger atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
694 1.11 cegger while ((ci->ci_flags & CPUF_GO) == 0) {
695 1.11 cegger /* Don't use delay, boot CPU may be patching the text. */
696 1.11 cegger for (i = 10000; i != 0; i--)
697 1.11 cegger x86_pause();
698 1.11 cegger }
699 1.2 bouyer
700 1.11 cegger /* Because the text may have been patched in x86_patch(). */
701 1.11 cegger wbinvd();
702 1.11 cegger x86_flush();
703 1.2 bouyer
704 1.11 cegger KASSERT((ci->ci_flags & CPUF_RUNNING) == 0);
705 1.2 bouyer
706 1.37 rmind pcb = lwp_getpcb(curlwp);
707 1.12 cegger lcr3(pmap_kernel()->pm_pdirpa);
708 1.37 rmind pcb->pcb_cr3 = pmap_kernel()->pm_pdirpa;
709 1.37 rmind pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp);
710 1.37 rmind lcr0(pcb->pcb_cr0);
711 1.37 rmind
712 1.2 bouyer cpu_init_idt();
713 1.11 cegger gdt_init_cpu(ci);
714 1.11 cegger lapic_enable();
715 1.2 bouyer lapic_set_lvt();
716 1.11 cegger lapic_initclocks();
717 1.11 cegger
718 1.12 cegger #ifdef i386
719 1.2 bouyer npxinit(ci);
720 1.12 cegger #else
721 1.12 cegger fpuinit(ci);
722 1.12 cegger #endif
723 1.2 bouyer
724 1.2 bouyer lldt(GSEL(GLDT_SEL, SEL_KPL));
725 1.12 cegger ltr(ci->ci_tss_sel);
726 1.2 bouyer
727 1.2 bouyer cpu_init(ci);
728 1.11 cegger cpu_get_tsc_freq(ci);
729 1.2 bouyer
730 1.2 bouyer s = splhigh();
731 1.11 cegger #ifdef i386
732 1.2 bouyer lapic_tpr = 0;
733 1.11 cegger #else
734 1.11 cegger lcr8(0);
735 1.11 cegger #endif
736 1.11 cegger x86_enable_intr();
737 1.11 cegger splx(s);
738 1.12 cegger #if 0
739 1.11 cegger x86_errata();
740 1.11 cegger #endif
741 1.2 bouyer
742 1.11 cegger aprint_debug_dev(ci->ci_dev, "CPU %ld running\n",
743 1.11 cegger (long)ci->ci_cpuid);
744 1.2 bouyer }
745 1.2 bouyer
746 1.2 bouyer #if defined(DDB)
747 1.2 bouyer
748 1.2 bouyer #include <ddb/db_output.h>
749 1.2 bouyer #include <machine/db_machdep.h>
750 1.2 bouyer
751 1.2 bouyer /*
752 1.2 bouyer * Dump CPU information from ddb.
753 1.2 bouyer */
754 1.2 bouyer void
755 1.2 bouyer cpu_debug_dump(void)
756 1.2 bouyer {
757 1.2 bouyer struct cpu_info *ci;
758 1.2 bouyer CPU_INFO_ITERATOR cii;
759 1.2 bouyer
760 1.13 yamt db_printf("addr dev id flags ipis curlwp fpcurlwp\n");
761 1.2 bouyer for (CPU_INFO_FOREACH(cii, ci)) {
762 1.2 bouyer db_printf("%p %s %ld %x %x %10p %10p\n",
763 1.2 bouyer ci,
764 1.9 cegger ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev),
765 1.12 cegger (long)ci->ci_cpuid,
766 1.2 bouyer ci->ci_flags, ci->ci_ipis,
767 1.2 bouyer ci->ci_curlwp,
768 1.2 bouyer ci->ci_fpcurlwp);
769 1.2 bouyer }
770 1.2 bouyer }
771 1.38 cegger #endif /* DDB */
772 1.2 bouyer
773 1.2 bouyer static void
774 1.10 cegger cpu_copy_trampoline(void)
775 1.2 bouyer {
776 1.2 bouyer /*
777 1.2 bouyer * Copy boot code.
778 1.2 bouyer */
779 1.2 bouyer extern u_char cpu_spinup_trampoline[];
780 1.2 bouyer extern u_char cpu_spinup_trampoline_end[];
781 1.11 cegger
782 1.11 cegger vaddr_t mp_trampoline_vaddr;
783 1.11 cegger
784 1.11 cegger mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
785 1.11 cegger UVM_KMF_VAONLY);
786 1.11 cegger
787 1.11 cegger pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr,
788 1.36 cegger VM_PROT_READ | VM_PROT_WRITE, 0);
789 1.11 cegger pmap_update(pmap_kernel());
790 1.11 cegger memcpy((void *)mp_trampoline_vaddr,
791 1.11 cegger cpu_spinup_trampoline,
792 1.11 cegger cpu_spinup_trampoline_end - cpu_spinup_trampoline);
793 1.11 cegger
794 1.11 cegger pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE);
795 1.11 cegger pmap_update(pmap_kernel());
796 1.11 cegger uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
797 1.2 bouyer }
798 1.2 bouyer
799 1.38 cegger #endif /* MULTIPROCESSOR */
800 1.2 bouyer
801 1.11 cegger #ifdef i386
802 1.11 cegger #if 0
803 1.11 cegger static void
804 1.11 cegger tss_init(struct i386tss *tss, void *stack, void *func)
805 1.11 cegger {
806 1.11 cegger memset(tss, 0, sizeof *tss);
807 1.11 cegger tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
808 1.11 cegger tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
809 1.11 cegger tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
810 1.11 cegger tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
811 1.11 cegger tss->tss_gs = tss->__tss_es = tss->__tss_ds =
812 1.11 cegger tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
813 1.11 cegger tss->tss_cr3 = pmap_kernel()->pm_pdirpa;
814 1.11 cegger tss->tss_esp = (int)((char *)stack + USPACE - 16);
815 1.11 cegger tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
816 1.11 cegger tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */
817 1.11 cegger tss->__tss_eip = (int)func;
818 1.11 cegger }
819 1.11 cegger #endif
820 1.2 bouyer
821 1.2 bouyer /* XXX */
822 1.2 bouyer #define IDTVEC(name) __CONCAT(X, name)
823 1.2 bouyer typedef void (vector)(void);
824 1.2 bouyer extern vector IDTVEC(tss_trap08);
825 1.2 bouyer #ifdef DDB
826 1.2 bouyer extern vector Xintrddbipi;
827 1.2 bouyer extern int ddb_vec;
828 1.2 bouyer #endif
829 1.2 bouyer
830 1.2 bouyer static void
831 1.2 bouyer cpu_set_tss_gates(struct cpu_info *ci)
832 1.2 bouyer {
833 1.11 cegger #if 0
834 1.11 cegger struct segment_descriptor sd;
835 1.11 cegger
836 1.11 cegger ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
837 1.11 cegger UVM_KMF_WIRED);
838 1.11 cegger tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
839 1.11 cegger IDTVEC(tss_trap08));
840 1.11 cegger setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
841 1.11 cegger SDT_SYS386TSS, SEL_KPL, 0, 0);
842 1.11 cegger ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
843 1.11 cegger setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
844 1.11 cegger GSEL(GTRAPTSS_SEL, SEL_KPL));
845 1.11 cegger #endif
846 1.11 cegger
847 1.2 bouyer #if defined(DDB) && defined(MULTIPROCESSOR)
848 1.2 bouyer /*
849 1.2 bouyer * Set up separate handler for the DDB IPI, so that it doesn't
850 1.2 bouyer * stomp on a possibly corrupted stack.
851 1.2 bouyer *
852 1.2 bouyer * XXX overwriting the gate set in db_machine_init.
853 1.2 bouyer * Should rearrange the code so that it's set only once.
854 1.2 bouyer */
855 1.2 bouyer ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
856 1.2 bouyer UVM_KMF_WIRED);
857 1.6 yamt tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack,
858 1.2 bouyer Xintrddbipi);
859 1.2 bouyer
860 1.2 bouyer setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
861 1.2 bouyer SDT_SYS386TSS, SEL_KPL, 0, 0);
862 1.2 bouyer ci->ci_gdt[GIPITSS_SEL].sd = sd;
863 1.2 bouyer
864 1.2 bouyer setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
865 1.2 bouyer GSEL(GIPITSS_SEL, SEL_KPL));
866 1.2 bouyer #endif
867 1.2 bouyer }
868 1.11 cegger #else
869 1.11 cegger static void
870 1.11 cegger cpu_set_tss_gates(struct cpu_info *ci)
871 1.11 cegger {
872 1.11 cegger
873 1.11 cegger }
874 1.11 cegger #endif /* i386 */
875 1.2 bouyer
876 1.2 bouyer int
877 1.5 joerg mp_cpu_start(struct cpu_info *ci, paddr_t target)
878 1.2 bouyer {
879 1.2 bouyer #if 0
880 1.2 bouyer #if NLAPIC > 0
881 1.2 bouyer int error;
882 1.2 bouyer #endif
883 1.2 bouyer unsigned short dwordptr[2];
884 1.2 bouyer
885 1.2 bouyer /*
886 1.11 cegger * Bootstrap code must be addressable in real mode
887 1.11 cegger * and it must be page aligned.
888 1.11 cegger */
889 1.11 cegger KASSERT(target < 0x10000 && target % PAGE_SIZE == 0);
890 1.11 cegger
891 1.11 cegger /*
892 1.2 bouyer * "The BSP must initialize CMOS shutdown code to 0Ah ..."
893 1.2 bouyer */
894 1.2 bouyer
895 1.2 bouyer outb(IO_RTC, NVRAM_RESET);
896 1.2 bouyer outb(IO_RTC+1, NVRAM_RESET_JUMP);
897 1.2 bouyer
898 1.2 bouyer /*
899 1.2 bouyer * "and the warm reset vector (DWORD based at 40:67) to point
900 1.2 bouyer * to the AP startup code ..."
901 1.2 bouyer */
902 1.2 bouyer
903 1.2 bouyer dwordptr[0] = 0;
904 1.5 joerg dwordptr[1] = target >> 4;
905 1.2 bouyer
906 1.36 cegger pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE, 0);
907 1.45 rmind pmap_update(pmap_kernel());
908 1.45 rmind
909 1.11 cegger memcpy ((uint8_t *) 0x467, dwordptr, 4);
910 1.45 rmind
911 1.2 bouyer pmap_kremove (0, PAGE_SIZE);
912 1.45 rmind pmap_update(pmap_kernel());
913 1.2 bouyer
914 1.2 bouyer #if NLAPIC > 0
915 1.2 bouyer /*
916 1.2 bouyer * ... prior to executing the following sequence:"
917 1.2 bouyer */
918 1.2 bouyer
919 1.2 bouyer if (ci->ci_flags & CPUF_AP) {
920 1.23 ad if ((error = x86_ipi_init(ci->ci_cpuid)) != 0)
921 1.2 bouyer return error;
922 1.2 bouyer
923 1.2 bouyer delay(10000);
924 1.2 bouyer
925 1.2 bouyer if (cpu_feature & CPUID_APIC) {
926 1.23 ad error = x86_ipi_init(ci->ci_cpuid);
927 1.11 cegger if (error != 0) {
928 1.11 cegger aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n",
929 1.11 cegger __func__);
930 1.11 cegger return error;
931 1.11 cegger }
932 1.11 cegger
933 1.11 cegger delay(10000);
934 1.2 bouyer
935 1.23 ad error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
936 1.11 cegger LAPIC_DLMODE_STARTUP);
937 1.11 cegger if (error != 0) {
938 1.11 cegger aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n",
939 1.11 cegger __func__);
940 1.2 bouyer return error;
941 1.11 cegger }
942 1.2 bouyer delay(200);
943 1.2 bouyer
944 1.23 ad error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
945 1.11 cegger LAPIC_DLMODE_STARTUP);
946 1.11 cegger if (error != 0) {
947 1.11 cegger aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n",
948 1.11 cegger __func__);
949 1.2 bouyer return error;
950 1.11 cegger }
951 1.2 bouyer delay(200);
952 1.2 bouyer }
953 1.2 bouyer }
954 1.2 bouyer #endif
955 1.2 bouyer #endif /* 0 */
956 1.2 bouyer return 0;
957 1.2 bouyer }
958 1.2 bouyer
959 1.2 bouyer void
960 1.2 bouyer mp_cpu_start_cleanup(struct cpu_info *ci)
961 1.2 bouyer {
962 1.2 bouyer #if 0
963 1.2 bouyer /*
964 1.2 bouyer * Ensure the NVRAM reset byte contains something vaguely sane.
965 1.2 bouyer */
966 1.2 bouyer
967 1.2 bouyer outb(IO_RTC, NVRAM_RESET);
968 1.2 bouyer outb(IO_RTC+1, NVRAM_RESET_RST);
969 1.2 bouyer #endif
970 1.2 bouyer }
971 1.2 bouyer
972 1.2 bouyer void
973 1.3 bouyer cpu_init_msrs(struct cpu_info *ci, bool full)
974 1.2 bouyer {
975 1.43 jym #ifdef __x86_64__
976 1.3 bouyer if (full) {
977 1.3 bouyer HYPERVISOR_set_segment_base (SEGBASE_FS, 0);
978 1.11 cegger HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci);
979 1.3 bouyer HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0);
980 1.3 bouyer }
981 1.43 jym #endif /* __x86_64__ */
982 1.44 jym
983 1.44 jym if (cpu_feature[2] & CPUID_NOX)
984 1.44 jym wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
985 1.2 bouyer }
986 1.2 bouyer
987 1.11 cegger void
988 1.11 cegger cpu_offline_md(void)
989 1.11 cegger {
990 1.11 cegger int s;
991 1.11 cegger
992 1.11 cegger s = splhigh();
993 1.11 cegger #ifdef __i386__
994 1.11 cegger npxsave_cpu(true);
995 1.11 cegger #else
996 1.11 cegger fpusave_cpu(true);
997 1.11 cegger #endif
998 1.11 cegger splx(s);
999 1.11 cegger }
1000 1.11 cegger
1001 1.11 cegger #if 0
1002 1.11 cegger /* XXX joerg restructure and restart CPUs individually */
1003 1.11 cegger static bool
1004 1.41 dyoung cpu_suspend(device_t dv, const pmf_qual_t *qual)
1005 1.11 cegger {
1006 1.11 cegger struct cpu_softc *sc = device_private(dv);
1007 1.11 cegger struct cpu_info *ci = sc->sc_info;
1008 1.11 cegger int err;
1009 1.11 cegger
1010 1.11 cegger if (ci->ci_flags & CPUF_PRIMARY)
1011 1.11 cegger return true;
1012 1.11 cegger if (ci->ci_data.cpu_idlelwp == NULL)
1013 1.11 cegger return true;
1014 1.11 cegger if ((ci->ci_flags & CPUF_PRESENT) == 0)
1015 1.11 cegger return true;
1016 1.11 cegger
1017 1.11 cegger sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE);
1018 1.11 cegger
1019 1.11 cegger if (sc->sc_wasonline) {
1020 1.11 cegger mutex_enter(&cpu_lock);
1021 1.29 rmind err = cpu_setstate(ci, false);
1022 1.11 cegger mutex_exit(&cpu_lock);
1023 1.11 cegger
1024 1.11 cegger if (err)
1025 1.11 cegger return false;
1026 1.11 cegger }
1027 1.11 cegger
1028 1.11 cegger return true;
1029 1.11 cegger }
1030 1.11 cegger
1031 1.11 cegger static bool
1032 1.41 dyoung cpu_resume(device_t dv, const pmf_qual_t *qual)
1033 1.11 cegger {
1034 1.11 cegger struct cpu_softc *sc = device_private(dv);
1035 1.11 cegger struct cpu_info *ci = sc->sc_info;
1036 1.11 cegger int err = 0;
1037 1.11 cegger
1038 1.11 cegger if (ci->ci_flags & CPUF_PRIMARY)
1039 1.11 cegger return true;
1040 1.11 cegger if (ci->ci_data.cpu_idlelwp == NULL)
1041 1.11 cegger return true;
1042 1.11 cegger if ((ci->ci_flags & CPUF_PRESENT) == 0)
1043 1.11 cegger return true;
1044 1.11 cegger
1045 1.11 cegger if (sc->sc_wasonline) {
1046 1.11 cegger mutex_enter(&cpu_lock);
1047 1.29 rmind err = cpu_setstate(ci, true);
1048 1.11 cegger mutex_exit(&cpu_lock);
1049 1.11 cegger }
1050 1.11 cegger
1051 1.11 cegger return err == 0;
1052 1.11 cegger }
1053 1.11 cegger #endif
1054 1.11 cegger
1055 1.2 bouyer void
1056 1.2 bouyer cpu_get_tsc_freq(struct cpu_info *ci)
1057 1.2 bouyer {
1058 1.16 cegger const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time;
1059 1.2 bouyer delay(1000000);
1060 1.2 bouyer uint64_t freq = 1000000000ULL << 32;
1061 1.2 bouyer freq = freq / (uint64_t)tinfo->tsc_to_system_mul;
1062 1.2 bouyer if ( tinfo->tsc_shift < 0 )
1063 1.2 bouyer freq = freq << -tinfo->tsc_shift;
1064 1.2 bouyer else
1065 1.2 bouyer freq = freq >> tinfo->tsc_shift;
1066 1.20 ad ci->ci_data.cpu_cc_freq = freq;
1067 1.2 bouyer }
1068 1.19 joerg
1069 1.19 joerg void
1070 1.19 joerg x86_cpu_idle_xen(void)
1071 1.19 joerg {
1072 1.19 joerg struct cpu_info *ci = curcpu();
1073 1.19 joerg
1074 1.19 joerg KASSERT(ci->ci_ilevel == IPL_NONE);
1075 1.19 joerg
1076 1.19 joerg x86_disable_intr();
1077 1.19 joerg if (!__predict_false(ci->ci_want_resched)) {
1078 1.19 joerg idle_block();
1079 1.19 joerg } else {
1080 1.19 joerg x86_enable_intr();
1081 1.19 joerg }
1082 1.19 joerg }
1083 1.47 jym
1084 1.47 jym /*
1085 1.47 jym * Loads pmap for the current CPU.
1086 1.47 jym */
1087 1.47 jym void
1088 1.47 jym cpu_load_pmap(struct pmap *pmap)
1089 1.47 jym {
1090 1.47 jym #ifdef i386
1091 1.47 jym #ifdef PAE
1092 1.47 jym int i, s;
1093 1.47 jym struct cpu_info *ci;
1094 1.47 jym
1095 1.47 jym s = splvm(); /* just to be safe */
1096 1.47 jym ci = curcpu();
1097 1.47 jym paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa);
1098 1.47 jym /* don't update the kernel L3 slot */
1099 1.47 jym for (i = 0 ; i < PDP_SIZE - 1; i++) {
1100 1.47 jym xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t),
1101 1.47 jym xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V);
1102 1.47 jym }
1103 1.47 jym splx(s);
1104 1.47 jym tlbflush();
1105 1.47 jym #else /* PAE */
1106 1.47 jym lcr3(pmap_pdirpa(pmap, 0));
1107 1.47 jym #endif /* PAE */
1108 1.47 jym #endif /* i386 */
1109 1.47 jym
1110 1.47 jym #ifdef __x86_64__
1111 1.47 jym int i, s;
1112 1.47 jym pd_entry_t *old_pgd, *new_pgd;
1113 1.47 jym paddr_t addr;
1114 1.47 jym struct cpu_info *ci;
1115 1.47 jym
1116 1.47 jym /* kernel pmap always in cr3 and should never go in user cr3 */
1117 1.47 jym if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) {
1118 1.47 jym ci = curcpu();
1119 1.47 jym /*
1120 1.47 jym * Map user space address in kernel space and load
1121 1.47 jym * user cr3
1122 1.47 jym */
1123 1.47 jym s = splvm();
1124 1.47 jym new_pgd = pmap->pm_pdir;
1125 1.47 jym old_pgd = pmap_kernel()->pm_pdir;
1126 1.47 jym addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0));
1127 1.47 jym for (i = 0; i < PDIR_SLOT_PTE;
1128 1.47 jym i++, addr += sizeof(pd_entry_t)) {
1129 1.47 jym if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V))
1130 1.47 jym xpq_queue_pte_update(addr, new_pgd[i]);
1131 1.47 jym }
1132 1.47 jym tlbflush();
1133 1.47 jym xen_set_user_pgd(pmap_pdirpa(pmap, 0));
1134 1.47 jym ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0);
1135 1.47 jym splx(s);
1136 1.47 jym }
1137 1.47 jym #endif /* __x86_64__ */
1138 1.47 jym }
1139