cpu.c revision 1.1.2.2
1 /* $NetBSD: cpu.c,v 1.1.2.2 2007/10/25 23:59:24 bouyer Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Copyright (c) 1999 Stefan Grefen 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the NetBSD 56 * Foundation, Inc. and its contributors. 57 * 4. Neither the name of The NetBSD Foundation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 62 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.1.2.2 2007/10/25 23:59:24 bouyer Exp $"); 76 77 #include "opt_ddb.h" 78 #include "opt_multiprocessor.h" 79 #include "opt_mpbios.h" /* for MPDEBUG */ 80 #include "opt_mtrr.h" 81 #include "opt_xen.h" 82 83 #include "lapic.h" 84 #include "ioapic.h" 85 86 #include <sys/param.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/cpu.h> 96 #include <machine/cpufunc.h> 97 #include <machine/cpuvar.h> 98 #include <machine/pmap.h> 99 #include <machine/vmparam.h> 100 #include <machine/mpbiosvar.h> 101 #include <machine/pcb.h> 102 #include <machine/specialreg.h> 103 #include <machine/segments.h> 104 #include <machine/gdt.h> 105 #include <machine/mtrr.h> 106 #include <machine/pio.h> 107 108 #ifdef XEN3 109 #include <xen/vcpuvar.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #if NIOAPIC > 0 119 #include <machine/i82093var.h> 120 #endif 121 122 #include <dev/ic/mc146818reg.h> 123 #include <dev/isa/isareg.h> 124 125 int cpu_match(struct device *, struct cfdata *, void *); 126 void cpu_attach(struct device *, struct device *, void *); 127 #ifdef XEN3 128 int vcpu_match(struct device *, struct cfdata *, void *); 129 void vcpu_attach(struct device *, struct device *, void *); 130 #endif 131 void cpu_attach_common(struct device *, struct device *, void *); 132 133 struct cpu_softc { 134 struct device sc_dev; /* device tree glue */ 135 struct cpu_info *sc_info; /* pointer to CPU info */ 136 }; 137 138 int mp_cpu_start(struct cpu_info *); 139 void mp_cpu_start_cleanup(struct cpu_info *); 140 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 141 mp_cpu_start_cleanup }; 142 143 CFATTACH_DECL(cpu, sizeof(struct cpu_softc), 144 cpu_match, cpu_attach, NULL, NULL); 145 #ifdef XEN3 146 CFATTACH_DECL(vcpu, sizeof(struct cpu_softc), 147 vcpu_match, vcpu_attach, NULL, NULL); 148 #endif 149 150 /* 151 * Statically-allocated CPU info for the primary CPU (or the only 152 * CPU, on uniprocessors). The CPU info list is initialized to 153 * point at it. 154 */ 155 #ifdef TRAPLOG 156 #include <machine/tlog.h> 157 struct tlog tlog_primary; 158 #endif 159 struct cpu_info cpu_info_primary = { 160 .ci_self = &cpu_info_primary, 161 #ifndef __x86_64__ 162 .ci_self150 = (uint8_t *)&cpu_info_primary + 0x150, 163 #endif 164 .ci_curlwp = &lwp0, 165 #ifdef TRAPLOG 166 .ci_tlog = &tlog_primary, 167 #endif 168 169 }; 170 struct cpu_info phycpu_info_primary = { 171 .ci_self = &phycpu_info_primary, 172 #ifndef __x86_64__ 173 .ci_self150 = (uint8_t *)&phycpu_info_primary + 0x150, 174 #endif 175 }; 176 177 struct cpu_info *cpu_info_list = &cpu_info_primary; 178 179 static void cpu_set_tss_gates(struct cpu_info *ci); 180 181 u_int32_t cpus_attached = 0; 182 183 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 184 185 #ifdef MULTIPROCESSOR 186 /* 187 * Array of CPU info structures. Must be statically-allocated because 188 * curproc, etc. are used early. 189 */ 190 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 191 192 u_int32_t cpus_running = 0; 193 194 void cpu_hatch(void *); 195 static void cpu_boot_secondary(struct cpu_info *ci); 196 static void cpu_start_secondary(struct cpu_info *ci); 197 static void cpu_copy_trampoline(void); 198 199 /* 200 * Runs once per boot once multiprocessor goo has been detected and 201 * the local APIC on the boot processor has been mapped. 202 * 203 * Called from lapic_boot_init() (from mpbios_scan()). 204 */ 205 void 206 cpu_init_first() 207 { 208 int cpunum = lapic_cpu_number(); 209 210 if (cpunum != 0) { 211 cpu_info[0] = NULL; 212 cpu_info[cpunum] = &cpu_info_primary; 213 } 214 215 cpu_copy_trampoline(); 216 } 217 #endif 218 219 int 220 cpu_match(parent, match, aux) 221 struct device *parent; 222 struct cfdata *match; 223 void *aux; 224 { 225 226 return 1; 227 } 228 229 void 230 cpu_attach(parent, self, aux) 231 struct device *parent, *self; 232 void *aux; 233 { 234 #ifdef XEN3 235 struct cpu_softc *sc = (void *) self; 236 struct cpu_attach_args *caa = aux; 237 struct cpu_info *ci; 238 int cpunum = caa->cpu_number; 239 240 /* 241 * If we're an Application Processor, allocate a cpu_info 242 * structure, otherwise use the primary's. 243 */ 244 if (caa->cpu_role == CPU_ROLE_AP) { 245 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 246 if (phycpu_info[cpunum] != NULL) 247 panic("cpu at apic id %d already attached?", cpunum); 248 phycpu_info[cpunum] = ci; 249 } else { 250 ci = &phycpu_info_primary; 251 if (cpunum != 0) { 252 phycpu_info[0] = NULL; 253 phycpu_info[cpunum] = ci; 254 } 255 } 256 257 ci->ci_self = ci; 258 sc->sc_info = ci; 259 260 ci->ci_dev = self; 261 ci->ci_apicid = caa->cpu_number; 262 ci->ci_cpuid = ci->ci_apicid; 263 264 printf(": "); 265 switch (caa->cpu_role) { 266 case CPU_ROLE_SP: 267 printf("(uniprocessor)\n"); 268 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 269 break; 270 271 case CPU_ROLE_BP: 272 printf("(boot processor)\n"); 273 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 274 #if NIOAPIC > 0 275 ioapic_bsp_id = caa->cpu_number; 276 #endif 277 break; 278 279 case CPU_ROLE_AP: 280 /* 281 * report on an AP 282 */ 283 printf("(application processor)\n"); 284 break; 285 286 default: 287 panic("unknown processor type??\n"); 288 } 289 return; 290 #else 291 cpu_attach_common(parent, self, aux); 292 #endif 293 } 294 295 #ifdef XEN3 296 int 297 vcpu_match(parent, match, aux) 298 struct device *parent; 299 struct cfdata *match; 300 void *aux; 301 { 302 struct vcpu_attach_args *vcaa = aux; 303 304 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 305 return 1; 306 return 0; 307 } 308 309 void 310 vcpu_attach(parent, self, aux) 311 struct device *parent, *self; 312 void *aux; 313 { 314 struct vcpu_attach_args *vcaa = aux; 315 316 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 317 } 318 #endif 319 320 static void 321 cpu_vm_init(struct cpu_info *ci) 322 { 323 int ncolors = 2, i; 324 325 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 326 struct x86_cache_info *cai; 327 int tcolors; 328 329 cai = &ci->ci_cinfo[i]; 330 331 tcolors = atop(cai->cai_totalsize); 332 switch(cai->cai_associativity) { 333 case 0xff: 334 tcolors = 1; /* fully associative */ 335 break; 336 case 0: 337 case 1: 338 break; 339 default: 340 tcolors /= cai->cai_associativity; 341 } 342 ncolors = max(ncolors, tcolors); 343 } 344 345 /* 346 * Knowing the size of the largest cache on this CPU, re-color 347 * our pages. 348 */ 349 if (ncolors <= uvmexp.ncolors) 350 return; 351 printf("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors); 352 uvm_page_recolor(ncolors); 353 } 354 355 void 356 cpu_attach_common(parent, self, aux) 357 struct device *parent, *self; 358 void *aux; 359 { 360 struct cpu_softc *sc = (void *) self; 361 struct cpu_attach_args *caa = aux; 362 struct cpu_info *ci; 363 #if defined(MULTIPROCESSOR) 364 int cpunum = caa->cpu_number; 365 #endif 366 367 /* 368 * If we're an Application Processor, allocate a cpu_info 369 * structure, otherwise use the primary's. 370 */ 371 if (caa->cpu_role == CPU_ROLE_AP) { 372 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 373 #if defined(MULTIPROCESSOR) 374 if (cpu_info[cpunum] != NULL) 375 panic("cpu at apic id %d already attached?", cpunum); 376 cpu_info[cpunum] = ci; 377 #endif 378 #ifdef TRAPLOG 379 ci->ci_tlog_base = malloc(sizeof(struct tlog), 380 M_DEVBUF, M_WAITOK); 381 #endif 382 } else { 383 ci = &cpu_info_primary; 384 #if defined(MULTIPROCESSOR) 385 if (cpunum != lapic_cpu_number()) { 386 panic("%s: running CPU is at apic %d" 387 " instead of at expected %d", 388 sc->sc_dev.dv_xname, lapic_cpu_number(), cpunum); 389 } 390 #endif 391 } 392 393 ci->ci_self = ci; 394 sc->sc_info = ci; 395 396 ci->ci_dev = self; 397 ci->ci_apicid = caa->cpu_number; 398 #ifdef MULTIPROCESSOR 399 ci->ci_cpuid = ci->ci_apicid; 400 #else 401 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 402 #endif 403 ci->ci_cpumask = (1 << ci->ci_cpuid); 404 ci->ci_func = caa->cpu_func; 405 406 #ifndef __x86_64__ 407 simple_lock_init(&ci->ci_slock); 408 #endif 409 410 if (caa->cpu_role == CPU_ROLE_AP) { 411 #if defined(MULTIPROCESSOR) 412 int error; 413 414 error = mi_cpu_attach(ci); 415 if (error != 0) { 416 aprint_normal("\n"); 417 aprint_error("%s: mi_cpu_attach failed with %d\n", 418 sc->sc_dev.dv_xname, error); 419 return; 420 } 421 #endif 422 } else { 423 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 424 } 425 426 pmap_reference(pmap_kernel()); 427 ci->ci_pmap = pmap_kernel(); 428 ci->ci_tlbstate = TLBSTATE_STALE; 429 430 /* further PCB init done later. */ 431 432 printf(": "); 433 434 switch (caa->cpu_role) { 435 case CPU_ROLE_SP: 436 printf("(uniprocessor)\n"); 437 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 438 cpu_intr_init(ci); 439 identifycpu(ci); 440 cpu_init(ci); 441 cpu_set_tss_gates(ci); 442 break; 443 444 case CPU_ROLE_BP: 445 printf("apid %d (boot processor)\n", caa->cpu_number); 446 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 447 cpu_intr_init(ci); 448 identifycpu(ci); 449 cpu_init(ci); 450 cpu_set_tss_gates(ci); 451 break; 452 453 case CPU_ROLE_AP: 454 /* 455 * report on an AP 456 */ 457 printf("apid %d (application processor)\n", caa->cpu_number); 458 459 #if defined(MULTIPROCESSOR) 460 cpu_intr_init(ci); 461 gdt_alloc_cpu(ci); 462 cpu_set_tss_gates(ci); 463 cpu_start_secondary(ci); 464 if (ci->ci_flags & CPUF_PRESENT) { 465 identifycpu(ci); 466 ci->ci_next = cpu_info_list->ci_next; 467 cpu_info_list->ci_next = ci; 468 } 469 #else 470 printf("%s: not started\n", sc->sc_dev.dv_xname); 471 #endif 472 break; 473 474 default: 475 panic("unknown processor type??\n"); 476 } 477 cpu_vm_init(ci); 478 479 cpus_attached |= (1 << ci->ci_cpuid); 480 481 #if defined(MULTIPROCESSOR) 482 if (mp_verbose) { 483 struct lwp *l = ci->ci_data.cpu_idlelwp; 484 485 aprint_verbose("%s: idle lwp at %p, idle sp at 0x%x\n", 486 sc->sc_dev.dv_xname, l, l->l_addr->u_pcb.pcb_esp); 487 } 488 #endif 489 } 490 491 /* 492 * Initialize the processor appropriately. 493 */ 494 495 void 496 cpu_init(ci) 497 struct cpu_info *ci; 498 { 499 /* configure the CPU if needed */ 500 if (ci->cpu_setup != NULL) 501 (*ci->cpu_setup)(ci); 502 503 #if defined(I686_CPU) 504 /* 505 * On a P6 or above, enable global TLB caching if the 506 * hardware supports it. 507 */ 508 if (cpu_feature & CPUID_PGE) 509 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 510 511 #ifdef MTRR 512 /* 513 * On a P6 or above, initialize MTRR's if the hardware supports them. 514 */ 515 if (cpu_feature & CPUID_MTRR) { 516 if ((ci->ci_flags & CPUF_AP) == 0) 517 i686_mtrr_init_first(); 518 mtrr_init_cpu(ci); 519 } 520 #endif 521 #endif 522 #if defined(I686_CPU) 523 /* 524 * If we have FXSAVE/FXRESTOR, use them. 525 */ 526 if (cpu_feature & CPUID_FXSR) { 527 lcr4(rcr4() | CR4_OSFXSR); 528 529 /* 530 * If we have SSE/SSE2, enable XMM exceptions. 531 */ 532 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 533 lcr4(rcr4() | CR4_OSXMMEXCPT); 534 } 535 #endif /* I686_CPU */ 536 537 #ifdef MULTIPROCESSOR 538 ci->ci_flags |= CPUF_RUNNING; 539 cpus_running |= 1 << ci->ci_cpuid; 540 #endif 541 } 542 543 544 #ifdef MULTIPROCESSOR 545 void 546 cpu_boot_secondary_processors() 547 { 548 struct cpu_info *ci; 549 u_long i; 550 551 for (i=0; i < X86_MAXPROCS; i++) { 552 ci = cpu_info[i]; 553 if (ci == NULL) 554 continue; 555 if (ci->ci_data.cpu_idlelwp == NULL) 556 continue; 557 if ((ci->ci_flags & CPUF_PRESENT) == 0) 558 continue; 559 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 560 continue; 561 cpu_boot_secondary(ci); 562 } 563 } 564 565 static void 566 cpu_init_idle_lwp(struct cpu_info *ci) 567 { 568 struct lwp *l = ci->ci_data.cpu_idlelwp; 569 struct pcb *pcb = &l->l_addr->u_pcb; 570 571 pcb->pcb_cr0 = rcr0(); 572 } 573 574 void 575 cpu_init_idle_lwps() 576 { 577 struct cpu_info *ci; 578 u_long i; 579 580 for (i = 0; i < X86_MAXPROCS; i++) { 581 ci = cpu_info[i]; 582 if (ci == NULL) 583 continue; 584 if (ci->ci_data.cpu_idlelwp == NULL) 585 continue; 586 if ((ci->ci_flags & CPUF_PRESENT) == 0) 587 continue; 588 cpu_init_idle_lwp(ci); 589 } 590 } 591 592 void 593 cpu_start_secondary (ci) 594 struct cpu_info *ci; 595 { 596 int i; 597 struct pmap *kpm = pmap_kernel(); 598 extern u_int32_t mp_pdirpa; 599 600 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 601 602 ci->ci_flags |= CPUF_AP; 603 604 printf("%s: starting\n", ci->ci_dev->dv_xname); 605 606 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 607 CPU_STARTUP(ci); 608 609 /* 610 * wait for it to become ready 611 */ 612 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) { 613 delay(10); 614 } 615 if (! (ci->ci_flags & CPUF_PRESENT)) { 616 printf("%s: failed to become ready\n", ci->ci_dev->dv_xname); 617 #if defined(MPDEBUG) && defined(DDB) 618 printf("dropping into debugger; continue from here to resume boot\n"); 619 Debugger(); 620 #endif 621 } 622 623 CPU_START_CLEANUP(ci); 624 } 625 626 void 627 cpu_boot_secondary(ci) 628 struct cpu_info *ci; 629 { 630 int i; 631 632 ci->ci_flags |= CPUF_GO; /* XXX atomic */ 633 634 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) { 635 delay(10); 636 } 637 if (! (ci->ci_flags & CPUF_RUNNING)) { 638 printf("CPU failed to start\n"); 639 #if defined(MPDEBUG) && defined(DDB) 640 printf("dropping into debugger; continue from here to resume boot\n"); 641 Debugger(); 642 #endif 643 } 644 } 645 646 /* 647 * The CPU ends up here when its ready to run 648 * This is called from code in mptramp.s; at this point, we are running 649 * in the idle pcb/idle stack of the new CPU. When this function returns, 650 * this processor will enter the idle loop and start looking for work. 651 * 652 * XXX should share some of this with init386 in machdep.c 653 */ 654 void 655 cpu_hatch(void *v) 656 { 657 struct cpu_info *ci = (struct cpu_info *)v; 658 int s; 659 #ifdef __x86_64__ 660 cpu_init_msrs(ci); 661 #endif 662 663 cpu_probe_features(ci); 664 cpu_feature &= ci->ci_feature_flags; 665 /* not on Xen... */ 666 cpu_feature &= ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); 667 668 #ifdef DEBUG 669 if (ci->ci_flags & CPUF_PRESENT) 670 panic("%s: already running!?", ci->ci_dev->dv_xname); 671 #endif 672 673 ci->ci_flags |= CPUF_PRESENT; 674 675 lapic_enable(); 676 lapic_initclocks(); 677 678 while ((ci->ci_flags & CPUF_GO) == 0) 679 delay(10); 680 #ifdef DEBUG 681 if (ci->ci_flags & CPUF_RUNNING) 682 panic("%s: already running!?", ci->ci_dev->dv_xname); 683 #endif 684 685 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 686 cpu_init_idt(); 687 lapic_set_lvt(); 688 gdt_init_cpu(ci); 689 npxinit(ci); 690 691 lldt(GSEL(GLDT_SEL, SEL_KPL)); 692 693 cpu_init(ci); 694 695 s = splhigh(); 696 lapic_tpr = 0; 697 enable_intr(); 698 699 printf("%s: CPU %ld running\n",ci->ci_dev->dv_xname, ci->ci_cpuid); 700 #if defined(I586_CPU) || defined(I686_CPU) 701 if (ci->ci_feature_flags & CPUID_TSC) 702 cc_microset(ci); 703 #endif 704 splx(s); 705 } 706 707 #if defined(DDB) 708 709 #include <ddb/db_output.h> 710 #include <machine/db_machdep.h> 711 712 /* 713 * Dump CPU information from ddb. 714 */ 715 void 716 cpu_debug_dump(void) 717 { 718 struct cpu_info *ci; 719 CPU_INFO_ITERATOR cii; 720 721 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 722 for (CPU_INFO_FOREACH(cii, ci)) { 723 db_printf("%p %s %ld %x %x %10p %10p\n", 724 ci, 725 ci->ci_dev == NULL ? "BOOT" : ci->ci_dev->dv_xname, 726 ci->ci_cpuid, 727 ci->ci_flags, ci->ci_ipis, 728 ci->ci_curlwp, 729 ci->ci_fpcurlwp); 730 } 731 } 732 #endif 733 734 static void 735 cpu_copy_trampoline() 736 { 737 /* 738 * Copy boot code. 739 */ 740 extern u_char cpu_spinup_trampoline[]; 741 extern u_char cpu_spinup_trampoline_end[]; 742 pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE, /* virtual */ 743 (paddr_t)MP_TRAMPOLINE, /* physical */ 744 VM_PROT_ALL); /* protection */ 745 memcpy((void *)MP_TRAMPOLINE, 746 cpu_spinup_trampoline, 747 cpu_spinup_trampoline_end-cpu_spinup_trampoline); 748 } 749 750 #endif 751 752 753 /* XXX */ 754 #define IDTVEC(name) __CONCAT(X, name) 755 typedef void (vector)(void); 756 extern vector IDTVEC(tss_trap08); 757 #ifdef DDB 758 extern vector Xintrddbipi; 759 extern int ddb_vec; 760 #endif 761 762 static void 763 cpu_set_tss_gates(struct cpu_info *ci) 764 { 765 #if defined(DDB) && defined(MULTIPROCESSOR) 766 /* 767 * Set up separate handler for the DDB IPI, so that it doesn't 768 * stomp on a possibly corrupted stack. 769 * 770 * XXX overwriting the gate set in db_machine_init. 771 * Should rearrange the code so that it's set only once. 772 */ 773 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 774 UVM_KMF_WIRED); 775 cpu_init_tss(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 776 Xintrddbipi); 777 778 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 779 SDT_SYS386TSS, SEL_KPL, 0, 0); 780 ci->ci_gdt[GIPITSS_SEL].sd = sd; 781 782 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 783 GSEL(GIPITSS_SEL, SEL_KPL)); 784 #endif 785 } 786 787 int 788 mp_cpu_start(struct cpu_info *ci) 789 { 790 #if 0 791 #if NLAPIC > 0 792 int error; 793 #endif 794 unsigned short dwordptr[2]; 795 796 /* 797 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 798 */ 799 800 outb(IO_RTC, NVRAM_RESET); 801 outb(IO_RTC+1, NVRAM_RESET_JUMP); 802 803 /* 804 * "and the warm reset vector (DWORD based at 40:67) to point 805 * to the AP startup code ..." 806 */ 807 808 dwordptr[0] = 0; 809 dwordptr[1] = MP_TRAMPOLINE >> 4; 810 811 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 812 memcpy ((u_int8_t *) 0x467, dwordptr, 4); 813 pmap_kremove (0, PAGE_SIZE); 814 815 #if NLAPIC > 0 816 /* 817 * ... prior to executing the following sequence:" 818 */ 819 820 if (ci->ci_flags & CPUF_AP) { 821 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 822 return error; 823 824 delay(10000); 825 826 if (cpu_feature & CPUID_APIC) { 827 828 if ((error = x86_ipi(MP_TRAMPOLINE/PAGE_SIZE, 829 ci->ci_apicid, 830 LAPIC_DLMODE_STARTUP)) != 0) 831 return error; 832 delay(200); 833 834 if ((error = x86_ipi(MP_TRAMPOLINE/PAGE_SIZE, 835 ci->ci_apicid, 836 LAPIC_DLMODE_STARTUP)) != 0) 837 return error; 838 delay(200); 839 } 840 } 841 #endif 842 #endif /* 0 */ 843 return 0; 844 } 845 846 void 847 mp_cpu_start_cleanup(struct cpu_info *ci) 848 { 849 #if 0 850 /* 851 * Ensure the NVRAM reset byte contains something vaguely sane. 852 */ 853 854 outb(IO_RTC, NVRAM_RESET); 855 outb(IO_RTC+1, NVRAM_RESET_RST); 856 #endif 857 } 858 859 #ifdef __x86_64__ 860 861 void 862 cpu_init_msrs(struct cpu_info *ci) 863 { 864 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 865 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (u_int64_t) ci); 866 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 867 } 868 #endif /* __x86_64__ */ 869
Indexes created Fri Oct 03 02:09:57 GMT 2025