cpu.c revision 1.10
1 /* $NetBSD: cpu.c,v 1.10 2008/04/13 21:59:15 cegger Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Copyright (c) 1999 Stefan Grefen 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the NetBSD 56 * Foundation, Inc. and its contributors. 57 * 4. Neither the name of The NetBSD Foundation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 62 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.10 2008/04/13 21:59:15 cegger Exp $"); 76 77 #include "opt_ddb.h" 78 #include "opt_multiprocessor.h" 79 #include "opt_mpbios.h" /* for MPDEBUG */ 80 #include "opt_mtrr.h" 81 #include "opt_xen.h" 82 83 #include "lapic.h" 84 #include "ioapic.h" 85 86 #include <sys/param.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/cpu.h> 96 #include <machine/cpufunc.h> 97 #include <machine/cpuvar.h> 98 #include <machine/pmap.h> 99 #include <machine/vmparam.h> 100 #include <machine/mpbiosvar.h> 101 #include <machine/pcb.h> 102 #include <machine/specialreg.h> 103 #include <machine/segments.h> 104 #include <machine/gdt.h> 105 #include <machine/mtrr.h> 106 #include <machine/pio.h> 107 108 #ifdef XEN3 109 #include <xen/vcpuvar.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #if NIOAPIC > 0 119 #include <machine/i82093var.h> 120 #endif 121 122 #include <dev/ic/mc146818reg.h> 123 #include <dev/isa/isareg.h> 124 125 int cpu_match(device_t, cfdata_t, void *); 126 void cpu_attach(device_t, device_t, void *); 127 #ifdef XEN3 128 int vcpu_match(device_t, cfdata_t, void *); 129 void vcpu_attach(device_t, device_t, void *); 130 #endif 131 void cpu_attach_common(device_t, device_t, void *); 132 void cpu_offline_md(void); 133 134 struct cpu_softc { 135 device_t sc_dev; /* device tree glue */ 136 struct cpu_info *sc_info; /* pointer to CPU info */ 137 }; 138 139 int mp_cpu_start(struct cpu_info *, paddr_t); 140 void mp_cpu_start_cleanup(struct cpu_info *); 141 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 142 mp_cpu_start_cleanup }; 143 144 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 145 cpu_match, cpu_attach, NULL, NULL); 146 #ifdef XEN3 147 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 148 vcpu_match, vcpu_attach, NULL, NULL); 149 #endif 150 151 /* 152 * Statically-allocated CPU info for the primary CPU (or the only 153 * CPU, on uniprocessors). The CPU info list is initialized to 154 * point at it. 155 */ 156 #ifdef TRAPLOG 157 #include <machine/tlog.h> 158 struct tlog tlog_primary; 159 #endif 160 struct cpu_info cpu_info_primary = { 161 .ci_dev = 0, 162 .ci_self = &cpu_info_primary, 163 .ci_idepth = -1, 164 .ci_curlwp = &lwp0, 165 #ifdef TRAPLOG 166 .ci_tlog = &tlog_primary, 167 #endif 168 169 }; 170 struct cpu_info phycpu_info_primary = { 171 .ci_dev = 0, 172 .ci_self = &phycpu_info_primary, 173 }; 174 175 struct cpu_info *cpu_info_list = &cpu_info_primary; 176 177 static void cpu_set_tss_gates(struct cpu_info *ci); 178 179 u_int32_t cpus_attached = 0; 180 181 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 182 183 #ifdef MULTIPROCESSOR 184 /* 185 * Array of CPU info structures. Must be statically-allocated because 186 * curproc, etc. are used early. 187 */ 188 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 189 190 u_int32_t cpus_running = 0; 191 192 void cpu_hatch(void *); 193 static void cpu_boot_secondary(struct cpu_info *ci); 194 static void cpu_start_secondary(struct cpu_info *ci); 195 static void cpu_copy_trampoline(void); 196 197 /* 198 * Runs once per boot once multiprocessor goo has been detected and 199 * the local APIC on the boot processor has been mapped. 200 * 201 * Called from lapic_boot_init() (from mpbios_scan()). 202 */ 203 void 204 cpu_init_first(void) 205 { 206 int cpunum = lapic_cpu_number(); 207 208 if (cpunum != 0) { 209 cpu_info[0] = NULL; 210 cpu_info[cpunum] = &cpu_info_primary; 211 } 212 213 cpu_copy_trampoline(); 214 } 215 #endif 216 217 int 218 cpu_match(device_t parent, cfdata_t match, void *aux) 219 { 220 221 return 1; 222 } 223 224 void 225 cpu_attach(device_t parent, device_t self, void *aux) 226 { 227 #ifdef XEN3 228 struct cpu_softc *sc = device_private(self); 229 struct cpu_attach_args *caa = aux; 230 struct cpu_info *ci; 231 int cpunum = caa->cpu_number; 232 233 sc->sc_dev = self; 234 235 /* 236 * If we're an Application Processor, allocate a cpu_info 237 * structure, otherwise use the primary's. 238 */ 239 if (caa->cpu_role == CPU_ROLE_AP) { 240 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 241 if (phycpu_info[cpunum] != NULL) 242 panic("cpu at apic id %d already attached?", cpunum); 243 phycpu_info[cpunum] = ci; 244 } else { 245 ci = &phycpu_info_primary; 246 if (cpunum != 0) { 247 phycpu_info[0] = NULL; 248 phycpu_info[cpunum] = ci; 249 } 250 } 251 252 ci->ci_self = ci; 253 sc->sc_info = ci; 254 255 ci->ci_dev = self; 256 ci->ci_apicid = caa->cpu_number; 257 ci->ci_cpuid = ci->ci_apicid; 258 259 printf(": "); 260 switch (caa->cpu_role) { 261 case CPU_ROLE_SP: 262 printf("(uniprocessor)\n"); 263 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 264 break; 265 266 case CPU_ROLE_BP: 267 printf("(boot processor)\n"); 268 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 269 #if NIOAPIC > 0 270 ioapic_bsp_id = caa->cpu_number; 271 #endif 272 break; 273 274 case CPU_ROLE_AP: 275 /* 276 * report on an AP 277 */ 278 printf("(application processor)\n"); 279 break; 280 281 default: 282 panic("unknown processor type??\n"); 283 } 284 return; 285 #else 286 cpu_attach_common(parent, self, aux); 287 #endif 288 } 289 290 #ifdef XEN3 291 int 292 vcpu_match(device_t parent, cfdata_t match, void *aux) 293 { 294 struct vcpu_attach_args *vcaa = aux; 295 296 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 297 return 1; 298 return 0; 299 } 300 301 void 302 vcpu_attach(device_t parent, device_t self, void *aux) 303 { 304 struct vcpu_attach_args *vcaa = aux; 305 306 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 307 } 308 #endif 309 310 static void 311 cpu_vm_init(struct cpu_info *ci) 312 { 313 int ncolors = 2, i; 314 315 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 316 struct x86_cache_info *cai; 317 int tcolors; 318 319 cai = &ci->ci_cinfo[i]; 320 321 tcolors = atop(cai->cai_totalsize); 322 switch(cai->cai_associativity) { 323 case 0xff: 324 tcolors = 1; /* fully associative */ 325 break; 326 case 0: 327 case 1: 328 break; 329 default: 330 tcolors /= cai->cai_associativity; 331 } 332 ncolors = max(ncolors, tcolors); 333 } 334 335 /* 336 * Knowing the size of the largest cache on this CPU, re-color 337 * our pages. 338 */ 339 if (ncolors <= uvmexp.ncolors) 340 return; 341 printf("%s: %d page colors\n", device_xname(ci->ci_dev), ncolors); 342 uvm_page_recolor(ncolors); 343 } 344 345 void 346 cpu_attach_common(parent, self, aux) 347 struct device *parent, *self; 348 void *aux; 349 { 350 struct cpu_softc *sc = device_private(self); 351 struct cpu_attach_args *caa = aux; 352 struct cpu_info *ci; 353 #if defined(MULTIPROCESSOR) 354 int cpunum = caa->cpu_number; 355 #endif 356 357 sc->sc_dev = self; 358 359 /* 360 * If we're an Application Processor, allocate a cpu_info 361 * structure, otherwise use the primary's. 362 */ 363 if (caa->cpu_role == CPU_ROLE_AP) { 364 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 365 #if defined(MULTIPROCESSOR) 366 if (cpu_info[cpunum] != NULL) 367 panic("cpu at apic id %d already attached?", cpunum); 368 cpu_info[cpunum] = ci; 369 #endif 370 #ifdef TRAPLOG 371 ci->ci_tlog_base = malloc(sizeof(struct tlog), 372 M_DEVBUF, M_WAITOK); 373 #endif 374 } else { 375 ci = &cpu_info_primary; 376 #if defined(MULTIPROCESSOR) 377 if (cpunum != lapic_cpu_number()) { 378 panic("%s: running CPU is at apic %d" 379 " instead of at expected %d", 380 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 381 } 382 #endif 383 } 384 385 ci->ci_self = ci; 386 sc->sc_info = ci; 387 388 ci->ci_dev = self; 389 ci->ci_apicid = caa->cpu_number; 390 #ifdef MULTIPROCESSOR 391 ci->ci_cpuid = ci->ci_apicid; 392 #else 393 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 394 #endif 395 ci->ci_cpumask = (1 << ci->ci_cpuid); 396 ci->ci_func = caa->cpu_func; 397 398 if (caa->cpu_role == CPU_ROLE_AP) { 399 #if defined(MULTIPROCESSOR) 400 int error; 401 402 error = mi_cpu_attach(ci); 403 if (error != 0) { 404 aprint_normal("\n"); 405 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 406 error); 407 return; 408 } 409 #endif 410 } else { 411 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 412 } 413 414 pmap_reference(pmap_kernel()); 415 ci->ci_pmap = pmap_kernel(); 416 ci->ci_tlbstate = TLBSTATE_STALE; 417 418 /* further PCB init done later. */ 419 420 printf(": "); 421 422 switch (caa->cpu_role) { 423 case CPU_ROLE_SP: 424 printf("(uniprocessor)\n"); 425 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 426 cpu_intr_init(ci); 427 identifycpu(ci); 428 cpu_init(ci); 429 cpu_set_tss_gates(ci); 430 break; 431 432 case CPU_ROLE_BP: 433 printf("apid %d (boot processor)\n", caa->cpu_number); 434 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 435 cpu_intr_init(ci); 436 identifycpu(ci); 437 cpu_init(ci); 438 cpu_set_tss_gates(ci); 439 break; 440 441 case CPU_ROLE_AP: 442 /* 443 * report on an AP 444 */ 445 printf("apid %d (application processor)\n", caa->cpu_number); 446 447 #if defined(MULTIPROCESSOR) 448 cpu_intr_init(ci); 449 gdt_alloc_cpu(ci); 450 cpu_set_tss_gates(ci); 451 cpu_start_secondary(ci); 452 if (ci->ci_flags & CPUF_PRESENT) { 453 identifycpu(ci); 454 ci->ci_next = cpu_info_list->ci_next; 455 cpu_info_list->ci_next = ci; 456 } 457 #else 458 printf("%s: not started\n", device_xname(sc->sc_dev)); 459 #endif 460 break; 461 462 default: 463 panic("unknown processor type??\n"); 464 } 465 cpu_vm_init(ci); 466 467 cpus_attached |= (1 << ci->ci_cpuid); 468 469 #if defined(MULTIPROCESSOR) 470 if (mp_verbose) { 471 struct lwp *l = ci->ci_data.cpu_idlelwp; 472 473 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%x\n", 474 l, l->l_addr->u_pcb.pcb_esp); 475 } 476 #endif 477 } 478 479 /* 480 * Initialize the processor appropriately. 481 */ 482 483 void 484 cpu_init(struct cpu_info *ci) 485 { 486 /* configure the CPU if needed */ 487 if (ci->cpu_setup != NULL) 488 (*ci->cpu_setup)(ci); 489 490 /* 491 * On a P6 or above, enable global TLB caching if the 492 * hardware supports it. 493 */ 494 if (cpu_feature & CPUID_PGE) 495 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 496 497 #ifdef XXXMTRR 498 /* 499 * On a P6 or above, initialize MTRR's if the hardware supports them. 500 */ 501 if (cpu_feature & CPUID_MTRR) { 502 if ((ci->ci_flags & CPUF_AP) == 0) 503 i686_mtrr_init_first(); 504 mtrr_init_cpu(ci); 505 } 506 #endif 507 /* 508 * If we have FXSAVE/FXRESTOR, use them. 509 */ 510 if (cpu_feature & CPUID_FXSR) { 511 lcr4(rcr4() | CR4_OSFXSR); 512 513 /* 514 * If we have SSE/SSE2, enable XMM exceptions. 515 */ 516 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 517 lcr4(rcr4() | CR4_OSXMMEXCPT); 518 } 519 520 #ifdef MULTIPROCESSOR 521 ci->ci_flags |= CPUF_RUNNING; 522 cpus_running |= 1 << ci->ci_cpuid; 523 #endif 524 } 525 526 527 #ifdef MULTIPROCESSOR 528 void 529 cpu_boot_secondary_processors(void) 530 { 531 struct cpu_info *ci; 532 u_long i; 533 534 for (i=0; i < X86_MAXPROCS; i++) { 535 ci = cpu_info[i]; 536 if (ci == NULL) 537 continue; 538 if (ci->ci_data.cpu_idlelwp == NULL) 539 continue; 540 if ((ci->ci_flags & CPUF_PRESENT) == 0) 541 continue; 542 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 543 continue; 544 cpu_boot_secondary(ci); 545 } 546 } 547 548 static void 549 cpu_init_idle_lwp(struct cpu_info *ci) 550 { 551 struct lwp *l = ci->ci_data.cpu_idlelwp; 552 struct pcb *pcb = &l->l_addr->u_pcb; 553 554 pcb->pcb_cr0 = rcr0(); 555 } 556 557 void 558 cpu_init_idle_lwps(void) 559 { 560 struct cpu_info *ci; 561 u_long i; 562 563 for (i = 0; i < X86_MAXPROCS; i++) { 564 ci = cpu_info[i]; 565 if (ci == NULL) 566 continue; 567 if (ci->ci_data.cpu_idlelwp == NULL) 568 continue; 569 if ((ci->ci_flags & CPUF_PRESENT) == 0) 570 continue; 571 cpu_init_idle_lwp(ci); 572 } 573 } 574 575 void 576 cpu_start_secondary(struct cpu_info *ci) 577 { 578 int i; 579 struct pmap *kpm = pmap_kernel(); 580 extern u_int32_t mp_pdirpa; 581 582 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 583 584 ci->ci_flags |= CPUF_AP; 585 586 printf("%s: starting\n", device_xname(ci->ci_dev)); 587 588 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 589 CPU_STARTUP(ci); 590 591 /* 592 * wait for it to become ready 593 */ 594 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) { 595 delay(10); 596 } 597 if (! (ci->ci_flags & CPUF_PRESENT)) { 598 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 599 #if defined(MPDEBUG) && defined(DDB) 600 printf("dropping into debugger; continue from here to resume boot\n"); 601 Debugger(); 602 #endif 603 } 604 605 CPU_START_CLEANUP(ci); 606 } 607 608 void 609 cpu_boot_secondary(struct cpu_info *ci) 610 { 611 int i; 612 613 ci->ci_flags |= CPUF_GO; /* XXX atomic */ 614 615 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) { 616 delay(10); 617 } 618 if (! (ci->ci_flags & CPUF_RUNNING)) { 619 printf("CPU failed to start\n"); 620 #if defined(MPDEBUG) && defined(DDB) 621 printf("dropping into debugger; continue from here to resume boot\n"); 622 Debugger(); 623 #endif 624 } 625 } 626 627 /* 628 * The CPU ends up here when its ready to run 629 * This is called from code in mptramp.s; at this point, we are running 630 * in the idle pcb/idle stack of the new CPU. When this function returns, 631 * this processor will enter the idle loop and start looking for work. 632 * 633 * XXX should share some of this with init386 in machdep.c 634 */ 635 void 636 cpu_hatch(void *v) 637 { 638 struct cpu_info *ci = (struct cpu_info *)v; 639 int s; 640 #ifdef __x86_64__ 641 cpu_init_msrs(ci); 642 #endif 643 644 cpu_probe_features(ci); 645 cpu_feature &= ci->ci_feature_flags; 646 /* not on Xen... */ 647 cpu_feature &= ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); 648 649 #ifdef DEBUG 650 if (ci->ci_flags & CPUF_PRESENT) 651 panic("%s: already running!?", device_xname(ci->ci_dev)); 652 #endif 653 654 ci->ci_flags |= CPUF_PRESENT; 655 656 lapic_enable(); 657 lapic_initclocks(); 658 659 while ((ci->ci_flags & CPUF_GO) == 0) 660 delay(10); 661 #ifdef DEBUG 662 if (ci->ci_flags & CPUF_RUNNING) 663 panic("%s: already running!?", device_xname(ci->ci_dev)); 664 #endif 665 666 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 667 cpu_init_idt(); 668 lapic_set_lvt(); 669 gdt_init_cpu(ci); 670 npxinit(ci); 671 672 lldt(GSEL(GLDT_SEL, SEL_KPL)); 673 674 cpu_init(ci); 675 676 s = splhigh(); 677 lapic_tpr = 0; 678 enable_intr(); 679 680 printf("%s: CPU %ld running\n", device_xname(ci->ci_dev), ci->ci_cpuid); 681 if (ci->ci_feature_flags & CPUID_TSC) 682 cc_microset(ci); 683 splx(s); 684 } 685 686 #if defined(DDB) 687 688 #include <ddb/db_output.h> 689 #include <machine/db_machdep.h> 690 691 /* 692 * Dump CPU information from ddb. 693 */ 694 void 695 cpu_debug_dump(void) 696 { 697 struct cpu_info *ci; 698 CPU_INFO_ITERATOR cii; 699 700 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 701 for (CPU_INFO_FOREACH(cii, ci)) { 702 db_printf("%p %s %ld %x %x %10p %10p\n", 703 ci, 704 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 705 ci->ci_cpuid, 706 ci->ci_flags, ci->ci_ipis, 707 ci->ci_curlwp, 708 ci->ci_fpcurlwp); 709 } 710 } 711 #endif 712 713 static void 714 cpu_copy_trampoline(void) 715 { 716 /* 717 * Copy boot code. 718 */ 719 extern u_char cpu_spinup_trampoline[]; 720 extern u_char cpu_spinup_trampoline_end[]; 721 pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE, /* virtual */ 722 (paddr_t)MP_TRAMPOLINE, /* physical */ 723 VM_PROT_ALL); /* protection */ 724 memcpy((void *)MP_TRAMPOLINE, 725 cpu_spinup_trampoline, 726 cpu_spinup_trampoline_end-cpu_spinup_trampoline); 727 } 728 729 #endif 730 731 732 /* XXX */ 733 #define IDTVEC(name) __CONCAT(X, name) 734 typedef void (vector)(void); 735 extern vector IDTVEC(tss_trap08); 736 #ifdef DDB 737 extern vector Xintrddbipi; 738 extern int ddb_vec; 739 #endif 740 741 static void 742 cpu_set_tss_gates(struct cpu_info *ci) 743 { 744 #if defined(DDB) && defined(MULTIPROCESSOR) 745 /* 746 * Set up separate handler for the DDB IPI, so that it doesn't 747 * stomp on a possibly corrupted stack. 748 * 749 * XXX overwriting the gate set in db_machine_init. 750 * Should rearrange the code so that it's set only once. 751 */ 752 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 753 UVM_KMF_WIRED); 754 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 755 Xintrddbipi); 756 757 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 758 SDT_SYS386TSS, SEL_KPL, 0, 0); 759 ci->ci_gdt[GIPITSS_SEL].sd = sd; 760 761 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 762 GSEL(GIPITSS_SEL, SEL_KPL)); 763 #endif 764 } 765 766 int 767 mp_cpu_start(struct cpu_info *ci, paddr_t target) 768 { 769 #if 0 770 #if NLAPIC > 0 771 int error; 772 #endif 773 unsigned short dwordptr[2]; 774 775 /* 776 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 777 */ 778 779 outb(IO_RTC, NVRAM_RESET); 780 outb(IO_RTC+1, NVRAM_RESET_JUMP); 781 782 /* 783 * "and the warm reset vector (DWORD based at 40:67) to point 784 * to the AP startup code ..." 785 */ 786 787 dwordptr[0] = 0; 788 dwordptr[1] = target >> 4; 789 790 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 791 memcpy ((u_int8_t *) 0x467, dwordptr, 4); 792 pmap_kremove (0, PAGE_SIZE); 793 794 #if NLAPIC > 0 795 /* 796 * ... prior to executing the following sequence:" 797 */ 798 799 if (ci->ci_flags & CPUF_AP) { 800 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 801 return error; 802 803 delay(10000); 804 805 if (cpu_feature & CPUID_APIC) { 806 807 if ((error = x86_ipi(target/PAGE_SIZE, 808 ci->ci_apicid, 809 LAPIC_DLMODE_STARTUP)) != 0) 810 return error; 811 delay(200); 812 813 if ((error = x86_ipi(target/PAGE_SIZE, 814 ci->ci_apicid, 815 LAPIC_DLMODE_STARTUP)) != 0) 816 return error; 817 delay(200); 818 } 819 } 820 #endif 821 #endif /* 0 */ 822 return 0; 823 } 824 825 void 826 mp_cpu_start_cleanup(struct cpu_info *ci) 827 { 828 #if 0 829 /* 830 * Ensure the NVRAM reset byte contains something vaguely sane. 831 */ 832 833 outb(IO_RTC, NVRAM_RESET); 834 outb(IO_RTC+1, NVRAM_RESET_RST); 835 #endif 836 } 837 838 #ifdef __x86_64__ 839 840 void 841 cpu_init_msrs(struct cpu_info *ci, bool full) 842 { 843 if (full) { 844 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 845 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (u_int64_t) ci); 846 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 847 } 848 } 849 #endif /* __x86_64__ */ 850 851 void 852 cpu_get_tsc_freq(struct cpu_info *ci) 853 { 854 #ifdef XEN3 855 const volatile vcpu_time_info_t *tinfo = 856 &HYPERVISOR_shared_info->vcpu_info[0].time; 857 delay(1000000); 858 uint64_t freq = 1000000000ULL << 32; 859 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 860 if ( tinfo->tsc_shift < 0 ) 861 freq = freq << -tinfo->tsc_shift; 862 else 863 freq = freq >> tinfo->tsc_shift; 864 ci->ci_tsc_freq = freq; 865 #else 866 /* XXX this needs to read the shared_info of the CPU being probed.. */ 867 ci->ci_tsc_freq = HYPERVISOR_shared_info->cpu_freq; 868 #endif /* XEN3 */ 869 } 870 871 void 872 cpu_offline_md(void) 873 { 874 int s; 875 876 s = splhigh(); 877 #ifdef __i386__ 878 npxsave_cpu(true); 879 #else 880 fpusave_cpu(true); 881 #endif 882 splx(s); 883 } 884
Indexes created Mon Sep 22 13:09:51 GMT 2025