cpu.c revision 1.11
1 /* $NetBSD: cpu.c,v 1.11 2008/04/13 22:29:38 cegger Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Copyright (c) 1999 Stefan Grefen 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the NetBSD 56 * Foundation, Inc. and its contributors. 57 * 4. Neither the name of The NetBSD Foundation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 62 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.11 2008/04/13 22:29:38 cegger Exp $"); 76 77 #include "opt_ddb.h" 78 #include "opt_multiprocessor.h" 79 #include "opt_mpbios.h" /* for MPDEBUG */ 80 #include "opt_mtrr.h" 81 #include "opt_xen.h" 82 83 #include "lapic.h" 84 #include "ioapic.h" 85 86 #include <sys/param.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 #include <sys/cpu.h> 93 #include <sys/atomic.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #include <machine/cpufunc.h> 98 #include <machine/cpuvar.h> 99 #include <machine/pmap.h> 100 #include <machine/vmparam.h> 101 #include <machine/mpbiosvar.h> 102 #include <machine/pcb.h> 103 #include <machine/specialreg.h> 104 #include <machine/segments.h> 105 #include <machine/gdt.h> 106 #include <machine/mtrr.h> 107 #include <machine/pio.h> 108 109 #ifdef XEN3 110 #include <xen/vcpuvar.h> 111 #endif 112 113 #if NLAPIC > 0 114 #include <machine/apicvar.h> 115 #include <machine/i82489reg.h> 116 #include <machine/i82489var.h> 117 #endif 118 119 #if NIOAPIC > 0 120 #include <machine/i82093var.h> 121 #endif 122 123 #include <dev/ic/mc146818reg.h> 124 #include <dev/isa/isareg.h> 125 126 int cpu_match(device_t, cfdata_t, void *); 127 void cpu_attach(device_t, device_t, void *); 128 #ifdef XEN3 129 int vcpu_match(device_t, cfdata_t, void *); 130 void vcpu_attach(device_t, device_t, void *); 131 #endif 132 void cpu_attach_common(device_t, device_t, void *); 133 void cpu_offline_md(void); 134 135 struct cpu_softc { 136 device_t sc_dev; /* device tree glue */ 137 struct cpu_info *sc_info; /* pointer to CPU info */ 138 }; 139 140 int mp_cpu_start(struct cpu_info *, paddr_t); 141 void mp_cpu_start_cleanup(struct cpu_info *); 142 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 143 mp_cpu_start_cleanup }; 144 145 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 146 cpu_match, cpu_attach, NULL, NULL); 147 #ifdef XEN3 148 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 149 vcpu_match, vcpu_attach, NULL, NULL); 150 #endif 151 152 /* 153 * Statically-allocated CPU info for the primary CPU (or the only 154 * CPU, on uniprocessors). The CPU info list is initialized to 155 * point at it. 156 */ 157 #ifdef TRAPLOG 158 #include <machine/tlog.h> 159 struct tlog tlog_primary; 160 #endif 161 struct cpu_info cpu_info_primary = { 162 .ci_dev = 0, 163 .ci_self = &cpu_info_primary, 164 .ci_idepth = -1, 165 .ci_curlwp = &lwp0, 166 #ifdef TRAPLOG 167 .ci_tlog = &tlog_primary, 168 #endif 169 170 }; 171 struct cpu_info phycpu_info_primary = { 172 .ci_dev = 0, 173 .ci_self = &phycpu_info_primary, 174 }; 175 176 struct cpu_info *cpu_info_list = &cpu_info_primary; 177 178 static void cpu_set_tss_gates(struct cpu_info *ci); 179 180 uint32_t cpus_attached = 0; 181 uint32_t cpus_running = 0; 182 183 bool x86_mp_online; 184 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 185 186 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 187 188 #ifdef MULTIPROCESSOR 189 /* 190 * Array of CPU info structures. Must be statically-allocated because 191 * curproc, etc. are used early. 192 */ 193 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 194 195 void cpu_hatch(void *); 196 static void cpu_boot_secondary(struct cpu_info *ci); 197 static void cpu_start_secondary(struct cpu_info *ci); 198 static void cpu_copy_trampoline(void); 199 200 /* 201 * Runs once per boot once multiprocessor goo has been detected and 202 * the local APIC on the boot processor has been mapped. 203 * 204 * Called from lapic_boot_init() (from mpbios_scan()). 205 */ 206 void 207 cpu_init_first(void) 208 { 209 int cpunum = lapic_cpu_number(); 210 211 if (cpunum != 0) { 212 cpu_info[0] = NULL; 213 cpu_info[cpunum] = &cpu_info_primary; 214 } 215 216 cpu_copy_trampoline(); 217 } 218 #endif 219 220 int 221 cpu_match(device_t parent, cfdata_t match, void *aux) 222 { 223 224 return 1; 225 } 226 227 void 228 cpu_attach(device_t parent, device_t self, void *aux) 229 { 230 #ifdef XEN3 231 struct cpu_softc *sc = device_private(self); 232 struct cpu_attach_args *caa = aux; 233 struct cpu_info *ci; 234 int cpunum = caa->cpu_number; 235 236 sc->sc_dev = self; 237 238 /* 239 * If we're an Application Processor, allocate a cpu_info 240 * structure, otherwise use the primary's. 241 */ 242 if (caa->cpu_role == CPU_ROLE_AP) { 243 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 244 if (phycpu_info[cpunum] != NULL) 245 panic("cpu at apic id %d already attached?", cpunum); 246 phycpu_info[cpunum] = ci; 247 } else { 248 ci = &phycpu_info_primary; 249 if (cpunum != 0) { 250 phycpu_info[0] = NULL; 251 phycpu_info[cpunum] = ci; 252 } 253 } 254 255 ci->ci_self = ci; 256 sc->sc_info = ci; 257 258 ci->ci_dev = self; 259 ci->ci_apicid = caa->cpu_number; 260 ci->ci_cpuid = ci->ci_apicid; 261 262 printf(": "); 263 switch (caa->cpu_role) { 264 case CPU_ROLE_SP: 265 printf("(uniprocessor)\n"); 266 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 267 break; 268 269 case CPU_ROLE_BP: 270 printf("(boot processor)\n"); 271 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 272 #if NIOAPIC > 0 273 ioapic_bsp_id = caa->cpu_number; 274 #endif 275 break; 276 277 case CPU_ROLE_AP: 278 /* 279 * report on an AP 280 */ 281 printf("(application processor)\n"); 282 break; 283 284 default: 285 panic("unknown processor type??\n"); 286 } 287 return; 288 #else 289 cpu_attach_common(parent, self, aux); 290 #endif 291 } 292 293 #ifdef XEN3 294 int 295 vcpu_match(device_t parent, cfdata_t match, void *aux) 296 { 297 struct vcpu_attach_args *vcaa = aux; 298 299 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 300 return 1; 301 return 0; 302 } 303 304 void 305 vcpu_attach(device_t parent, device_t self, void *aux) 306 { 307 struct vcpu_attach_args *vcaa = aux; 308 309 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 310 } 311 #endif 312 313 static void 314 cpu_vm_init(struct cpu_info *ci) 315 { 316 int ncolors = 2, i; 317 318 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 319 struct x86_cache_info *cai; 320 int tcolors; 321 322 cai = &ci->ci_cinfo[i]; 323 324 tcolors = atop(cai->cai_totalsize); 325 switch(cai->cai_associativity) { 326 case 0xff: 327 tcolors = 1; /* fully associative */ 328 break; 329 case 0: 330 case 1: 331 break; 332 default: 333 tcolors /= cai->cai_associativity; 334 } 335 ncolors = max(ncolors, tcolors); 336 } 337 338 /* 339 * Knowing the size of the largest cache on this CPU, re-color 340 * our pages. 341 */ 342 if (ncolors <= uvmexp.ncolors) 343 return; 344 printf("%s: %d page colors\n", device_xname(ci->ci_dev), ncolors); 345 uvm_page_recolor(ncolors); 346 } 347 348 void 349 cpu_attach_common(device_t parent, device_t self, void *aux) 350 { 351 struct cpu_softc *sc = device_private(self); 352 struct cpu_attach_args *caa = aux; 353 struct cpu_info *ci; 354 #if defined(MULTIPROCESSOR) 355 int cpunum = caa->cpu_number; 356 #endif 357 358 sc->sc_dev = self; 359 360 /* 361 * If we're an Application Processor, allocate a cpu_info 362 * structure, otherwise use the primary's. 363 */ 364 if (caa->cpu_role == CPU_ROLE_AP) { 365 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 366 #if defined(MULTIPROCESSOR) 367 if (cpu_info[cpunum] != NULL) 368 panic("cpu at apic id %d already attached?", cpunum); 369 cpu_info[cpunum] = ci; 370 #endif 371 #ifdef TRAPLOG 372 ci->ci_tlog_base = malloc(sizeof(struct tlog), 373 M_DEVBUF, M_WAITOK); 374 #endif 375 } else { 376 ci = &cpu_info_primary; 377 #if defined(MULTIPROCESSOR) 378 if (cpunum != lapic_cpu_number()) { 379 panic("%s: running CPU is at apic %d" 380 " instead of at expected %d", 381 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 382 } 383 #endif 384 } 385 386 ci->ci_self = ci; 387 sc->sc_info = ci; 388 389 ci->ci_dev = self; 390 ci->ci_apicid = caa->cpu_number; 391 #ifdef MULTIPROCESSOR 392 ci->ci_cpuid = ci->ci_apicid; 393 #else 394 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 395 #endif 396 ci->ci_cpumask = (1 << ci->ci_cpuid); 397 ci->ci_func = caa->cpu_func; 398 399 if (caa->cpu_role == CPU_ROLE_AP) { 400 #if defined(MULTIPROCESSOR) 401 int error; 402 403 error = mi_cpu_attach(ci); 404 if (error != 0) { 405 aprint_normal("\n"); 406 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 407 error); 408 return; 409 } 410 #endif 411 } else { 412 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 413 } 414 415 pmap_reference(pmap_kernel()); 416 ci->ci_pmap = pmap_kernel(); 417 ci->ci_tlbstate = TLBSTATE_STALE; 418 419 /* further PCB init done later. */ 420 421 printf(": "); 422 423 switch (caa->cpu_role) { 424 case CPU_ROLE_SP: 425 printf("(uniprocessor)\n"); 426 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 427 cpu_intr_init(ci); 428 identifycpu(ci); 429 cpu_init(ci); 430 cpu_set_tss_gates(ci); 431 break; 432 433 case CPU_ROLE_BP: 434 printf("apid %d (boot processor)\n", caa->cpu_number); 435 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 436 cpu_intr_init(ci); 437 identifycpu(ci); 438 cpu_init(ci); 439 cpu_set_tss_gates(ci); 440 break; 441 442 case CPU_ROLE_AP: 443 /* 444 * report on an AP 445 */ 446 printf("apid %d (application processor)\n", caa->cpu_number); 447 448 #if defined(MULTIPROCESSOR) 449 cpu_intr_init(ci); 450 gdt_alloc_cpu(ci); 451 cpu_set_tss_gates(ci); 452 cpu_start_secondary(ci); 453 if (ci->ci_flags & CPUF_PRESENT) { 454 identifycpu(ci); 455 ci->ci_next = cpu_info_list->ci_next; 456 cpu_info_list->ci_next = ci; 457 } 458 #else 459 printf("%s: not started\n", device_xname(sc->sc_dev)); 460 #endif 461 break; 462 463 default: 464 panic("unknown processor type??\n"); 465 } 466 cpu_vm_init(ci); 467 468 cpus_attached |= (1 << ci->ci_cpuid); 469 470 #if defined(MULTIPROCESSOR) 471 if (mp_verbose) { 472 struct lwp *l = ci->ci_data.cpu_idlelwp; 473 474 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%x\n", 475 l, l->l_addr->u_pcb.pcb_esp); 476 } 477 #endif 478 } 479 480 /* 481 * Initialize the processor appropriately. 482 */ 483 484 void 485 cpu_init(struct cpu_info *ci) 486 { 487 /* configure the CPU if needed */ 488 if (ci->cpu_setup != NULL) 489 (*ci->cpu_setup)(ci); 490 491 /* 492 * On a P6 or above, enable global TLB caching if the 493 * hardware supports it. 494 */ 495 if (cpu_feature & CPUID_PGE) 496 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 497 498 #ifdef XXXMTRR 499 /* 500 * On a P6 or above, initialize MTRR's if the hardware supports them. 501 */ 502 if (cpu_feature & CPUID_MTRR) { 503 if ((ci->ci_flags & CPUF_AP) == 0) 504 i686_mtrr_init_first(); 505 mtrr_init_cpu(ci); 506 } 507 #endif 508 /* 509 * If we have FXSAVE/FXRESTOR, use them. 510 */ 511 if (cpu_feature & CPUID_FXSR) { 512 lcr4(rcr4() | CR4_OSFXSR); 513 514 /* 515 * If we have SSE/SSE2, enable XMM exceptions. 516 */ 517 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 518 lcr4(rcr4() | CR4_OSXMMEXCPT); 519 } 520 521 #ifdef MULTIPROCESSOR 522 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 523 atomic_or_32(&cpus_running, ci->ci_cpumask); 524 #endif 525 } 526 527 528 #ifdef MULTIPROCESSOR 529 void 530 cpu_boot_secondary_processors(void) 531 { 532 struct cpu_info *ci; 533 u_long i; 534 535 for (i = 0; i < X86_MAXPROCS; i++) { 536 ci = cpu_info[i]; 537 if (ci == NULL) 538 continue; 539 if (ci->ci_data.cpu_idlelwp == NULL) 540 continue; 541 if ((ci->ci_flags & CPUF_PRESENT) == 0) 542 continue; 543 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 544 continue; 545 cpu_boot_secondary(ci); 546 } 547 548 x86_mp_online = true; 549 } 550 551 static void 552 cpu_init_idle_lwp(struct cpu_info *ci) 553 { 554 struct lwp *l = ci->ci_data.cpu_idlelwp; 555 struct pcb *pcb = &l->l_addr->u_pcb; 556 557 pcb->pcb_cr0 = rcr0(); 558 } 559 560 void 561 cpu_init_idle_lwps(void) 562 { 563 struct cpu_info *ci; 564 u_long i; 565 566 for (i = 0; i < X86_MAXPROCS; i++) { 567 ci = cpu_info[i]; 568 if (ci == NULL) 569 continue; 570 if (ci->ci_data.cpu_idlelwp == NULL) 571 continue; 572 if ((ci->ci_flags & CPUF_PRESENT) == 0) 573 continue; 574 cpu_init_idle_lwp(ci); 575 } 576 } 577 578 void 579 cpu_start_secondary(struct cpu_info *ci) 580 { 581 int i; 582 struct pmap *kpm = pmap_kernel(); 583 extern uint32_t mp_pdirpa; 584 585 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 586 587 atomic_or_32(&ci->ci_flags, CPUF_AP); 588 589 aprint_debug_dev(ci->ci_dev, "starting\n"); 590 591 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 592 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 593 return; 594 595 /* 596 * wait for it to become ready 597 */ 598 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 599 #ifdef MPDEBUG 600 extern int cpu_trace[3]; 601 static int otrace[3]; 602 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 603 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 604 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 605 memcpy(otrace, cpu_trace, sizeof(otrace)); 606 } 607 #endif 608 delay(10); 609 } 610 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 611 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 612 #if defined(MPDEBUG) && defined(DDB) 613 printf("dropping into debugger; continue from here to resume boot\n"); 614 Debugger(); 615 #endif 616 } 617 618 CPU_START_CLEANUP(ci); 619 } 620 621 void 622 cpu_boot_secondary(struct cpu_info *ci) 623 { 624 int i; 625 626 atomic_or_32(&ci->ci_flags, CPUF_GO); 627 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 628 delay(10); 629 } 630 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 631 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 632 #if defined(MPDEBUG) && defined(DDB) 633 printf("dropping into debugger; continue from here to resume boot\n"); 634 Debugger(); 635 #endif 636 } 637 } 638 639 /* 640 * The CPU ends up here when its ready to run 641 * This is called from code in mptramp.s; at this point, we are running 642 * in the idle pcb/idle stack of the new CPU. When this function returns, 643 * this processor will enter the idle loop and start looking for work. 644 * 645 * XXX should share some of this with init386 in machdep.c 646 */ 647 void 648 cpu_hatch(void *v) 649 { 650 struct cpu_info *ci = (struct cpu_info *)v; 651 int s, i; 652 uint32_t blacklist_features; 653 654 #ifdef __x86_64__ 655 cpu_init_msrs(ci, true); 656 #endif 657 658 cpu_probe_features(ci); 659 cpu_feature &= ci->ci_feature_flags; 660 cpu_feature2 &= ci->ci_feature2_flags; 661 662 /* not on Xen... */ 663 blacklist_features = ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); /* XXX add CPUID_SVM */ 664 665 cpu_feature &= blacklist_features; 666 667 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 668 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 669 while ((ci->ci_flags & CPUF_GO) == 0) { 670 /* Don't use delay, boot CPU may be patching the text. */ 671 for (i = 10000; i != 0; i--) 672 x86_pause(); 673 } 674 675 /* Because the text may have been patched in x86_patch(). */ 676 wbinvd(); 677 x86_flush(); 678 679 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 680 681 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 682 cpu_init_idt(); 683 gdt_init_cpu(ci); 684 lapic_enable(); 685 lapic_set_lvt(); 686 lapic_initclocks(); 687 688 npxinit(ci); 689 690 lldt(GSEL(GLDT_SEL, SEL_KPL)); 691 /* ltr(ci->ci_tss_sel); */ /* XXX */ 692 693 cpu_init(ci); 694 cpu_get_tsc_freq(ci); 695 696 s = splhigh(); 697 #ifdef i386 698 lapic_tpr = 0; 699 #else 700 lcr8(0); 701 #endif 702 x86_enable_intr(); 703 splx(s); 704 #ifdef DOM0OPS 705 x86_errata(); 706 #endif 707 708 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 709 (long)ci->ci_cpuid); 710 } 711 712 #if defined(DDB) 713 714 #include <ddb/db_output.h> 715 #include <machine/db_machdep.h> 716 717 /* 718 * Dump CPU information from ddb. 719 */ 720 void 721 cpu_debug_dump(void) 722 { 723 struct cpu_info *ci; 724 CPU_INFO_ITERATOR cii; 725 726 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 727 for (CPU_INFO_FOREACH(cii, ci)) { 728 db_printf("%p %s %ld %x %x %10p %10p\n", 729 ci, 730 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 731 ci->ci_cpuid, 732 ci->ci_flags, ci->ci_ipis, 733 ci->ci_curlwp, 734 ci->ci_fpcurlwp); 735 } 736 } 737 #endif 738 739 static void 740 cpu_copy_trampoline(void) 741 { 742 /* 743 * Copy boot code. 744 */ 745 extern u_char cpu_spinup_trampoline[]; 746 extern u_char cpu_spinup_trampoline_end[]; 747 748 vaddr_t mp_trampoline_vaddr; 749 750 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 751 UVM_KMF_VAONLY); 752 753 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 754 VM_PROT_READ | VM_PROT_WRITE); 755 pmap_update(pmap_kernel()); 756 memcpy((void *)mp_trampoline_vaddr, 757 cpu_spinup_trampoline, 758 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 759 760 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 761 pmap_update(pmap_kernel()); 762 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 763 } 764 765 #endif 766 767 #ifdef i386 768 #if 0 769 static void 770 tss_init(struct i386tss *tss, void *stack, void *func) 771 { 772 memset(tss, 0, sizeof *tss); 773 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 774 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 775 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 776 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 777 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 778 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 779 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 780 tss->tss_esp = (int)((char *)stack + USPACE - 16); 781 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 782 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 783 tss->__tss_eip = (int)func; 784 } 785 #endif 786 787 /* XXX */ 788 #define IDTVEC(name) __CONCAT(X, name) 789 typedef void (vector)(void); 790 extern vector IDTVEC(tss_trap08); 791 #ifdef DDB 792 extern vector Xintrddbipi; 793 extern int ddb_vec; 794 #endif 795 796 static void 797 cpu_set_tss_gates(struct cpu_info *ci) 798 { 799 #if 0 800 struct segment_descriptor sd; 801 802 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 803 UVM_KMF_WIRED); 804 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 805 IDTVEC(tss_trap08)); 806 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 807 SDT_SYS386TSS, SEL_KPL, 0, 0); 808 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 809 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 810 GSEL(GTRAPTSS_SEL, SEL_KPL)); 811 #endif 812 813 #if defined(DDB) && defined(MULTIPROCESSOR) 814 /* 815 * Set up separate handler for the DDB IPI, so that it doesn't 816 * stomp on a possibly corrupted stack. 817 * 818 * XXX overwriting the gate set in db_machine_init. 819 * Should rearrange the code so that it's set only once. 820 */ 821 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 822 UVM_KMF_WIRED); 823 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 824 Xintrddbipi); 825 826 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 827 SDT_SYS386TSS, SEL_KPL, 0, 0); 828 ci->ci_gdt[GIPITSS_SEL].sd = sd; 829 830 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 831 GSEL(GIPITSS_SEL, SEL_KPL)); 832 #endif 833 } 834 #else 835 static void 836 cpu_set_tss_gates(struct cpu_info *ci) 837 { 838 839 } 840 #endif /* i386 */ 841 842 int 843 mp_cpu_start(struct cpu_info *ci, paddr_t target) 844 { 845 #if 0 846 #if NLAPIC > 0 847 int error; 848 #endif 849 unsigned short dwordptr[2]; 850 851 /* 852 * Bootstrap code must be addressable in real mode 853 * and it must be page aligned. 854 */ 855 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 856 857 /* 858 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 859 */ 860 861 outb(IO_RTC, NVRAM_RESET); 862 outb(IO_RTC+1, NVRAM_RESET_JUMP); 863 864 /* 865 * "and the warm reset vector (DWORD based at 40:67) to point 866 * to the AP startup code ..." 867 */ 868 869 dwordptr[0] = 0; 870 dwordptr[1] = target >> 4; 871 872 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 873 memcpy ((uint8_t *) 0x467, dwordptr, 4); 874 pmap_kremove (0, PAGE_SIZE); 875 876 #if NLAPIC > 0 877 /* 878 * ... prior to executing the following sequence:" 879 */ 880 881 if (ci->ci_flags & CPUF_AP) { 882 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 883 return error; 884 885 delay(10000); 886 887 if (cpu_feature & CPUID_APIC) { 888 error = x86_ipi_init(ci->ci_apicid); 889 if (error != 0) { 890 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 891 __func__); 892 return error; 893 } 894 895 delay(10000); 896 897 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 898 LAPIC_DLMODE_STARTUP); 899 if (error != 0) { 900 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 901 __func__); 902 return error; 903 } 904 delay(200); 905 906 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 907 LAPIC_DLMODE_STARTUP); 908 if (error != 0) { 909 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 910 __func__); 911 return error; 912 } 913 delay(200); 914 } 915 } 916 #endif 917 #endif /* 0 */ 918 return 0; 919 } 920 921 void 922 mp_cpu_start_cleanup(struct cpu_info *ci) 923 { 924 #if 0 925 /* 926 * Ensure the NVRAM reset byte contains something vaguely sane. 927 */ 928 929 outb(IO_RTC, NVRAM_RESET); 930 outb(IO_RTC+1, NVRAM_RESET_RST); 931 #endif 932 } 933 934 #ifdef __x86_64__ 935 936 void 937 cpu_init_msrs(struct cpu_info *ci, bool full) 938 { 939 if (full) { 940 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 941 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 942 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 943 } 944 } 945 #endif /* __x86_64__ */ 946 947 void 948 cpu_offline_md(void) 949 { 950 int s; 951 952 s = splhigh(); 953 #ifdef __i386__ 954 npxsave_cpu(true); 955 #else 956 fpusave_cpu(true); 957 #endif 958 splx(s); 959 } 960 961 #if 0 962 /* XXX joerg restructure and restart CPUs individually */ 963 static bool 964 cpu_suspend(device_t dv PMF_FN_ARGS) 965 { 966 struct cpu_softc *sc = device_private(dv); 967 struct cpu_info *ci = sc->sc_info; 968 int err; 969 970 if (ci->ci_flags & CPUF_PRIMARY) 971 return true; 972 if (ci->ci_data.cpu_idlelwp == NULL) 973 return true; 974 if ((ci->ci_flags & CPUF_PRESENT) == 0) 975 return true; 976 977 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 978 979 if (sc->sc_wasonline) { 980 mutex_enter(&cpu_lock); 981 err = cpu_setonline(ci, false); 982 mutex_exit(&cpu_lock); 983 984 if (err) 985 return false; 986 } 987 988 return true; 989 } 990 991 static bool 992 cpu_resume(device_t dv PMF_FN_ARGS) 993 { 994 struct cpu_softc *sc = device_private(dv); 995 struct cpu_info *ci = sc->sc_info; 996 int err = 0; 997 998 if (ci->ci_flags & CPUF_PRIMARY) 999 return true; 1000 if (ci->ci_data.cpu_idlelwp == NULL) 1001 return true; 1002 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1003 return true; 1004 1005 if (sc->sc_wasonline) { 1006 mutex_enter(&cpu_lock); 1007 err = cpu_setonline(ci, true); 1008 mutex_exit(&cpu_lock); 1009 } 1010 1011 return err == 0; 1012 } 1013 #endif 1014 1015 void 1016 cpu_get_tsc_freq(struct cpu_info *ci) 1017 { 1018 #ifdef XEN3 1019 const volatile vcpu_time_info_t *tinfo = 1020 &HYPERVISOR_shared_info->vcpu_info[0].time; 1021 delay(1000000); 1022 uint64_t freq = 1000000000ULL << 32; 1023 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1024 if ( tinfo->tsc_shift < 0 ) 1025 freq = freq << -tinfo->tsc_shift; 1026 else 1027 freq = freq >> tinfo->tsc_shift; 1028 ci->ci_tsc_freq = freq; 1029 #else 1030 /* XXX this needs to read the shared_info of the CPU being probed.. */ 1031 ci->ci_tsc_freq = HYPERVISOR_shared_info->cpu_freq; 1032 #endif /* XEN3 */ 1033 } 1034
Indexes created Wed Sep 24 05:09:52 GMT 2025