cpu.c revision 1.15
1 /* $NetBSD: cpu.c,v 1.15 2008/04/18 15:32:46 cegger Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Copyright (c) 1999 Stefan Grefen 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the NetBSD 56 * Foundation, Inc. and its contributors. 57 * 4. Neither the name of The NetBSD Foundation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 62 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.15 2008/04/18 15:32:46 cegger Exp $"); 76 77 #include "opt_ddb.h" 78 #include "opt_multiprocessor.h" 79 #include "opt_mpbios.h" /* for MPDEBUG */ 80 #include "opt_mtrr.h" 81 #include "opt_xen.h" 82 83 #include "lapic.h" 84 #include "ioapic.h" 85 86 #include <sys/param.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 #include <sys/cpu.h> 93 #include <sys/atomic.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #include <machine/cpufunc.h> 98 #include <machine/cpuvar.h> 99 #include <machine/pmap.h> 100 #include <machine/vmparam.h> 101 #include <machine/mpbiosvar.h> 102 #include <machine/pcb.h> 103 #include <machine/specialreg.h> 104 #include <machine/segments.h> 105 #include <machine/gdt.h> 106 #include <machine/mtrr.h> 107 #include <machine/pio.h> 108 109 #ifdef XEN3 110 #include <xen/vcpuvar.h> 111 #endif 112 113 #if NLAPIC > 0 114 #include <machine/apicvar.h> 115 #include <machine/i82489reg.h> 116 #include <machine/i82489var.h> 117 #endif 118 119 #include <dev/ic/mc146818reg.h> 120 #include <dev/isa/isareg.h> 121 122 int cpu_match(device_t, cfdata_t, void *); 123 void cpu_attach(device_t, device_t, void *); 124 #ifdef XEN3 125 int vcpu_match(device_t, cfdata_t, void *); 126 void vcpu_attach(device_t, device_t, void *); 127 #endif 128 void cpu_attach_common(device_t, device_t, void *); 129 void cpu_offline_md(void); 130 131 struct cpu_softc { 132 device_t sc_dev; /* device tree glue */ 133 struct cpu_info *sc_info; /* pointer to CPU info */ 134 }; 135 136 int mp_cpu_start(struct cpu_info *, paddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL); 143 #ifdef XEN3 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 #endif 147 148 /* 149 * Statically-allocated CPU info for the primary CPU (or the only 150 * CPU, on uniprocessors). The CPU info list is initialized to 151 * point at it. 152 */ 153 #ifdef TRAPLOG 154 #include <machine/tlog.h> 155 struct tlog tlog_primary; 156 #endif 157 struct cpu_info cpu_info_primary = { 158 .ci_dev = 0, 159 .ci_self = &cpu_info_primary, 160 .ci_idepth = -1, 161 .ci_curlwp = &lwp0, 162 #ifdef TRAPLOG 163 .ci_tlog = &tlog_primary, 164 #endif 165 166 }; 167 struct cpu_info phycpu_info_primary = { 168 .ci_dev = 0, 169 .ci_self = &phycpu_info_primary, 170 }; 171 172 struct cpu_info *cpu_info_list = &cpu_info_primary; 173 174 static void cpu_set_tss_gates(struct cpu_info *ci); 175 176 uint32_t cpus_attached = 0; 177 uint32_t cpus_running = 0; 178 179 bool x86_mp_online; 180 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 181 182 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 183 184 #ifdef MULTIPROCESSOR 185 /* 186 * Array of CPU info structures. Must be statically-allocated because 187 * curproc, etc. are used early. 188 */ 189 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 190 191 void cpu_hatch(void *); 192 static void cpu_boot_secondary(struct cpu_info *ci); 193 static void cpu_start_secondary(struct cpu_info *ci); 194 static void cpu_copy_trampoline(void); 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 void 203 cpu_init_first(void) 204 { 205 int cpunum = lapic_cpu_number(); 206 207 if (cpunum != 0) { 208 cpu_info[0] = NULL; 209 cpu_info[cpunum] = &cpu_info_primary; 210 } 211 212 cpu_copy_trampoline(); 213 } 214 #endif 215 216 int 217 cpu_match(device_t parent, cfdata_t match, void *aux) 218 { 219 220 return 1; 221 } 222 223 void 224 cpu_attach(device_t parent, device_t self, void *aux) 225 { 226 #ifdef XEN3 227 struct cpu_softc *sc = device_private(self); 228 struct cpu_attach_args *caa = aux; 229 struct cpu_info *ci; 230 int cpunum = caa->cpu_number; 231 232 sc->sc_dev = self; 233 234 /* 235 * If we're an Application Processor, allocate a cpu_info 236 * structure, otherwise use the primary's. 237 */ 238 if (caa->cpu_role == CPU_ROLE_AP) { 239 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 240 if (phycpu_info[cpunum] != NULL) 241 panic("cpu at apic id %d already attached?", cpunum); 242 phycpu_info[cpunum] = ci; 243 } else { 244 ci = &phycpu_info_primary; 245 if (cpunum != 0) { 246 phycpu_info[0] = NULL; 247 phycpu_info[cpunum] = ci; 248 } 249 } 250 251 ci->ci_self = ci; 252 sc->sc_info = ci; 253 254 ci->ci_dev = self; 255 ci->ci_apicid = caa->cpu_number; 256 ci->ci_cpuid = ci->ci_apicid; 257 258 printf(": "); 259 switch (caa->cpu_role) { 260 case CPU_ROLE_SP: 261 printf("(uniprocessor)\n"); 262 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 263 break; 264 265 case CPU_ROLE_BP: 266 printf("(boot processor)\n"); 267 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 268 break; 269 270 case CPU_ROLE_AP: 271 /* 272 * report on an AP 273 */ 274 printf("(application processor)\n"); 275 break; 276 277 default: 278 panic("unknown processor type??\n"); 279 } 280 return; 281 #else 282 cpu_attach_common(parent, self, aux); 283 #endif 284 } 285 286 #ifdef XEN3 287 int 288 vcpu_match(device_t parent, cfdata_t match, void *aux) 289 { 290 struct vcpu_attach_args *vcaa = aux; 291 292 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 293 return 1; 294 return 0; 295 } 296 297 void 298 vcpu_attach(device_t parent, device_t self, void *aux) 299 { 300 struct vcpu_attach_args *vcaa = aux; 301 302 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 303 } 304 #endif 305 306 static void 307 cpu_vm_init(struct cpu_info *ci) 308 { 309 int ncolors = 2, i; 310 311 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 312 struct x86_cache_info *cai; 313 int tcolors; 314 315 cai = &ci->ci_cinfo[i]; 316 317 tcolors = atop(cai->cai_totalsize); 318 switch(cai->cai_associativity) { 319 case 0xff: 320 tcolors = 1; /* fully associative */ 321 break; 322 case 0: 323 case 1: 324 break; 325 default: 326 tcolors /= cai->cai_associativity; 327 } 328 ncolors = max(ncolors, tcolors); 329 } 330 331 /* 332 * Knowing the size of the largest cache on this CPU, re-color 333 * our pages. 334 */ 335 if (ncolors <= uvmexp.ncolors) 336 return; 337 printf("%s: %d page colors\n", device_xname(ci->ci_dev), ncolors); 338 uvm_page_recolor(ncolors); 339 } 340 341 void 342 cpu_attach_common(device_t parent, device_t self, void *aux) 343 { 344 struct cpu_softc *sc = device_private(self); 345 struct cpu_attach_args *caa = aux; 346 struct cpu_info *ci; 347 uintptr_t ptr; 348 #if defined(MULTIPROCESSOR) 349 int cpunum = caa->cpu_number; 350 #endif 351 352 sc->sc_dev = self; 353 354 /* 355 * If we're an Application Processor, allocate a cpu_info 356 * structure, otherwise use the primary's. 357 */ 358 if (caa->cpu_role == CPU_ROLE_AP) { 359 aprint_naive(": Application Processor\n"); 360 ptr = (uintptr_t)malloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 361 M_DEVBUF, M_WAITOK); 362 ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) & 363 ~(CACHE_LINE_SIZE - 1)); 364 memset(ci, 0, sizeof(*ci)); 365 #if defined(MULTIPROCESSOR) 366 if (cpu_info[cpunum] != NULL) 367 panic("cpu at apic id %d already attached?", cpunum); 368 cpu_info[cpunum] = ci; 369 #endif 370 #ifdef TRAPLOG 371 ci->ci_tlog_base = malloc(sizeof(struct tlog), 372 M_DEVBUF, M_WAITOK); 373 #endif 374 } else { 375 aprint_naive(": %s Processor\n", 376 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 377 ci = &cpu_info_primary; 378 #if defined(MULTIPROCESSOR) 379 if (cpunum != lapic_cpu_number()) { 380 panic("%s: running CPU is at apic %d" 381 " instead of at expected %d", 382 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 383 } 384 #endif 385 } 386 387 ci->ci_self = ci; 388 sc->sc_info = ci; 389 390 ci->ci_dev = self; 391 ci->ci_apicid = caa->cpu_number; 392 #ifdef MULTIPROCESSOR 393 ci->ci_cpuid = ci->ci_apicid; 394 #else 395 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 396 #endif 397 ci->ci_cpumask = (1 << ci->ci_cpuid); 398 ci->ci_func = caa->cpu_func; 399 400 if (caa->cpu_role == CPU_ROLE_AP) { 401 #if defined(MULTIPROCESSOR) 402 int error; 403 404 error = mi_cpu_attach(ci); 405 if (error != 0) { 406 aprint_normal("\n"); 407 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 408 error); 409 return; 410 } 411 #endif 412 } else { 413 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 414 } 415 416 pmap_reference(pmap_kernel()); 417 ci->ci_pmap = pmap_kernel(); 418 ci->ci_tlbstate = TLBSTATE_STALE; 419 420 /* further PCB init done later. */ 421 422 switch (caa->cpu_role) { 423 case CPU_ROLE_SP: 424 aprint_normal(": (uniprocessor)\n"); 425 atomic_or_32(&ci->ci_flags, 426 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 427 cpu_intr_init(ci); 428 identifycpu(ci); 429 cpu_init(ci); 430 cpu_set_tss_gates(ci); 431 pmap_cpu_init_late(ci); 432 #if 0 433 x86_errata(); 434 #endif 435 break; 436 437 case CPU_ROLE_BP: 438 aprint_normal("apid %d (boot processor)\n", caa->cpu_number); 439 atomic_or_32(&ci->ci_flags, 440 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 441 cpu_intr_init(ci); 442 identifycpu(ci); 443 cpu_init(ci); 444 cpu_set_tss_gates(ci); 445 pmap_cpu_init_late(ci); 446 #if NLAPIC > 0 447 /* 448 * Enable local apic 449 */ 450 lapic_enable(); 451 lapic_set_lvt(); 452 lapic_calibrate_timer(ci); 453 #endif 454 #if 0 455 x86_errata(); 456 #endif 457 break; 458 459 case CPU_ROLE_AP: 460 /* 461 * report on an AP 462 */ 463 aprint_normal("apid %d (application processor)\n", caa->cpu_number); 464 465 #if defined(MULTIPROCESSOR) 466 cpu_intr_init(ci); 467 gdt_alloc_cpu(ci); 468 cpu_set_tss_gates(ci); 469 pmap_cpu_init_early(ci); 470 pmap_cpu_init_late(ci); 471 cpu_start_secondary(ci); 472 if (ci->ci_flags & CPUF_PRESENT) { 473 identifycpu(ci); 474 ci->ci_next = cpu_info_list->ci_next; 475 cpu_info_list->ci_next = ci; 476 } 477 #else 478 aprint_normal_dev(sc->sc_dev, "not started\n"); 479 #endif 480 break; 481 482 default: 483 aprint_normal("\n"); 484 panic("unknown processor type??\n"); 485 } 486 cpu_vm_init(ci); 487 488 cpus_attached |= (1 << ci->ci_cpuid); 489 490 #if 0 491 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 492 aprint_error_dev(self, "couldn't establish power handler\n"); 493 #endif 494 495 #if defined(MULTIPROCESSOR) 496 if (mp_verbose) { 497 struct lwp *l = ci->ci_data.cpu_idlelwp; 498 499 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n", 500 l, 501 #ifdef i386 502 (void *)l->l_addr->u_pcb.pcb_esp 503 #else 504 (void *)l->l_addr->u_pcb.pcb_rsp 505 #endif 506 ); 507 508 } 509 #endif 510 } 511 512 /* 513 * Initialize the processor appropriately. 514 */ 515 516 void 517 cpu_init(struct cpu_info *ci) 518 { 519 /* configure the CPU if needed */ 520 if (ci->cpu_setup != NULL) 521 (*ci->cpu_setup)(ci); 522 523 /* 524 * On a P6 or above, enable global TLB caching if the 525 * hardware supports it. 526 */ 527 if (cpu_feature & CPUID_PGE) 528 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 529 530 #ifdef XXXMTRR 531 /* 532 * On a P6 or above, initialize MTRR's if the hardware supports them. 533 */ 534 if (cpu_feature & CPUID_MTRR) { 535 if ((ci->ci_flags & CPUF_AP) == 0) 536 i686_mtrr_init_first(); 537 mtrr_init_cpu(ci); 538 } 539 #endif 540 /* 541 * If we have FXSAVE/FXRESTOR, use them. 542 */ 543 if (cpu_feature & CPUID_FXSR) { 544 lcr4(rcr4() | CR4_OSFXSR); 545 546 /* 547 * If we have SSE/SSE2, enable XMM exceptions. 548 */ 549 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 550 lcr4(rcr4() | CR4_OSXMMEXCPT); 551 } 552 553 #ifdef MULTIPROCESSOR 554 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 555 atomic_or_32(&cpus_running, ci->ci_cpumask); 556 #endif 557 } 558 559 560 #ifdef MULTIPROCESSOR 561 void 562 cpu_boot_secondary_processors(void) 563 { 564 struct cpu_info *ci; 565 u_long i; 566 567 for (i = 0; i < X86_MAXPROCS; i++) { 568 ci = cpu_info[i]; 569 if (ci == NULL) 570 continue; 571 if (ci->ci_data.cpu_idlelwp == NULL) 572 continue; 573 if ((ci->ci_flags & CPUF_PRESENT) == 0) 574 continue; 575 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 576 continue; 577 cpu_boot_secondary(ci); 578 } 579 580 x86_mp_online = true; 581 } 582 583 static void 584 cpu_init_idle_lwp(struct cpu_info *ci) 585 { 586 struct lwp *l = ci->ci_data.cpu_idlelwp; 587 struct pcb *pcb = &l->l_addr->u_pcb; 588 589 pcb->pcb_cr0 = rcr0(); 590 } 591 592 void 593 cpu_init_idle_lwps(void) 594 { 595 struct cpu_info *ci; 596 u_long i; 597 598 for (i = 0; i < X86_MAXPROCS; i++) { 599 ci = cpu_info[i]; 600 if (ci == NULL) 601 continue; 602 if (ci->ci_data.cpu_idlelwp == NULL) 603 continue; 604 if ((ci->ci_flags & CPUF_PRESENT) == 0) 605 continue; 606 cpu_init_idle_lwp(ci); 607 } 608 } 609 610 void 611 cpu_start_secondary(struct cpu_info *ci) 612 { 613 int i; 614 struct pmap *kpm = pmap_kernel(); 615 extern uint32_t mp_pdirpa; 616 617 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 618 619 atomic_or_32(&ci->ci_flags, CPUF_AP); 620 621 aprint_debug_dev(ci->ci_dev, "starting\n"); 622 623 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 624 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 625 return; 626 627 /* 628 * wait for it to become ready 629 */ 630 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 631 #ifdef MPDEBUG 632 extern int cpu_trace[3]; 633 static int otrace[3]; 634 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 635 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 636 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 637 memcpy(otrace, cpu_trace, sizeof(otrace)); 638 } 639 #endif 640 delay(10); 641 } 642 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 643 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 644 #if defined(MPDEBUG) && defined(DDB) 645 printf("dropping into debugger; continue from here to resume boot\n"); 646 Debugger(); 647 #endif 648 } 649 650 CPU_START_CLEANUP(ci); 651 } 652 653 void 654 cpu_boot_secondary(struct cpu_info *ci) 655 { 656 int i; 657 658 atomic_or_32(&ci->ci_flags, CPUF_GO); 659 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 660 delay(10); 661 } 662 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 663 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 664 #if defined(MPDEBUG) && defined(DDB) 665 printf("dropping into debugger; continue from here to resume boot\n"); 666 Debugger(); 667 #endif 668 } 669 } 670 671 /* 672 * The CPU ends up here when its ready to run 673 * This is called from code in mptramp.s; at this point, we are running 674 * in the idle pcb/idle stack of the new CPU. When this function returns, 675 * this processor will enter the idle loop and start looking for work. 676 * 677 * XXX should share some of this with init386 in machdep.c 678 */ 679 void 680 cpu_hatch(void *v) 681 { 682 struct cpu_info *ci = (struct cpu_info *)v; 683 int s, i; 684 uint32_t blacklist_features; 685 686 #ifdef __x86_64__ 687 cpu_init_msrs(ci, true); 688 #endif 689 690 cpu_probe_features(ci); 691 cpu_feature &= ci->ci_feature_flags; 692 cpu_feature2 &= ci->ci_feature2_flags; 693 694 /* not on Xen... */ 695 blacklist_features = ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); /* XXX add CPUID_SVM */ 696 697 cpu_feature &= blacklist_features; 698 699 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 700 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 701 while ((ci->ci_flags & CPUF_GO) == 0) { 702 /* Don't use delay, boot CPU may be patching the text. */ 703 for (i = 10000; i != 0; i--) 704 x86_pause(); 705 } 706 707 /* Because the text may have been patched in x86_patch(). */ 708 wbinvd(); 709 x86_flush(); 710 711 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 712 713 lcr3(pmap_kernel()->pm_pdirpa); 714 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 715 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 716 cpu_init_idt(); 717 gdt_init_cpu(ci); 718 lapic_enable(); 719 lapic_set_lvt(); 720 lapic_initclocks(); 721 722 #ifdef i386 723 npxinit(ci); 724 #else 725 fpuinit(ci); 726 #endif 727 728 lldt(GSEL(GLDT_SEL, SEL_KPL)); 729 ltr(ci->ci_tss_sel); 730 731 cpu_init(ci); 732 cpu_get_tsc_freq(ci); 733 734 s = splhigh(); 735 #ifdef i386 736 lapic_tpr = 0; 737 #else 738 lcr8(0); 739 #endif 740 x86_enable_intr(); 741 splx(s); 742 #if 0 743 x86_errata(); 744 #endif 745 746 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 747 (long)ci->ci_cpuid); 748 } 749 750 #if defined(DDB) 751 752 #include <ddb/db_output.h> 753 #include <machine/db_machdep.h> 754 755 /* 756 * Dump CPU information from ddb. 757 */ 758 void 759 cpu_debug_dump(void) 760 { 761 struct cpu_info *ci; 762 CPU_INFO_ITERATOR cii; 763 764 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 765 for (CPU_INFO_FOREACH(cii, ci)) { 766 db_printf("%p %s %ld %x %x %10p %10p\n", 767 ci, 768 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 769 (long)ci->ci_cpuid, 770 ci->ci_flags, ci->ci_ipis, 771 ci->ci_curlwp, 772 ci->ci_fpcurlwp); 773 } 774 } 775 #endif 776 777 static void 778 cpu_copy_trampoline(void) 779 { 780 /* 781 * Copy boot code. 782 */ 783 extern u_char cpu_spinup_trampoline[]; 784 extern u_char cpu_spinup_trampoline_end[]; 785 786 vaddr_t mp_trampoline_vaddr; 787 788 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 789 UVM_KMF_VAONLY); 790 791 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 792 VM_PROT_READ | VM_PROT_WRITE); 793 pmap_update(pmap_kernel()); 794 memcpy((void *)mp_trampoline_vaddr, 795 cpu_spinup_trampoline, 796 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 797 798 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 799 pmap_update(pmap_kernel()); 800 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 801 } 802 803 #endif 804 805 #ifdef i386 806 #if 0 807 static void 808 tss_init(struct i386tss *tss, void *stack, void *func) 809 { 810 memset(tss, 0, sizeof *tss); 811 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 812 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 813 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 814 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 815 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 816 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 817 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 818 tss->tss_esp = (int)((char *)stack + USPACE - 16); 819 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 820 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 821 tss->__tss_eip = (int)func; 822 } 823 #endif 824 825 /* XXX */ 826 #define IDTVEC(name) __CONCAT(X, name) 827 typedef void (vector)(void); 828 extern vector IDTVEC(tss_trap08); 829 #ifdef DDB 830 extern vector Xintrddbipi; 831 extern int ddb_vec; 832 #endif 833 834 static void 835 cpu_set_tss_gates(struct cpu_info *ci) 836 { 837 #if 0 838 struct segment_descriptor sd; 839 840 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 841 UVM_KMF_WIRED); 842 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 843 IDTVEC(tss_trap08)); 844 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 845 SDT_SYS386TSS, SEL_KPL, 0, 0); 846 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 847 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 848 GSEL(GTRAPTSS_SEL, SEL_KPL)); 849 #endif 850 851 #if defined(DDB) && defined(MULTIPROCESSOR) 852 /* 853 * Set up separate handler for the DDB IPI, so that it doesn't 854 * stomp on a possibly corrupted stack. 855 * 856 * XXX overwriting the gate set in db_machine_init. 857 * Should rearrange the code so that it's set only once. 858 */ 859 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 860 UVM_KMF_WIRED); 861 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 862 Xintrddbipi); 863 864 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 865 SDT_SYS386TSS, SEL_KPL, 0, 0); 866 ci->ci_gdt[GIPITSS_SEL].sd = sd; 867 868 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 869 GSEL(GIPITSS_SEL, SEL_KPL)); 870 #endif 871 } 872 #else 873 static void 874 cpu_set_tss_gates(struct cpu_info *ci) 875 { 876 877 } 878 #endif /* i386 */ 879 880 int 881 mp_cpu_start(struct cpu_info *ci, paddr_t target) 882 { 883 #if 0 884 #if NLAPIC > 0 885 int error; 886 #endif 887 unsigned short dwordptr[2]; 888 889 /* 890 * Bootstrap code must be addressable in real mode 891 * and it must be page aligned. 892 */ 893 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 894 895 /* 896 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 897 */ 898 899 outb(IO_RTC, NVRAM_RESET); 900 outb(IO_RTC+1, NVRAM_RESET_JUMP); 901 902 /* 903 * "and the warm reset vector (DWORD based at 40:67) to point 904 * to the AP startup code ..." 905 */ 906 907 dwordptr[0] = 0; 908 dwordptr[1] = target >> 4; 909 910 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 911 memcpy ((uint8_t *) 0x467, dwordptr, 4); 912 pmap_kremove (0, PAGE_SIZE); 913 914 #if NLAPIC > 0 915 /* 916 * ... prior to executing the following sequence:" 917 */ 918 919 if (ci->ci_flags & CPUF_AP) { 920 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 921 return error; 922 923 delay(10000); 924 925 if (cpu_feature & CPUID_APIC) { 926 error = x86_ipi_init(ci->ci_apicid); 927 if (error != 0) { 928 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 929 __func__); 930 return error; 931 } 932 933 delay(10000); 934 935 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 936 LAPIC_DLMODE_STARTUP); 937 if (error != 0) { 938 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 939 __func__); 940 return error; 941 } 942 delay(200); 943 944 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 945 LAPIC_DLMODE_STARTUP); 946 if (error != 0) { 947 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 948 __func__); 949 return error; 950 } 951 delay(200); 952 } 953 } 954 #endif 955 #endif /* 0 */ 956 return 0; 957 } 958 959 void 960 mp_cpu_start_cleanup(struct cpu_info *ci) 961 { 962 #if 0 963 /* 964 * Ensure the NVRAM reset byte contains something vaguely sane. 965 */ 966 967 outb(IO_RTC, NVRAM_RESET); 968 outb(IO_RTC+1, NVRAM_RESET_RST); 969 #endif 970 } 971 972 #ifdef __x86_64__ 973 974 void 975 cpu_init_msrs(struct cpu_info *ci, bool full) 976 { 977 if (full) { 978 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 979 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 980 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 981 } 982 } 983 #endif /* __x86_64__ */ 984 985 void 986 cpu_offline_md(void) 987 { 988 int s; 989 990 s = splhigh(); 991 #ifdef __i386__ 992 npxsave_cpu(true); 993 #else 994 fpusave_cpu(true); 995 #endif 996 splx(s); 997 } 998 999 #if 0 1000 /* XXX joerg restructure and restart CPUs individually */ 1001 static bool 1002 cpu_suspend(device_t dv PMF_FN_ARGS) 1003 { 1004 struct cpu_softc *sc = device_private(dv); 1005 struct cpu_info *ci = sc->sc_info; 1006 int err; 1007 1008 if (ci->ci_flags & CPUF_PRIMARY) 1009 return true; 1010 if (ci->ci_data.cpu_idlelwp == NULL) 1011 return true; 1012 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1013 return true; 1014 1015 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1016 1017 if (sc->sc_wasonline) { 1018 mutex_enter(&cpu_lock); 1019 err = cpu_setonline(ci, false); 1020 mutex_exit(&cpu_lock); 1021 1022 if (err) 1023 return false; 1024 } 1025 1026 return true; 1027 } 1028 1029 static bool 1030 cpu_resume(device_t dv PMF_FN_ARGS) 1031 { 1032 struct cpu_softc *sc = device_private(dv); 1033 struct cpu_info *ci = sc->sc_info; 1034 int err = 0; 1035 1036 if (ci->ci_flags & CPUF_PRIMARY) 1037 return true; 1038 if (ci->ci_data.cpu_idlelwp == NULL) 1039 return true; 1040 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1041 return true; 1042 1043 if (sc->sc_wasonline) { 1044 mutex_enter(&cpu_lock); 1045 err = cpu_setonline(ci, true); 1046 mutex_exit(&cpu_lock); 1047 } 1048 1049 return err == 0; 1050 } 1051 #endif 1052 1053 void 1054 cpu_get_tsc_freq(struct cpu_info *ci) 1055 { 1056 #ifdef XEN3 1057 const volatile vcpu_time_info_t *tinfo = 1058 &HYPERVISOR_shared_info->vcpu_info[0].time; 1059 delay(1000000); 1060 uint64_t freq = 1000000000ULL << 32; 1061 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1062 if ( tinfo->tsc_shift < 0 ) 1063 freq = freq << -tinfo->tsc_shift; 1064 else 1065 freq = freq >> tinfo->tsc_shift; 1066 ci->ci_tsc_freq = freq; 1067 #else 1068 /* XXX this needs to read the shared_info of the CPU being probed.. */ 1069 ci->ci_tsc_freq = HYPERVISOR_shared_info->cpu_freq; 1070 #endif /* XEN3 */ 1071 } 1072
Indexes created Fri Oct 03 15:10:06 GMT 2025