cpu.c revision 1.17
1 /* $NetBSD: cpu.c,v 1.17 2008/04/24 20:44:02 cegger Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Copyright (c) 1999 Stefan Grefen 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the NetBSD 56 * Foundation, Inc. and its contributors. 57 * 4. Neither the name of The NetBSD Foundation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 62 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.17 2008/04/24 20:44:02 cegger Exp $"); 76 77 #include "opt_ddb.h" 78 #include "opt_multiprocessor.h" 79 #include "opt_mpbios.h" /* for MPDEBUG */ 80 #include "opt_mtrr.h" 81 #include "opt_xen.h" 82 83 #include "lapic.h" 84 #include "ioapic.h" 85 86 #include <sys/param.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 #include <sys/cpu.h> 93 #include <sys/atomic.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #include <machine/cpufunc.h> 98 #include <machine/cpuvar.h> 99 #include <machine/pmap.h> 100 #include <machine/vmparam.h> 101 #include <machine/mpbiosvar.h> 102 #include <machine/pcb.h> 103 #include <machine/specialreg.h> 104 #include <machine/segments.h> 105 #include <machine/gdt.h> 106 #include <machine/mtrr.h> 107 #include <machine/pio.h> 108 109 #ifdef XEN3 110 #include <xen/vcpuvar.h> 111 #endif 112 113 #if NLAPIC > 0 114 #include <machine/apicvar.h> 115 #include <machine/i82489reg.h> 116 #include <machine/i82489var.h> 117 #endif 118 119 #include <dev/ic/mc146818reg.h> 120 #include <dev/isa/isareg.h> 121 122 int cpu_match(device_t, cfdata_t, void *); 123 void cpu_attach(device_t, device_t, void *); 124 #ifdef XEN3 125 int vcpu_match(device_t, cfdata_t, void *); 126 void vcpu_attach(device_t, device_t, void *); 127 #endif 128 void cpu_attach_common(device_t, device_t, void *); 129 void cpu_offline_md(void); 130 131 struct cpu_softc { 132 device_t sc_dev; /* device tree glue */ 133 struct cpu_info *sc_info; /* pointer to CPU info */ 134 }; 135 136 int mp_cpu_start(struct cpu_info *, paddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL); 143 #ifdef XEN3 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 #endif 147 148 /* 149 * Statically-allocated CPU info for the primary CPU (or the only 150 * CPU, on uniprocessors). The CPU info list is initialized to 151 * point at it. 152 */ 153 #ifdef TRAPLOG 154 #include <machine/tlog.h> 155 struct tlog tlog_primary; 156 #endif 157 struct cpu_info cpu_info_primary = { 158 .ci_dev = 0, 159 .ci_self = &cpu_info_primary, 160 .ci_idepth = -1, 161 .ci_curlwp = &lwp0, 162 #ifdef TRAPLOG 163 .ci_tlog = &tlog_primary, 164 #endif 165 166 }; 167 struct cpu_info phycpu_info_primary = { 168 .ci_dev = 0, 169 .ci_self = &phycpu_info_primary, 170 }; 171 172 struct cpu_info *cpu_info_list = &cpu_info_primary; 173 174 static void cpu_set_tss_gates(struct cpu_info *ci); 175 176 uint32_t cpus_attached = 0; 177 uint32_t cpus_running = 0; 178 179 bool x86_mp_online; 180 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 181 182 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 183 184 #ifdef MULTIPROCESSOR 185 /* 186 * Array of CPU info structures. Must be statically-allocated because 187 * curproc, etc. are used early. 188 */ 189 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 190 191 void cpu_hatch(void *); 192 static void cpu_boot_secondary(struct cpu_info *ci); 193 static void cpu_start_secondary(struct cpu_info *ci); 194 static void cpu_copy_trampoline(void); 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 void 203 cpu_init_first(void) 204 { 205 int cpunum = lapic_cpu_number(); 206 207 if (cpunum != 0) { 208 cpu_info[0] = NULL; 209 cpu_info[cpunum] = &cpu_info_primary; 210 } 211 212 cpu_copy_trampoline(); 213 } 214 #endif 215 216 int 217 cpu_match(device_t parent, cfdata_t match, void *aux) 218 { 219 220 return 1; 221 } 222 223 void 224 cpu_attach(device_t parent, device_t self, void *aux) 225 { 226 #ifdef XEN3 227 struct cpu_softc *sc = device_private(self); 228 struct cpu_attach_args *caa = aux; 229 struct cpu_info *ci; 230 int cpunum = caa->cpu_number; 231 232 sc->sc_dev = self; 233 234 /* 235 * If we're an Application Processor, allocate a cpu_info 236 * structure, otherwise use the primary's. 237 */ 238 if (caa->cpu_role == CPU_ROLE_AP) { 239 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 240 if (phycpu_info[cpunum] != NULL) 241 panic("cpu at apic id %d already attached?", cpunum); 242 phycpu_info[cpunum] = ci; 243 } else { 244 ci = &phycpu_info_primary; 245 if (cpunum != 0) { 246 phycpu_info[0] = NULL; 247 phycpu_info[cpunum] = ci; 248 } 249 } 250 251 ci->ci_self = ci; 252 sc->sc_info = ci; 253 254 ci->ci_dev = self; 255 ci->ci_apicid = caa->cpu_number; 256 ci->ci_cpuid = ci->ci_apicid; 257 ci->ci_vcpu = NULL; 258 259 printf(": "); 260 switch (caa->cpu_role) { 261 case CPU_ROLE_SP: 262 printf("(uniprocessor)\n"); 263 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 264 break; 265 266 case CPU_ROLE_BP: 267 printf("(boot processor)\n"); 268 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 269 break; 270 271 case CPU_ROLE_AP: 272 /* 273 * report on an AP 274 */ 275 printf("(application processor)\n"); 276 break; 277 278 default: 279 panic("unknown processor type??\n"); 280 } 281 return; 282 #else 283 cpu_attach_common(parent, self, aux); 284 #endif 285 } 286 287 #ifdef XEN3 288 int 289 vcpu_match(device_t parent, cfdata_t match, void *aux) 290 { 291 struct vcpu_attach_args *vcaa = aux; 292 293 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 294 return 1; 295 return 0; 296 } 297 298 void 299 vcpu_attach(device_t parent, device_t self, void *aux) 300 { 301 struct vcpu_attach_args *vcaa = aux; 302 303 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 304 } 305 #endif 306 307 static void 308 cpu_vm_init(struct cpu_info *ci) 309 { 310 int ncolors = 2, i; 311 312 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 313 struct x86_cache_info *cai; 314 int tcolors; 315 316 cai = &ci->ci_cinfo[i]; 317 318 tcolors = atop(cai->cai_totalsize); 319 switch(cai->cai_associativity) { 320 case 0xff: 321 tcolors = 1; /* fully associative */ 322 break; 323 case 0: 324 case 1: 325 break; 326 default: 327 tcolors /= cai->cai_associativity; 328 } 329 ncolors = max(ncolors, tcolors); 330 } 331 332 /* 333 * Knowing the size of the largest cache on this CPU, re-color 334 * our pages. 335 */ 336 if (ncolors <= uvmexp.ncolors) 337 return; 338 printf("%s: %d page colors\n", device_xname(ci->ci_dev), ncolors); 339 uvm_page_recolor(ncolors); 340 } 341 342 void 343 cpu_attach_common(device_t parent, device_t self, void *aux) 344 { 345 struct cpu_softc *sc = device_private(self); 346 struct cpu_attach_args *caa = aux; 347 struct cpu_info *ci; 348 uintptr_t ptr; 349 int cpunum = caa->cpu_number; 350 351 sc->sc_dev = self; 352 353 /* 354 * If we're an Application Processor, allocate a cpu_info 355 * structure, otherwise use the primary's. 356 */ 357 if (caa->cpu_role == CPU_ROLE_AP) { 358 if (cpunum >= X86_MAXPROCS) { 359 aprint_error(": apic id %d ignored, " 360 "please increase X86_MAXPROCS\n", cpunum); 361 } 362 363 aprint_naive(": Application Processor\n"); 364 ptr = (uintptr_t)malloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 365 M_DEVBUF, M_WAITOK); 366 ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) & 367 ~(CACHE_LINE_SIZE - 1)); 368 memset(ci, 0, sizeof(*ci)); 369 #if defined(MULTIPROCESSOR) 370 if (cpu_info[cpunum] != NULL) 371 panic("cpu at apic id %d already attached?", cpunum); 372 cpu_info[cpunum] = ci; 373 #endif 374 #ifdef TRAPLOG 375 ci->ci_tlog_base = malloc(sizeof(struct tlog), 376 M_DEVBUF, M_WAITOK); 377 #endif 378 } else { 379 aprint_naive(": %s Processor\n", 380 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 381 ci = &cpu_info_primary; 382 #if defined(MULTIPROCESSOR) 383 if (cpunum != lapic_cpu_number()) { 384 panic("%s: running CPU is at apic %d" 385 " instead of at expected %d", 386 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 387 } 388 #endif 389 } 390 391 ci->ci_self = ci; 392 sc->sc_info = ci; 393 394 ci->ci_dev = self; 395 ci->ci_apicid = cpunum; 396 397 KASSERT(HYPERVISOR_shared_info != NULL); 398 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 399 400 #ifdef MULTIPROCESSOR 401 ci->ci_cpuid = ci->ci_apicid; 402 #else 403 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 404 #endif 405 ci->ci_cpumask = (1 << ci->ci_cpuid); 406 ci->ci_func = caa->cpu_func; 407 408 if (caa->cpu_role == CPU_ROLE_AP) { 409 #if defined(MULTIPROCESSOR) 410 int error; 411 412 error = mi_cpu_attach(ci); 413 if (error != 0) { 414 aprint_normal("\n"); 415 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 416 error); 417 return; 418 } 419 #endif 420 } else { 421 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 422 } 423 424 pmap_reference(pmap_kernel()); 425 ci->ci_pmap = pmap_kernel(); 426 ci->ci_tlbstate = TLBSTATE_STALE; 427 428 /* further PCB init done later. */ 429 430 switch (caa->cpu_role) { 431 case CPU_ROLE_SP: 432 aprint_normal(": (uniprocessor)\n"); 433 atomic_or_32(&ci->ci_flags, 434 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 435 cpu_intr_init(ci); 436 identifycpu(ci); 437 cpu_init(ci); 438 cpu_set_tss_gates(ci); 439 pmap_cpu_init_late(ci); 440 #if 0 441 x86_errata(); 442 #endif 443 break; 444 445 case CPU_ROLE_BP: 446 aprint_normal("apid %d (boot processor)\n", caa->cpu_number); 447 atomic_or_32(&ci->ci_flags, 448 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 449 cpu_intr_init(ci); 450 identifycpu(ci); 451 cpu_init(ci); 452 cpu_set_tss_gates(ci); 453 pmap_cpu_init_late(ci); 454 #if NLAPIC > 0 455 /* 456 * Enable local apic 457 */ 458 lapic_enable(); 459 lapic_set_lvt(); 460 lapic_calibrate_timer(ci); 461 #endif 462 #if 0 463 x86_errata(); 464 #endif 465 break; 466 467 case CPU_ROLE_AP: 468 /* 469 * report on an AP 470 */ 471 aprint_normal("apid %d (application processor)\n", caa->cpu_number); 472 473 #if defined(MULTIPROCESSOR) 474 cpu_intr_init(ci); 475 gdt_alloc_cpu(ci); 476 cpu_set_tss_gates(ci); 477 pmap_cpu_init_early(ci); 478 pmap_cpu_init_late(ci); 479 cpu_start_secondary(ci); 480 if (ci->ci_flags & CPUF_PRESENT) { 481 identifycpu(ci); 482 ci->ci_next = cpu_info_list->ci_next; 483 cpu_info_list->ci_next = ci; 484 } 485 #else 486 aprint_normal_dev(sc->sc_dev, "not started\n"); 487 #endif 488 break; 489 490 default: 491 aprint_normal("\n"); 492 panic("unknown processor type??\n"); 493 } 494 cpu_vm_init(ci); 495 496 cpus_attached |= (1 << ci->ci_cpuid); 497 498 #if 0 499 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 500 aprint_error_dev(self, "couldn't establish power handler\n"); 501 #endif 502 503 #if defined(MULTIPROCESSOR) 504 if (mp_verbose) { 505 struct lwp *l = ci->ci_data.cpu_idlelwp; 506 507 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n", 508 l, 509 #ifdef i386 510 (void *)l->l_addr->u_pcb.pcb_esp 511 #else 512 (void *)l->l_addr->u_pcb.pcb_rsp 513 #endif 514 ); 515 516 } 517 #endif 518 } 519 520 /* 521 * Initialize the processor appropriately. 522 */ 523 524 void 525 cpu_init(struct cpu_info *ci) 526 { 527 /* configure the CPU if needed */ 528 if (ci->cpu_setup != NULL) 529 (*ci->cpu_setup)(ci); 530 531 /* 532 * On a P6 or above, enable global TLB caching if the 533 * hardware supports it. 534 */ 535 if (cpu_feature & CPUID_PGE) 536 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 537 538 #ifdef XXXMTRR 539 /* 540 * On a P6 or above, initialize MTRR's if the hardware supports them. 541 */ 542 if (cpu_feature & CPUID_MTRR) { 543 if ((ci->ci_flags & CPUF_AP) == 0) 544 i686_mtrr_init_first(); 545 mtrr_init_cpu(ci); 546 } 547 #endif 548 /* 549 * If we have FXSAVE/FXRESTOR, use them. 550 */ 551 if (cpu_feature & CPUID_FXSR) { 552 lcr4(rcr4() | CR4_OSFXSR); 553 554 /* 555 * If we have SSE/SSE2, enable XMM exceptions. 556 */ 557 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 558 lcr4(rcr4() | CR4_OSXMMEXCPT); 559 } 560 561 #ifdef MULTIPROCESSOR 562 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 563 atomic_or_32(&cpus_running, ci->ci_cpumask); 564 #endif 565 } 566 567 568 #ifdef MULTIPROCESSOR 569 void 570 cpu_boot_secondary_processors(void) 571 { 572 struct cpu_info *ci; 573 u_long i; 574 575 for (i = 0; i < X86_MAXPROCS; i++) { 576 ci = cpu_info[i]; 577 if (ci == NULL) 578 continue; 579 if (ci->ci_data.cpu_idlelwp == NULL) 580 continue; 581 if ((ci->ci_flags & CPUF_PRESENT) == 0) 582 continue; 583 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 584 continue; 585 cpu_boot_secondary(ci); 586 } 587 588 x86_mp_online = true; 589 } 590 591 static void 592 cpu_init_idle_lwp(struct cpu_info *ci) 593 { 594 struct lwp *l = ci->ci_data.cpu_idlelwp; 595 struct pcb *pcb = &l->l_addr->u_pcb; 596 597 pcb->pcb_cr0 = rcr0(); 598 } 599 600 void 601 cpu_init_idle_lwps(void) 602 { 603 struct cpu_info *ci; 604 u_long i; 605 606 for (i = 0; i < X86_MAXPROCS; i++) { 607 ci = cpu_info[i]; 608 if (ci == NULL) 609 continue; 610 if (ci->ci_data.cpu_idlelwp == NULL) 611 continue; 612 if ((ci->ci_flags & CPUF_PRESENT) == 0) 613 continue; 614 cpu_init_idle_lwp(ci); 615 } 616 } 617 618 void 619 cpu_start_secondary(struct cpu_info *ci) 620 { 621 int i; 622 struct pmap *kpm = pmap_kernel(); 623 extern uint32_t mp_pdirpa; 624 625 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 626 627 atomic_or_32(&ci->ci_flags, CPUF_AP); 628 629 aprint_debug_dev(ci->ci_dev, "starting\n"); 630 631 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 632 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 633 return; 634 635 /* 636 * wait for it to become ready 637 */ 638 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 639 #ifdef MPDEBUG 640 extern int cpu_trace[3]; 641 static int otrace[3]; 642 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 643 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 644 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 645 memcpy(otrace, cpu_trace, sizeof(otrace)); 646 } 647 #endif 648 delay(10); 649 } 650 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 651 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 652 #if defined(MPDEBUG) && defined(DDB) 653 printf("dropping into debugger; continue from here to resume boot\n"); 654 Debugger(); 655 #endif 656 } 657 658 CPU_START_CLEANUP(ci); 659 } 660 661 void 662 cpu_boot_secondary(struct cpu_info *ci) 663 { 664 int i; 665 666 atomic_or_32(&ci->ci_flags, CPUF_GO); 667 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 668 delay(10); 669 } 670 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 671 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 672 #if defined(MPDEBUG) && defined(DDB) 673 printf("dropping into debugger; continue from here to resume boot\n"); 674 Debugger(); 675 #endif 676 } 677 } 678 679 /* 680 * The CPU ends up here when its ready to run 681 * This is called from code in mptramp.s; at this point, we are running 682 * in the idle pcb/idle stack of the new CPU. When this function returns, 683 * this processor will enter the idle loop and start looking for work. 684 * 685 * XXX should share some of this with init386 in machdep.c 686 */ 687 void 688 cpu_hatch(void *v) 689 { 690 struct cpu_info *ci = (struct cpu_info *)v; 691 int s, i; 692 uint32_t blacklist_features; 693 694 #ifdef __x86_64__ 695 cpu_init_msrs(ci, true); 696 #endif 697 698 cpu_probe_features(ci); 699 cpu_feature &= ci->ci_feature_flags; 700 cpu_feature2 &= ci->ci_feature2_flags; 701 702 /* not on Xen... */ 703 blacklist_features = ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); /* XXX add CPUID_SVM */ 704 705 cpu_feature &= blacklist_features; 706 707 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 708 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 709 while ((ci->ci_flags & CPUF_GO) == 0) { 710 /* Don't use delay, boot CPU may be patching the text. */ 711 for (i = 10000; i != 0; i--) 712 x86_pause(); 713 } 714 715 /* Because the text may have been patched in x86_patch(). */ 716 wbinvd(); 717 x86_flush(); 718 719 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 720 721 lcr3(pmap_kernel()->pm_pdirpa); 722 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 723 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 724 cpu_init_idt(); 725 gdt_init_cpu(ci); 726 lapic_enable(); 727 lapic_set_lvt(); 728 lapic_initclocks(); 729 730 #ifdef i386 731 npxinit(ci); 732 #else 733 fpuinit(ci); 734 #endif 735 736 lldt(GSEL(GLDT_SEL, SEL_KPL)); 737 ltr(ci->ci_tss_sel); 738 739 cpu_init(ci); 740 cpu_get_tsc_freq(ci); 741 742 s = splhigh(); 743 #ifdef i386 744 lapic_tpr = 0; 745 #else 746 lcr8(0); 747 #endif 748 x86_enable_intr(); 749 splx(s); 750 #if 0 751 x86_errata(); 752 #endif 753 754 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 755 (long)ci->ci_cpuid); 756 } 757 758 #if defined(DDB) 759 760 #include <ddb/db_output.h> 761 #include <machine/db_machdep.h> 762 763 /* 764 * Dump CPU information from ddb. 765 */ 766 void 767 cpu_debug_dump(void) 768 { 769 struct cpu_info *ci; 770 CPU_INFO_ITERATOR cii; 771 772 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 773 for (CPU_INFO_FOREACH(cii, ci)) { 774 db_printf("%p %s %ld %x %x %10p %10p\n", 775 ci, 776 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 777 (long)ci->ci_cpuid, 778 ci->ci_flags, ci->ci_ipis, 779 ci->ci_curlwp, 780 ci->ci_fpcurlwp); 781 } 782 } 783 #endif 784 785 static void 786 cpu_copy_trampoline(void) 787 { 788 /* 789 * Copy boot code. 790 */ 791 extern u_char cpu_spinup_trampoline[]; 792 extern u_char cpu_spinup_trampoline_end[]; 793 794 vaddr_t mp_trampoline_vaddr; 795 796 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 797 UVM_KMF_VAONLY); 798 799 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 800 VM_PROT_READ | VM_PROT_WRITE); 801 pmap_update(pmap_kernel()); 802 memcpy((void *)mp_trampoline_vaddr, 803 cpu_spinup_trampoline, 804 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 805 806 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 807 pmap_update(pmap_kernel()); 808 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 809 } 810 811 #endif 812 813 #ifdef i386 814 #if 0 815 static void 816 tss_init(struct i386tss *tss, void *stack, void *func) 817 { 818 memset(tss, 0, sizeof *tss); 819 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 820 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 821 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 822 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 823 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 824 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 825 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 826 tss->tss_esp = (int)((char *)stack + USPACE - 16); 827 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 828 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 829 tss->__tss_eip = (int)func; 830 } 831 #endif 832 833 /* XXX */ 834 #define IDTVEC(name) __CONCAT(X, name) 835 typedef void (vector)(void); 836 extern vector IDTVEC(tss_trap08); 837 #ifdef DDB 838 extern vector Xintrddbipi; 839 extern int ddb_vec; 840 #endif 841 842 static void 843 cpu_set_tss_gates(struct cpu_info *ci) 844 { 845 #if 0 846 struct segment_descriptor sd; 847 848 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 849 UVM_KMF_WIRED); 850 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 851 IDTVEC(tss_trap08)); 852 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 853 SDT_SYS386TSS, SEL_KPL, 0, 0); 854 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 855 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 856 GSEL(GTRAPTSS_SEL, SEL_KPL)); 857 #endif 858 859 #if defined(DDB) && defined(MULTIPROCESSOR) 860 /* 861 * Set up separate handler for the DDB IPI, so that it doesn't 862 * stomp on a possibly corrupted stack. 863 * 864 * XXX overwriting the gate set in db_machine_init. 865 * Should rearrange the code so that it's set only once. 866 */ 867 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 868 UVM_KMF_WIRED); 869 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 870 Xintrddbipi); 871 872 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 873 SDT_SYS386TSS, SEL_KPL, 0, 0); 874 ci->ci_gdt[GIPITSS_SEL].sd = sd; 875 876 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 877 GSEL(GIPITSS_SEL, SEL_KPL)); 878 #endif 879 } 880 #else 881 static void 882 cpu_set_tss_gates(struct cpu_info *ci) 883 { 884 885 } 886 #endif /* i386 */ 887 888 int 889 mp_cpu_start(struct cpu_info *ci, paddr_t target) 890 { 891 #if 0 892 #if NLAPIC > 0 893 int error; 894 #endif 895 unsigned short dwordptr[2]; 896 897 /* 898 * Bootstrap code must be addressable in real mode 899 * and it must be page aligned. 900 */ 901 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 902 903 /* 904 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 905 */ 906 907 outb(IO_RTC, NVRAM_RESET); 908 outb(IO_RTC+1, NVRAM_RESET_JUMP); 909 910 /* 911 * "and the warm reset vector (DWORD based at 40:67) to point 912 * to the AP startup code ..." 913 */ 914 915 dwordptr[0] = 0; 916 dwordptr[1] = target >> 4; 917 918 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 919 memcpy ((uint8_t *) 0x467, dwordptr, 4); 920 pmap_kremove (0, PAGE_SIZE); 921 922 #if NLAPIC > 0 923 /* 924 * ... prior to executing the following sequence:" 925 */ 926 927 if (ci->ci_flags & CPUF_AP) { 928 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 929 return error; 930 931 delay(10000); 932 933 if (cpu_feature & CPUID_APIC) { 934 error = x86_ipi_init(ci->ci_apicid); 935 if (error != 0) { 936 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 937 __func__); 938 return error; 939 } 940 941 delay(10000); 942 943 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 944 LAPIC_DLMODE_STARTUP); 945 if (error != 0) { 946 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 947 __func__); 948 return error; 949 } 950 delay(200); 951 952 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 953 LAPIC_DLMODE_STARTUP); 954 if (error != 0) { 955 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 956 __func__); 957 return error; 958 } 959 delay(200); 960 } 961 } 962 #endif 963 #endif /* 0 */ 964 return 0; 965 } 966 967 void 968 mp_cpu_start_cleanup(struct cpu_info *ci) 969 { 970 #if 0 971 /* 972 * Ensure the NVRAM reset byte contains something vaguely sane. 973 */ 974 975 outb(IO_RTC, NVRAM_RESET); 976 outb(IO_RTC+1, NVRAM_RESET_RST); 977 #endif 978 } 979 980 #ifdef __x86_64__ 981 982 void 983 cpu_init_msrs(struct cpu_info *ci, bool full) 984 { 985 if (full) { 986 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 987 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 988 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 989 } 990 } 991 #endif /* __x86_64__ */ 992 993 void 994 cpu_offline_md(void) 995 { 996 int s; 997 998 s = splhigh(); 999 #ifdef __i386__ 1000 npxsave_cpu(true); 1001 #else 1002 fpusave_cpu(true); 1003 #endif 1004 splx(s); 1005 } 1006 1007 #if 0 1008 /* XXX joerg restructure and restart CPUs individually */ 1009 static bool 1010 cpu_suspend(device_t dv PMF_FN_ARGS) 1011 { 1012 struct cpu_softc *sc = device_private(dv); 1013 struct cpu_info *ci = sc->sc_info; 1014 int err; 1015 1016 if (ci->ci_flags & CPUF_PRIMARY) 1017 return true; 1018 if (ci->ci_data.cpu_idlelwp == NULL) 1019 return true; 1020 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1021 return true; 1022 1023 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1024 1025 if (sc->sc_wasonline) { 1026 mutex_enter(&cpu_lock); 1027 err = cpu_setonline(ci, false); 1028 mutex_exit(&cpu_lock); 1029 1030 if (err) 1031 return false; 1032 } 1033 1034 return true; 1035 } 1036 1037 static bool 1038 cpu_resume(device_t dv PMF_FN_ARGS) 1039 { 1040 struct cpu_softc *sc = device_private(dv); 1041 struct cpu_info *ci = sc->sc_info; 1042 int err = 0; 1043 1044 if (ci->ci_flags & CPUF_PRIMARY) 1045 return true; 1046 if (ci->ci_data.cpu_idlelwp == NULL) 1047 return true; 1048 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1049 return true; 1050 1051 if (sc->sc_wasonline) { 1052 mutex_enter(&cpu_lock); 1053 err = cpu_setonline(ci, true); 1054 mutex_exit(&cpu_lock); 1055 } 1056 1057 return err == 0; 1058 } 1059 #endif 1060 1061 void 1062 cpu_get_tsc_freq(struct cpu_info *ci) 1063 { 1064 #ifdef XEN3 1065 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1066 delay(1000000); 1067 uint64_t freq = 1000000000ULL << 32; 1068 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1069 if ( tinfo->tsc_shift < 0 ) 1070 freq = freq << -tinfo->tsc_shift; 1071 else 1072 freq = freq >> tinfo->tsc_shift; 1073 ci->ci_tsc_freq = freq; 1074 #else 1075 /* Xen2 */ 1076 /* XXX this needs to read the shared_info of the CPU being probed.. */ 1077 ci->ci_tsc_freq = HYPERVISOR_shared_info->cpu_freq; 1078 #endif /* XEN3 */ 1079 } 1080
Indexes created Tue Sep 23 07:09:52 GMT 2025