cpu.c revision 1.18
1 /* $NetBSD: cpu.c,v 1.18 2008/04/28 20:23:40 martin Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.18 2008/04/28 20:23:40 martin Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #include <machine/mpbiosvar.h> 95 #include <machine/pcb.h> 96 #include <machine/specialreg.h> 97 #include <machine/segments.h> 98 #include <machine/gdt.h> 99 #include <machine/mtrr.h> 100 #include <machine/pio.h> 101 102 #ifdef XEN3 103 #include <xen/vcpuvar.h> 104 #endif 105 106 #if NLAPIC > 0 107 #include <machine/apicvar.h> 108 #include <machine/i82489reg.h> 109 #include <machine/i82489var.h> 110 #endif 111 112 #include <dev/ic/mc146818reg.h> 113 #include <dev/isa/isareg.h> 114 115 int cpu_match(device_t, cfdata_t, void *); 116 void cpu_attach(device_t, device_t, void *); 117 #ifdef XEN3 118 int vcpu_match(device_t, cfdata_t, void *); 119 void vcpu_attach(device_t, device_t, void *); 120 #endif 121 void cpu_attach_common(device_t, device_t, void *); 122 void cpu_offline_md(void); 123 124 struct cpu_softc { 125 device_t sc_dev; /* device tree glue */ 126 struct cpu_info *sc_info; /* pointer to CPU info */ 127 }; 128 129 int mp_cpu_start(struct cpu_info *, paddr_t); 130 void mp_cpu_start_cleanup(struct cpu_info *); 131 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 132 mp_cpu_start_cleanup }; 133 134 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 135 cpu_match, cpu_attach, NULL, NULL); 136 #ifdef XEN3 137 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 138 vcpu_match, vcpu_attach, NULL, NULL); 139 #endif 140 141 /* 142 * Statically-allocated CPU info for the primary CPU (or the only 143 * CPU, on uniprocessors). The CPU info list is initialized to 144 * point at it. 145 */ 146 #ifdef TRAPLOG 147 #include <machine/tlog.h> 148 struct tlog tlog_primary; 149 #endif 150 struct cpu_info cpu_info_primary = { 151 .ci_dev = 0, 152 .ci_self = &cpu_info_primary, 153 .ci_idepth = -1, 154 .ci_curlwp = &lwp0, 155 #ifdef TRAPLOG 156 .ci_tlog = &tlog_primary, 157 #endif 158 159 }; 160 struct cpu_info phycpu_info_primary = { 161 .ci_dev = 0, 162 .ci_self = &phycpu_info_primary, 163 }; 164 165 struct cpu_info *cpu_info_list = &cpu_info_primary; 166 167 static void cpu_set_tss_gates(struct cpu_info *ci); 168 169 uint32_t cpus_attached = 0; 170 uint32_t cpus_running = 0; 171 172 bool x86_mp_online; 173 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 174 175 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 176 177 #ifdef MULTIPROCESSOR 178 /* 179 * Array of CPU info structures. Must be statically-allocated because 180 * curproc, etc. are used early. 181 */ 182 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 183 184 void cpu_hatch(void *); 185 static void cpu_boot_secondary(struct cpu_info *ci); 186 static void cpu_start_secondary(struct cpu_info *ci); 187 static void cpu_copy_trampoline(void); 188 189 /* 190 * Runs once per boot once multiprocessor goo has been detected and 191 * the local APIC on the boot processor has been mapped. 192 * 193 * Called from lapic_boot_init() (from mpbios_scan()). 194 */ 195 void 196 cpu_init_first(void) 197 { 198 int cpunum = lapic_cpu_number(); 199 200 if (cpunum != 0) { 201 cpu_info[0] = NULL; 202 cpu_info[cpunum] = &cpu_info_primary; 203 } 204 205 cpu_copy_trampoline(); 206 } 207 #endif 208 209 int 210 cpu_match(device_t parent, cfdata_t match, void *aux) 211 { 212 213 return 1; 214 } 215 216 void 217 cpu_attach(device_t parent, device_t self, void *aux) 218 { 219 #ifdef XEN3 220 struct cpu_softc *sc = device_private(self); 221 struct cpu_attach_args *caa = aux; 222 struct cpu_info *ci; 223 int cpunum = caa->cpu_number; 224 225 sc->sc_dev = self; 226 227 /* 228 * If we're an Application Processor, allocate a cpu_info 229 * structure, otherwise use the primary's. 230 */ 231 if (caa->cpu_role == CPU_ROLE_AP) { 232 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 233 if (phycpu_info[cpunum] != NULL) 234 panic("cpu at apic id %d already attached?", cpunum); 235 phycpu_info[cpunum] = ci; 236 } else { 237 ci = &phycpu_info_primary; 238 if (cpunum != 0) { 239 phycpu_info[0] = NULL; 240 phycpu_info[cpunum] = ci; 241 } 242 } 243 244 ci->ci_self = ci; 245 sc->sc_info = ci; 246 247 ci->ci_dev = self; 248 ci->ci_apicid = caa->cpu_number; 249 ci->ci_cpuid = ci->ci_apicid; 250 ci->ci_vcpu = NULL; 251 252 printf(": "); 253 switch (caa->cpu_role) { 254 case CPU_ROLE_SP: 255 printf("(uniprocessor)\n"); 256 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 257 break; 258 259 case CPU_ROLE_BP: 260 printf("(boot processor)\n"); 261 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 262 break; 263 264 case CPU_ROLE_AP: 265 /* 266 * report on an AP 267 */ 268 printf("(application processor)\n"); 269 break; 270 271 default: 272 panic("unknown processor type??\n"); 273 } 274 return; 275 #else 276 cpu_attach_common(parent, self, aux); 277 #endif 278 } 279 280 #ifdef XEN3 281 int 282 vcpu_match(device_t parent, cfdata_t match, void *aux) 283 { 284 struct vcpu_attach_args *vcaa = aux; 285 286 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 287 return 1; 288 return 0; 289 } 290 291 void 292 vcpu_attach(device_t parent, device_t self, void *aux) 293 { 294 struct vcpu_attach_args *vcaa = aux; 295 296 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 297 } 298 #endif 299 300 static void 301 cpu_vm_init(struct cpu_info *ci) 302 { 303 int ncolors = 2, i; 304 305 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 306 struct x86_cache_info *cai; 307 int tcolors; 308 309 cai = &ci->ci_cinfo[i]; 310 311 tcolors = atop(cai->cai_totalsize); 312 switch(cai->cai_associativity) { 313 case 0xff: 314 tcolors = 1; /* fully associative */ 315 break; 316 case 0: 317 case 1: 318 break; 319 default: 320 tcolors /= cai->cai_associativity; 321 } 322 ncolors = max(ncolors, tcolors); 323 } 324 325 /* 326 * Knowing the size of the largest cache on this CPU, re-color 327 * our pages. 328 */ 329 if (ncolors <= uvmexp.ncolors) 330 return; 331 printf("%s: %d page colors\n", device_xname(ci->ci_dev), ncolors); 332 uvm_page_recolor(ncolors); 333 } 334 335 void 336 cpu_attach_common(device_t parent, device_t self, void *aux) 337 { 338 struct cpu_softc *sc = device_private(self); 339 struct cpu_attach_args *caa = aux; 340 struct cpu_info *ci; 341 uintptr_t ptr; 342 int cpunum = caa->cpu_number; 343 344 sc->sc_dev = self; 345 346 /* 347 * If we're an Application Processor, allocate a cpu_info 348 * structure, otherwise use the primary's. 349 */ 350 if (caa->cpu_role == CPU_ROLE_AP) { 351 if (cpunum >= X86_MAXPROCS) { 352 aprint_error(": apic id %d ignored, " 353 "please increase X86_MAXPROCS\n", cpunum); 354 } 355 356 aprint_naive(": Application Processor\n"); 357 ptr = (uintptr_t)malloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 358 M_DEVBUF, M_WAITOK); 359 ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) & 360 ~(CACHE_LINE_SIZE - 1)); 361 memset(ci, 0, sizeof(*ci)); 362 #if defined(MULTIPROCESSOR) 363 if (cpu_info[cpunum] != NULL) 364 panic("cpu at apic id %d already attached?", cpunum); 365 cpu_info[cpunum] = ci; 366 #endif 367 #ifdef TRAPLOG 368 ci->ci_tlog_base = malloc(sizeof(struct tlog), 369 M_DEVBUF, M_WAITOK); 370 #endif 371 } else { 372 aprint_naive(": %s Processor\n", 373 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 374 ci = &cpu_info_primary; 375 #if defined(MULTIPROCESSOR) 376 if (cpunum != lapic_cpu_number()) { 377 panic("%s: running CPU is at apic %d" 378 " instead of at expected %d", 379 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 380 } 381 #endif 382 } 383 384 ci->ci_self = ci; 385 sc->sc_info = ci; 386 387 ci->ci_dev = self; 388 ci->ci_apicid = cpunum; 389 390 KASSERT(HYPERVISOR_shared_info != NULL); 391 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 392 393 #ifdef MULTIPROCESSOR 394 ci->ci_cpuid = ci->ci_apicid; 395 #else 396 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 397 #endif 398 ci->ci_cpumask = (1 << ci->ci_cpuid); 399 ci->ci_func = caa->cpu_func; 400 401 if (caa->cpu_role == CPU_ROLE_AP) { 402 #if defined(MULTIPROCESSOR) 403 int error; 404 405 error = mi_cpu_attach(ci); 406 if (error != 0) { 407 aprint_normal("\n"); 408 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 409 error); 410 return; 411 } 412 #endif 413 } else { 414 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 415 } 416 417 pmap_reference(pmap_kernel()); 418 ci->ci_pmap = pmap_kernel(); 419 ci->ci_tlbstate = TLBSTATE_STALE; 420 421 /* further PCB init done later. */ 422 423 switch (caa->cpu_role) { 424 case CPU_ROLE_SP: 425 aprint_normal(": (uniprocessor)\n"); 426 atomic_or_32(&ci->ci_flags, 427 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 428 cpu_intr_init(ci); 429 identifycpu(ci); 430 cpu_init(ci); 431 cpu_set_tss_gates(ci); 432 pmap_cpu_init_late(ci); 433 #if 0 434 x86_errata(); 435 #endif 436 break; 437 438 case CPU_ROLE_BP: 439 aprint_normal("apid %d (boot processor)\n", caa->cpu_number); 440 atomic_or_32(&ci->ci_flags, 441 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 442 cpu_intr_init(ci); 443 identifycpu(ci); 444 cpu_init(ci); 445 cpu_set_tss_gates(ci); 446 pmap_cpu_init_late(ci); 447 #if NLAPIC > 0 448 /* 449 * Enable local apic 450 */ 451 lapic_enable(); 452 lapic_set_lvt(); 453 lapic_calibrate_timer(ci); 454 #endif 455 #if 0 456 x86_errata(); 457 #endif 458 break; 459 460 case CPU_ROLE_AP: 461 /* 462 * report on an AP 463 */ 464 aprint_normal("apid %d (application processor)\n", caa->cpu_number); 465 466 #if defined(MULTIPROCESSOR) 467 cpu_intr_init(ci); 468 gdt_alloc_cpu(ci); 469 cpu_set_tss_gates(ci); 470 pmap_cpu_init_early(ci); 471 pmap_cpu_init_late(ci); 472 cpu_start_secondary(ci); 473 if (ci->ci_flags & CPUF_PRESENT) { 474 identifycpu(ci); 475 ci->ci_next = cpu_info_list->ci_next; 476 cpu_info_list->ci_next = ci; 477 } 478 #else 479 aprint_normal_dev(sc->sc_dev, "not started\n"); 480 #endif 481 break; 482 483 default: 484 aprint_normal("\n"); 485 panic("unknown processor type??\n"); 486 } 487 cpu_vm_init(ci); 488 489 cpus_attached |= (1 << ci->ci_cpuid); 490 491 #if 0 492 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 493 aprint_error_dev(self, "couldn't establish power handler\n"); 494 #endif 495 496 #if defined(MULTIPROCESSOR) 497 if (mp_verbose) { 498 struct lwp *l = ci->ci_data.cpu_idlelwp; 499 500 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n", 501 l, 502 #ifdef i386 503 (void *)l->l_addr->u_pcb.pcb_esp 504 #else 505 (void *)l->l_addr->u_pcb.pcb_rsp 506 #endif 507 ); 508 509 } 510 #endif 511 } 512 513 /* 514 * Initialize the processor appropriately. 515 */ 516 517 void 518 cpu_init(struct cpu_info *ci) 519 { 520 /* configure the CPU if needed */ 521 if (ci->cpu_setup != NULL) 522 (*ci->cpu_setup)(ci); 523 524 /* 525 * On a P6 or above, enable global TLB caching if the 526 * hardware supports it. 527 */ 528 if (cpu_feature & CPUID_PGE) 529 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 530 531 #ifdef XXXMTRR 532 /* 533 * On a P6 or above, initialize MTRR's if the hardware supports them. 534 */ 535 if (cpu_feature & CPUID_MTRR) { 536 if ((ci->ci_flags & CPUF_AP) == 0) 537 i686_mtrr_init_first(); 538 mtrr_init_cpu(ci); 539 } 540 #endif 541 /* 542 * If we have FXSAVE/FXRESTOR, use them. 543 */ 544 if (cpu_feature & CPUID_FXSR) { 545 lcr4(rcr4() | CR4_OSFXSR); 546 547 /* 548 * If we have SSE/SSE2, enable XMM exceptions. 549 */ 550 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 551 lcr4(rcr4() | CR4_OSXMMEXCPT); 552 } 553 554 #ifdef MULTIPROCESSOR 555 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 556 atomic_or_32(&cpus_running, ci->ci_cpumask); 557 #endif 558 } 559 560 561 #ifdef MULTIPROCESSOR 562 void 563 cpu_boot_secondary_processors(void) 564 { 565 struct cpu_info *ci; 566 u_long i; 567 568 for (i = 0; i < X86_MAXPROCS; i++) { 569 ci = cpu_info[i]; 570 if (ci == NULL) 571 continue; 572 if (ci->ci_data.cpu_idlelwp == NULL) 573 continue; 574 if ((ci->ci_flags & CPUF_PRESENT) == 0) 575 continue; 576 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 577 continue; 578 cpu_boot_secondary(ci); 579 } 580 581 x86_mp_online = true; 582 } 583 584 static void 585 cpu_init_idle_lwp(struct cpu_info *ci) 586 { 587 struct lwp *l = ci->ci_data.cpu_idlelwp; 588 struct pcb *pcb = &l->l_addr->u_pcb; 589 590 pcb->pcb_cr0 = rcr0(); 591 } 592 593 void 594 cpu_init_idle_lwps(void) 595 { 596 struct cpu_info *ci; 597 u_long i; 598 599 for (i = 0; i < X86_MAXPROCS; i++) { 600 ci = cpu_info[i]; 601 if (ci == NULL) 602 continue; 603 if (ci->ci_data.cpu_idlelwp == NULL) 604 continue; 605 if ((ci->ci_flags & CPUF_PRESENT) == 0) 606 continue; 607 cpu_init_idle_lwp(ci); 608 } 609 } 610 611 void 612 cpu_start_secondary(struct cpu_info *ci) 613 { 614 int i; 615 struct pmap *kpm = pmap_kernel(); 616 extern uint32_t mp_pdirpa; 617 618 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 619 620 atomic_or_32(&ci->ci_flags, CPUF_AP); 621 622 aprint_debug_dev(ci->ci_dev, "starting\n"); 623 624 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 625 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 626 return; 627 628 /* 629 * wait for it to become ready 630 */ 631 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 632 #ifdef MPDEBUG 633 extern int cpu_trace[3]; 634 static int otrace[3]; 635 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 636 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 637 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 638 memcpy(otrace, cpu_trace, sizeof(otrace)); 639 } 640 #endif 641 delay(10); 642 } 643 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 644 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 645 #if defined(MPDEBUG) && defined(DDB) 646 printf("dropping into debugger; continue from here to resume boot\n"); 647 Debugger(); 648 #endif 649 } 650 651 CPU_START_CLEANUP(ci); 652 } 653 654 void 655 cpu_boot_secondary(struct cpu_info *ci) 656 { 657 int i; 658 659 atomic_or_32(&ci->ci_flags, CPUF_GO); 660 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 661 delay(10); 662 } 663 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 664 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 665 #if defined(MPDEBUG) && defined(DDB) 666 printf("dropping into debugger; continue from here to resume boot\n"); 667 Debugger(); 668 #endif 669 } 670 } 671 672 /* 673 * The CPU ends up here when its ready to run 674 * This is called from code in mptramp.s; at this point, we are running 675 * in the idle pcb/idle stack of the new CPU. When this function returns, 676 * this processor will enter the idle loop and start looking for work. 677 * 678 * XXX should share some of this with init386 in machdep.c 679 */ 680 void 681 cpu_hatch(void *v) 682 { 683 struct cpu_info *ci = (struct cpu_info *)v; 684 int s, i; 685 uint32_t blacklist_features; 686 687 #ifdef __x86_64__ 688 cpu_init_msrs(ci, true); 689 #endif 690 691 cpu_probe_features(ci); 692 cpu_feature &= ci->ci_feature_flags; 693 cpu_feature2 &= ci->ci_feature2_flags; 694 695 /* not on Xen... */ 696 blacklist_features = ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); /* XXX add CPUID_SVM */ 697 698 cpu_feature &= blacklist_features; 699 700 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 701 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 702 while ((ci->ci_flags & CPUF_GO) == 0) { 703 /* Don't use delay, boot CPU may be patching the text. */ 704 for (i = 10000; i != 0; i--) 705 x86_pause(); 706 } 707 708 /* Because the text may have been patched in x86_patch(). */ 709 wbinvd(); 710 x86_flush(); 711 712 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 713 714 lcr3(pmap_kernel()->pm_pdirpa); 715 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 716 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 717 cpu_init_idt(); 718 gdt_init_cpu(ci); 719 lapic_enable(); 720 lapic_set_lvt(); 721 lapic_initclocks(); 722 723 #ifdef i386 724 npxinit(ci); 725 #else 726 fpuinit(ci); 727 #endif 728 729 lldt(GSEL(GLDT_SEL, SEL_KPL)); 730 ltr(ci->ci_tss_sel); 731 732 cpu_init(ci); 733 cpu_get_tsc_freq(ci); 734 735 s = splhigh(); 736 #ifdef i386 737 lapic_tpr = 0; 738 #else 739 lcr8(0); 740 #endif 741 x86_enable_intr(); 742 splx(s); 743 #if 0 744 x86_errata(); 745 #endif 746 747 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 748 (long)ci->ci_cpuid); 749 } 750 751 #if defined(DDB) 752 753 #include <ddb/db_output.h> 754 #include <machine/db_machdep.h> 755 756 /* 757 * Dump CPU information from ddb. 758 */ 759 void 760 cpu_debug_dump(void) 761 { 762 struct cpu_info *ci; 763 CPU_INFO_ITERATOR cii; 764 765 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 766 for (CPU_INFO_FOREACH(cii, ci)) { 767 db_printf("%p %s %ld %x %x %10p %10p\n", 768 ci, 769 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 770 (long)ci->ci_cpuid, 771 ci->ci_flags, ci->ci_ipis, 772 ci->ci_curlwp, 773 ci->ci_fpcurlwp); 774 } 775 } 776 #endif 777 778 static void 779 cpu_copy_trampoline(void) 780 { 781 /* 782 * Copy boot code. 783 */ 784 extern u_char cpu_spinup_trampoline[]; 785 extern u_char cpu_spinup_trampoline_end[]; 786 787 vaddr_t mp_trampoline_vaddr; 788 789 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 790 UVM_KMF_VAONLY); 791 792 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 793 VM_PROT_READ | VM_PROT_WRITE); 794 pmap_update(pmap_kernel()); 795 memcpy((void *)mp_trampoline_vaddr, 796 cpu_spinup_trampoline, 797 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 798 799 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 800 pmap_update(pmap_kernel()); 801 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 802 } 803 804 #endif 805 806 #ifdef i386 807 #if 0 808 static void 809 tss_init(struct i386tss *tss, void *stack, void *func) 810 { 811 memset(tss, 0, sizeof *tss); 812 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 813 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 814 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 815 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 816 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 817 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 818 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 819 tss->tss_esp = (int)((char *)stack + USPACE - 16); 820 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 821 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 822 tss->__tss_eip = (int)func; 823 } 824 #endif 825 826 /* XXX */ 827 #define IDTVEC(name) __CONCAT(X, name) 828 typedef void (vector)(void); 829 extern vector IDTVEC(tss_trap08); 830 #ifdef DDB 831 extern vector Xintrddbipi; 832 extern int ddb_vec; 833 #endif 834 835 static void 836 cpu_set_tss_gates(struct cpu_info *ci) 837 { 838 #if 0 839 struct segment_descriptor sd; 840 841 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 842 UVM_KMF_WIRED); 843 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 844 IDTVEC(tss_trap08)); 845 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 846 SDT_SYS386TSS, SEL_KPL, 0, 0); 847 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 848 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 849 GSEL(GTRAPTSS_SEL, SEL_KPL)); 850 #endif 851 852 #if defined(DDB) && defined(MULTIPROCESSOR) 853 /* 854 * Set up separate handler for the DDB IPI, so that it doesn't 855 * stomp on a possibly corrupted stack. 856 * 857 * XXX overwriting the gate set in db_machine_init. 858 * Should rearrange the code so that it's set only once. 859 */ 860 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 861 UVM_KMF_WIRED); 862 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 863 Xintrddbipi); 864 865 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 866 SDT_SYS386TSS, SEL_KPL, 0, 0); 867 ci->ci_gdt[GIPITSS_SEL].sd = sd; 868 869 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 870 GSEL(GIPITSS_SEL, SEL_KPL)); 871 #endif 872 } 873 #else 874 static void 875 cpu_set_tss_gates(struct cpu_info *ci) 876 { 877 878 } 879 #endif /* i386 */ 880 881 int 882 mp_cpu_start(struct cpu_info *ci, paddr_t target) 883 { 884 #if 0 885 #if NLAPIC > 0 886 int error; 887 #endif 888 unsigned short dwordptr[2]; 889 890 /* 891 * Bootstrap code must be addressable in real mode 892 * and it must be page aligned. 893 */ 894 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 895 896 /* 897 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 898 */ 899 900 outb(IO_RTC, NVRAM_RESET); 901 outb(IO_RTC+1, NVRAM_RESET_JUMP); 902 903 /* 904 * "and the warm reset vector (DWORD based at 40:67) to point 905 * to the AP startup code ..." 906 */ 907 908 dwordptr[0] = 0; 909 dwordptr[1] = target >> 4; 910 911 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 912 memcpy ((uint8_t *) 0x467, dwordptr, 4); 913 pmap_kremove (0, PAGE_SIZE); 914 915 #if NLAPIC > 0 916 /* 917 * ... prior to executing the following sequence:" 918 */ 919 920 if (ci->ci_flags & CPUF_AP) { 921 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 922 return error; 923 924 delay(10000); 925 926 if (cpu_feature & CPUID_APIC) { 927 error = x86_ipi_init(ci->ci_apicid); 928 if (error != 0) { 929 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 930 __func__); 931 return error; 932 } 933 934 delay(10000); 935 936 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 937 LAPIC_DLMODE_STARTUP); 938 if (error != 0) { 939 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 940 __func__); 941 return error; 942 } 943 delay(200); 944 945 error = x86_ipi(target / PAGE_SIZE, ci->ci_apicid, 946 LAPIC_DLMODE_STARTUP); 947 if (error != 0) { 948 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 949 __func__); 950 return error; 951 } 952 delay(200); 953 } 954 } 955 #endif 956 #endif /* 0 */ 957 return 0; 958 } 959 960 void 961 mp_cpu_start_cleanup(struct cpu_info *ci) 962 { 963 #if 0 964 /* 965 * Ensure the NVRAM reset byte contains something vaguely sane. 966 */ 967 968 outb(IO_RTC, NVRAM_RESET); 969 outb(IO_RTC+1, NVRAM_RESET_RST); 970 #endif 971 } 972 973 #ifdef __x86_64__ 974 975 void 976 cpu_init_msrs(struct cpu_info *ci, bool full) 977 { 978 if (full) { 979 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 980 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 981 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 982 } 983 } 984 #endif /* __x86_64__ */ 985 986 void 987 cpu_offline_md(void) 988 { 989 int s; 990 991 s = splhigh(); 992 #ifdef __i386__ 993 npxsave_cpu(true); 994 #else 995 fpusave_cpu(true); 996 #endif 997 splx(s); 998 } 999 1000 #if 0 1001 /* XXX joerg restructure and restart CPUs individually */ 1002 static bool 1003 cpu_suspend(device_t dv PMF_FN_ARGS) 1004 { 1005 struct cpu_softc *sc = device_private(dv); 1006 struct cpu_info *ci = sc->sc_info; 1007 int err; 1008 1009 if (ci->ci_flags & CPUF_PRIMARY) 1010 return true; 1011 if (ci->ci_data.cpu_idlelwp == NULL) 1012 return true; 1013 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1014 return true; 1015 1016 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1017 1018 if (sc->sc_wasonline) { 1019 mutex_enter(&cpu_lock); 1020 err = cpu_setonline(ci, false); 1021 mutex_exit(&cpu_lock); 1022 1023 if (err) 1024 return false; 1025 } 1026 1027 return true; 1028 } 1029 1030 static bool 1031 cpu_resume(device_t dv PMF_FN_ARGS) 1032 { 1033 struct cpu_softc *sc = device_private(dv); 1034 struct cpu_info *ci = sc->sc_info; 1035 int err = 0; 1036 1037 if (ci->ci_flags & CPUF_PRIMARY) 1038 return true; 1039 if (ci->ci_data.cpu_idlelwp == NULL) 1040 return true; 1041 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1042 return true; 1043 1044 if (sc->sc_wasonline) { 1045 mutex_enter(&cpu_lock); 1046 err = cpu_setonline(ci, true); 1047 mutex_exit(&cpu_lock); 1048 } 1049 1050 return err == 0; 1051 } 1052 #endif 1053 1054 void 1055 cpu_get_tsc_freq(struct cpu_info *ci) 1056 { 1057 #ifdef XEN3 1058 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1059 delay(1000000); 1060 uint64_t freq = 1000000000ULL << 32; 1061 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1062 if ( tinfo->tsc_shift < 0 ) 1063 freq = freq << -tinfo->tsc_shift; 1064 else 1065 freq = freq >> tinfo->tsc_shift; 1066 ci->ci_tsc_freq = freq; 1067 #else 1068 /* Xen2 */ 1069 /* XXX this needs to read the shared_info of the CPU being probed.. */ 1070 ci->ci_tsc_freq = HYPERVISOR_shared_info->cpu_freq; 1071 #endif /* XEN3 */ 1072 } 1073
Indexes created Fri Oct 03 02:09:57 GMT 2025