cpu.c revision 1.28.4.3
1 /* $NetBSD: cpu.c,v 1.28.4.3 2010/11/22 01:43:58 riz Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.28.4.3 2010/11/22 01:43:58 riz Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/user.h> 83 #include <sys/systm.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/cpu.h> 87 #include <sys/atomic.h> 88 89 #include <uvm/uvm_extern.h> 90 91 #include <machine/cpufunc.h> 92 #include <machine/cpuvar.h> 93 #include <machine/pmap.h> 94 #include <machine/vmparam.h> 95 #include <machine/mpbiosvar.h> 96 #include <machine/pcb.h> 97 #include <machine/specialreg.h> 98 #include <machine/segments.h> 99 #include <machine/gdt.h> 100 #include <machine/mtrr.h> 101 #include <machine/pio.h> 102 103 #ifdef XEN3 104 #include <xen/vcpuvar.h> 105 #endif 106 107 #if NLAPIC > 0 108 #include <machine/apicvar.h> 109 #include <machine/i82489reg.h> 110 #include <machine/i82489var.h> 111 #endif 112 113 #include <dev/ic/mc146818reg.h> 114 #include <dev/isa/isareg.h> 115 116 #define X86_MAXPROCS 32 117 118 int cpu_match(device_t, cfdata_t, void *); 119 void cpu_attach(device_t, device_t, void *); 120 #ifdef XEN3 121 int vcpu_match(device_t, cfdata_t, void *); 122 void vcpu_attach(device_t, device_t, void *); 123 #endif 124 void cpu_attach_common(device_t, device_t, void *); 125 void cpu_offline_md(void); 126 127 struct cpu_softc { 128 device_t sc_dev; /* device tree glue */ 129 struct cpu_info *sc_info; /* pointer to CPU info */ 130 }; 131 132 int mp_cpu_start(struct cpu_info *, paddr_t); 133 void mp_cpu_start_cleanup(struct cpu_info *); 134 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 135 mp_cpu_start_cleanup }; 136 137 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 138 cpu_match, cpu_attach, NULL, NULL); 139 #ifdef XEN3 140 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 141 vcpu_match, vcpu_attach, NULL, NULL); 142 #endif 143 144 /* 145 * Statically-allocated CPU info for the primary CPU (or the only 146 * CPU, on uniprocessors). The CPU info list is initialized to 147 * point at it. 148 */ 149 #ifdef TRAPLOG 150 #include <machine/tlog.h> 151 struct tlog tlog_primary; 152 #endif 153 struct cpu_info cpu_info_primary = { 154 .ci_dev = 0, 155 .ci_self = &cpu_info_primary, 156 .ci_idepth = -1, 157 .ci_curlwp = &lwp0, 158 .ci_curldt = -1, 159 #ifdef TRAPLOG 160 .ci_tlog = &tlog_primary, 161 #endif 162 163 }; 164 struct cpu_info phycpu_info_primary = { 165 .ci_dev = 0, 166 .ci_self = &phycpu_info_primary, 167 }; 168 169 struct cpu_info *cpu_info_list = &cpu_info_primary; 170 171 static void cpu_set_tss_gates(struct cpu_info *ci); 172 173 uint32_t cpus_attached = 0; 174 uint32_t cpus_running = 0; 175 176 /* CPUID feature flags */ 177 uint32_t cpu_feature; /* %edx */ 178 uint32_t cpu_feature2; /* %ecx */ 179 uint32_t cpu_feature3; /* extended features - %edx */ 180 uint32_t cpu_feature4; /* extended features - %ecx */ 181 uint32_t cpu_feature_padlock; /* VIA PadLock feature flags */ 182 183 bool x86_mp_online; 184 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 185 186 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 187 188 #ifdef MULTIPROCESSOR 189 /* 190 * Array of CPU info structures. Must be statically-allocated because 191 * curproc, etc. are used early. 192 */ 193 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 194 195 void cpu_hatch(void *); 196 static void cpu_boot_secondary(struct cpu_info *ci); 197 static void cpu_start_secondary(struct cpu_info *ci); 198 static void cpu_copy_trampoline(void); 199 200 /* 201 * Runs once per boot once multiprocessor goo has been detected and 202 * the local APIC on the boot processor has been mapped. 203 * 204 * Called from lapic_boot_init() (from mpbios_scan()). 205 */ 206 void 207 cpu_init_first(void) 208 { 209 int cpunum = lapic_cpu_number(); 210 211 if (cpunum != 0) { 212 cpu_info[0] = NULL; 213 cpu_info[cpunum] = &cpu_info_primary; 214 } 215 216 cpu_copy_trampoline(); 217 } 218 #endif 219 220 int 221 cpu_match(device_t parent, cfdata_t match, void *aux) 222 { 223 224 return 1; 225 } 226 227 void 228 cpu_attach(device_t parent, device_t self, void *aux) 229 { 230 #ifdef XEN3 231 struct cpu_softc *sc = device_private(self); 232 struct cpu_attach_args *caa = aux; 233 struct cpu_info *ci; 234 static int nphycpu = 0; 235 236 sc->sc_dev = self; 237 238 /* 239 * If we're the first attached CPU use the primary cpu_info, 240 * otherwise allocate a new one. 241 */ 242 if (nphycpu > 0) { 243 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 244 ci->ci_curldt = -1; 245 if (phycpu_info[nphycpu] != NULL) 246 panic("cpu%d already attached?", nphycpu); 247 phycpu_info[nphycpu] = ci; 248 } else { 249 ci = &phycpu_info_primary; 250 } 251 252 ci->ci_self = ci; 253 sc->sc_info = ci; 254 255 ci->ci_dev = self; 256 ci->ci_cpuid = caa->cpu_number; 257 ci->ci_vcpu = NULL; 258 ci->ci_index = nphycpu++; 259 260 printf("\n"); 261 return; 262 #else 263 cpu_attach_common(parent, self, aux); 264 #endif 265 } 266 267 #ifdef XEN3 268 int 269 vcpu_match(device_t parent, cfdata_t match, void *aux) 270 { 271 struct vcpu_attach_args *vcaa = aux; 272 273 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 274 return 1; 275 return 0; 276 } 277 278 void 279 vcpu_attach(device_t parent, device_t self, void *aux) 280 { 281 struct vcpu_attach_args *vcaa = aux; 282 283 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 284 } 285 #endif 286 287 static void 288 cpu_vm_init(struct cpu_info *ci) 289 { 290 int ncolors = 2, i; 291 292 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 293 struct x86_cache_info *cai; 294 int tcolors; 295 296 cai = &ci->ci_cinfo[i]; 297 298 tcolors = atop(cai->cai_totalsize); 299 switch(cai->cai_associativity) { 300 case 0xff: 301 tcolors = 1; /* fully associative */ 302 break; 303 case 0: 304 case 1: 305 break; 306 default: 307 tcolors /= cai->cai_associativity; 308 } 309 ncolors = max(ncolors, tcolors); 310 } 311 312 /* 313 * Knowing the size of the largest cache on this CPU, re-color 314 * our pages. 315 */ 316 if (ncolors <= uvmexp.ncolors) 317 return; 318 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 319 uvm_page_recolor(ncolors); 320 } 321 322 void 323 cpu_attach_common(device_t parent, device_t self, void *aux) 324 { 325 struct cpu_softc *sc = device_private(self); 326 struct cpu_attach_args *caa = aux; 327 struct cpu_info *ci; 328 uintptr_t ptr; 329 int cpunum = caa->cpu_number; 330 331 sc->sc_dev = self; 332 333 /* 334 * If we're an Application Processor, allocate a cpu_info 335 * structure, otherwise use the primary's. 336 */ 337 if (caa->cpu_role == CPU_ROLE_AP) { 338 if (cpunum >= X86_MAXPROCS) { 339 aprint_error(": apic id %d ignored, " 340 "please increase X86_MAXPROCS\n", cpunum); 341 } 342 343 aprint_naive(": Application Processor\n"); 344 ptr = (uintptr_t)malloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 345 M_DEVBUF, M_WAITOK); 346 ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) & 347 ~(CACHE_LINE_SIZE - 1)); 348 memset(ci, 0, sizeof(*ci)); 349 #if defined(MULTIPROCESSOR) 350 if (cpu_info[cpunum] != NULL) 351 panic("cpu at apic id %d already attached?", cpunum); 352 cpu_info[cpunum] = ci; 353 #endif 354 #ifdef TRAPLOG 355 ci->ci_tlog_base = malloc(sizeof(struct tlog), 356 M_DEVBUF, M_WAITOK); 357 #endif 358 } else { 359 aprint_naive(": %s Processor\n", 360 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 361 ci = &cpu_info_primary; 362 #if defined(MULTIPROCESSOR) 363 if (cpunum != lapic_cpu_number()) { 364 panic("%s: running CPU is at apic %d" 365 " instead of at expected %d", 366 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 367 } 368 #endif 369 } 370 371 ci->ci_self = ci; 372 sc->sc_info = ci; 373 374 ci->ci_dev = self; 375 ci->ci_cpuid = cpunum; 376 377 KASSERT(HYPERVISOR_shared_info != NULL); 378 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 379 380 ci->ci_func = caa->cpu_func; 381 382 if (caa->cpu_role == CPU_ROLE_AP) { 383 #if defined(MULTIPROCESSOR) 384 int error; 385 386 error = mi_cpu_attach(ci); 387 if (error != 0) { 388 aprint_normal("\n"); 389 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 390 error); 391 return; 392 } 393 #endif 394 } else { 395 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 396 } 397 398 ci->ci_cpumask = (1 << cpu_index(ci)); 399 pmap_reference(pmap_kernel()); 400 ci->ci_pmap = pmap_kernel(); 401 ci->ci_tlbstate = TLBSTATE_STALE; 402 403 /* further PCB init done later. */ 404 405 switch (caa->cpu_role) { 406 case CPU_ROLE_SP: 407 atomic_or_32(&ci->ci_flags, 408 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 409 cpu_intr_init(ci); 410 cpu_get_tsc_freq(ci); 411 cpu_identify(ci); 412 cpu_init(ci); 413 cpu_set_tss_gates(ci); 414 pmap_cpu_init_late(ci); 415 x86_cpu_idle_init(); 416 #if 0 417 x86_errata(); 418 #endif 419 break; 420 421 case CPU_ROLE_BP: 422 atomic_or_32(&ci->ci_flags, 423 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 424 cpu_intr_init(ci); 425 cpu_get_tsc_freq(ci); 426 cpu_identify(ci); 427 cpu_init(ci); 428 cpu_set_tss_gates(ci); 429 pmap_cpu_init_late(ci); 430 x86_cpu_idle_init(); 431 #if NLAPIC > 0 432 /* 433 * Enable local apic 434 */ 435 lapic_enable(); 436 lapic_set_lvt(); 437 lapic_calibrate_timer(ci); 438 #endif 439 #if 0 440 x86_errata(); 441 #endif 442 break; 443 444 case CPU_ROLE_AP: 445 /* 446 * report on an AP 447 */ 448 449 #if defined(MULTIPROCESSOR) 450 cpu_intr_init(ci); 451 gdt_alloc_cpu(ci); 452 cpu_set_tss_gates(ci); 453 pmap_cpu_init_early(ci); 454 pmap_cpu_init_late(ci); 455 cpu_start_secondary(ci); 456 if (ci->ci_flags & CPUF_PRESENT) { 457 identifycpu(ci); 458 ci->ci_next = cpu_info_list->ci_next; 459 cpu_info_list->ci_next = ci; 460 } 461 #else 462 aprint_normal_dev(sc->sc_dev, "not started\n"); 463 #endif 464 break; 465 466 default: 467 aprint_normal("\n"); 468 panic("unknown processor type??\n"); 469 } 470 cpu_vm_init(ci); 471 472 cpus_attached |= (1 << ci->ci_cpuid); 473 474 #if 0 475 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 476 aprint_error_dev(self, "couldn't establish power handler\n"); 477 #endif 478 479 #if defined(MULTIPROCESSOR) 480 if (mp_verbose) { 481 struct lwp *l = ci->ci_data.cpu_idlelwp; 482 483 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n", 484 l, 485 #ifdef i386 486 (void *)l->l_addr->u_pcb.pcb_esp 487 #else 488 (void *)l->l_addr->u_pcb.pcb_rsp 489 #endif 490 ); 491 492 } 493 #endif 494 } 495 496 /* 497 * Initialize the processor appropriately. 498 */ 499 500 void 501 cpu_init(struct cpu_info *ci) 502 { 503 504 /* 505 * On a P6 or above, enable global TLB caching if the 506 * hardware supports it. 507 */ 508 if (cpu_feature & CPUID_PGE) 509 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 510 511 #ifdef XXXMTRR 512 /* 513 * On a P6 or above, initialize MTRR's if the hardware supports them. 514 */ 515 if (cpu_feature & CPUID_MTRR) { 516 if ((ci->ci_flags & CPUF_AP) == 0) 517 i686_mtrr_init_first(); 518 mtrr_init_cpu(ci); 519 } 520 #endif 521 /* 522 * If we have FXSAVE/FXRESTOR, use them. 523 */ 524 if (cpu_feature & CPUID_FXSR) { 525 lcr4(rcr4() | CR4_OSFXSR); 526 527 /* 528 * If we have SSE/SSE2, enable XMM exceptions. 529 */ 530 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 531 lcr4(rcr4() | CR4_OSXMMEXCPT); 532 } 533 534 #ifdef MULTIPROCESSOR 535 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 536 atomic_or_32(&cpus_running, ci->ci_cpumask); 537 #endif 538 } 539 540 541 #ifdef MULTIPROCESSOR 542 void 543 cpu_boot_secondary_processors(void) 544 { 545 struct cpu_info *ci; 546 u_long i; 547 548 for (i = 0; i < X86_MAXPROCS; i++) { 549 ci = cpu_info[i]; 550 if (ci == NULL) 551 continue; 552 if (ci->ci_data.cpu_idlelwp == NULL) 553 continue; 554 if ((ci->ci_flags & CPUF_PRESENT) == 0) 555 continue; 556 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 557 continue; 558 cpu_boot_secondary(ci); 559 } 560 561 x86_mp_online = true; 562 } 563 564 static void 565 cpu_init_idle_lwp(struct cpu_info *ci) 566 { 567 struct lwp *l = ci->ci_data.cpu_idlelwp; 568 struct pcb *pcb = &l->l_addr->u_pcb; 569 570 pcb->pcb_cr0 = rcr0(); 571 } 572 573 void 574 cpu_init_idle_lwps(void) 575 { 576 struct cpu_info *ci; 577 u_long i; 578 579 for (i = 0; i < X86_MAXPROCS; i++) { 580 ci = cpu_info[i]; 581 if (ci == NULL) 582 continue; 583 if (ci->ci_data.cpu_idlelwp == NULL) 584 continue; 585 if ((ci->ci_flags & CPUF_PRESENT) == 0) 586 continue; 587 cpu_init_idle_lwp(ci); 588 } 589 } 590 591 void 592 cpu_start_secondary(struct cpu_info *ci) 593 { 594 int i; 595 struct pmap *kpm = pmap_kernel(); 596 extern uint32_t mp_pdirpa; 597 598 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 599 600 atomic_or_32(&ci->ci_flags, CPUF_AP); 601 602 aprint_debug_dev(ci->ci_dev, "starting\n"); 603 604 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 605 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 606 return; 607 608 /* 609 * wait for it to become ready 610 */ 611 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 612 #ifdef MPDEBUG 613 extern int cpu_trace[3]; 614 static int otrace[3]; 615 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 616 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 617 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 618 memcpy(otrace, cpu_trace, sizeof(otrace)); 619 } 620 #endif 621 delay(10); 622 } 623 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 624 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 625 #if defined(MPDEBUG) && defined(DDB) 626 printf("dropping into debugger; continue from here to resume boot\n"); 627 Debugger(); 628 #endif 629 } 630 631 CPU_START_CLEANUP(ci); 632 } 633 634 void 635 cpu_boot_secondary(struct cpu_info *ci) 636 { 637 int i; 638 639 atomic_or_32(&ci->ci_flags, CPUF_GO); 640 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 641 delay(10); 642 } 643 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 644 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 645 #if defined(MPDEBUG) && defined(DDB) 646 printf("dropping into debugger; continue from here to resume boot\n"); 647 Debugger(); 648 #endif 649 } 650 } 651 652 /* 653 * The CPU ends up here when its ready to run 654 * This is called from code in mptramp.s; at this point, we are running 655 * in the idle pcb/idle stack of the new CPU. When this function returns, 656 * this processor will enter the idle loop and start looking for work. 657 * 658 * XXX should share some of this with init386 in machdep.c 659 */ 660 void 661 cpu_hatch(void *v) 662 { 663 struct cpu_info *ci = (struct cpu_info *)v; 664 int s, i; 665 666 #ifdef __x86_64__ 667 cpu_init_msrs(ci, true); 668 #endif 669 670 cpu_probe(ci); 671 672 /* not on Xen... */ 673 cpu_feature &= ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR); /* XXX add CPUID_SVM */ 674 cpu_feature3 &= ~CPUID_NOX; 675 676 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 677 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 678 while ((ci->ci_flags & CPUF_GO) == 0) { 679 /* Don't use delay, boot CPU may be patching the text. */ 680 for (i = 10000; i != 0; i--) 681 x86_pause(); 682 } 683 684 /* Because the text may have been patched in x86_patch(). */ 685 wbinvd(); 686 x86_flush(); 687 688 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 689 690 lcr3(pmap_kernel()->pm_pdirpa); 691 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 692 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 693 cpu_init_idt(); 694 gdt_init_cpu(ci); 695 lapic_enable(); 696 lapic_set_lvt(); 697 lapic_initclocks(); 698 699 #ifdef i386 700 npxinit(ci); 701 #else 702 fpuinit(ci); 703 #endif 704 705 lldt(GSEL(GLDT_SEL, SEL_KPL)); 706 ltr(ci->ci_tss_sel); 707 708 cpu_init(ci); 709 cpu_get_tsc_freq(ci); 710 711 s = splhigh(); 712 #ifdef i386 713 lapic_tpr = 0; 714 #else 715 lcr8(0); 716 #endif 717 x86_enable_intr(); 718 splx(s); 719 #if 0 720 x86_errata(); 721 #endif 722 723 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 724 (long)ci->ci_cpuid); 725 } 726 727 #if defined(DDB) 728 729 #include <ddb/db_output.h> 730 #include <machine/db_machdep.h> 731 732 /* 733 * Dump CPU information from ddb. 734 */ 735 void 736 cpu_debug_dump(void) 737 { 738 struct cpu_info *ci; 739 CPU_INFO_ITERATOR cii; 740 741 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 742 for (CPU_INFO_FOREACH(cii, ci)) { 743 db_printf("%p %s %ld %x %x %10p %10p\n", 744 ci, 745 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 746 (long)ci->ci_cpuid, 747 ci->ci_flags, ci->ci_ipis, 748 ci->ci_curlwp, 749 ci->ci_fpcurlwp); 750 } 751 } 752 #endif 753 754 static void 755 cpu_copy_trampoline(void) 756 { 757 /* 758 * Copy boot code. 759 */ 760 extern u_char cpu_spinup_trampoline[]; 761 extern u_char cpu_spinup_trampoline_end[]; 762 763 vaddr_t mp_trampoline_vaddr; 764 765 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 766 UVM_KMF_VAONLY); 767 768 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 769 VM_PROT_READ | VM_PROT_WRITE); 770 pmap_update(pmap_kernel()); 771 memcpy((void *)mp_trampoline_vaddr, 772 cpu_spinup_trampoline, 773 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 774 775 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 776 pmap_update(pmap_kernel()); 777 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 778 } 779 780 #endif 781 782 #ifdef i386 783 #if 0 784 static void 785 tss_init(struct i386tss *tss, void *stack, void *func) 786 { 787 memset(tss, 0, sizeof *tss); 788 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 789 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 790 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 791 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 792 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 793 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 794 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 795 tss->tss_esp = (int)((char *)stack + USPACE - 16); 796 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 797 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 798 tss->__tss_eip = (int)func; 799 } 800 #endif 801 802 /* XXX */ 803 #define IDTVEC(name) __CONCAT(X, name) 804 typedef void (vector)(void); 805 extern vector IDTVEC(tss_trap08); 806 #ifdef DDB 807 extern vector Xintrddbipi; 808 extern int ddb_vec; 809 #endif 810 811 static void 812 cpu_set_tss_gates(struct cpu_info *ci) 813 { 814 #if 0 815 struct segment_descriptor sd; 816 817 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 818 UVM_KMF_WIRED); 819 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 820 IDTVEC(tss_trap08)); 821 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 822 SDT_SYS386TSS, SEL_KPL, 0, 0); 823 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 824 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 825 GSEL(GTRAPTSS_SEL, SEL_KPL)); 826 #endif 827 828 #if defined(DDB) && defined(MULTIPROCESSOR) 829 /* 830 * Set up separate handler for the DDB IPI, so that it doesn't 831 * stomp on a possibly corrupted stack. 832 * 833 * XXX overwriting the gate set in db_machine_init. 834 * Should rearrange the code so that it's set only once. 835 */ 836 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 837 UVM_KMF_WIRED); 838 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 839 Xintrddbipi); 840 841 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 842 SDT_SYS386TSS, SEL_KPL, 0, 0); 843 ci->ci_gdt[GIPITSS_SEL].sd = sd; 844 845 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 846 GSEL(GIPITSS_SEL, SEL_KPL)); 847 #endif 848 } 849 #else 850 static void 851 cpu_set_tss_gates(struct cpu_info *ci) 852 { 853 854 } 855 #endif /* i386 */ 856 857 int 858 mp_cpu_start(struct cpu_info *ci, paddr_t target) 859 { 860 #if 0 861 #if NLAPIC > 0 862 int error; 863 #endif 864 unsigned short dwordptr[2]; 865 866 /* 867 * Bootstrap code must be addressable in real mode 868 * and it must be page aligned. 869 */ 870 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 871 872 /* 873 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 874 */ 875 876 outb(IO_RTC, NVRAM_RESET); 877 outb(IO_RTC+1, NVRAM_RESET_JUMP); 878 879 /* 880 * "and the warm reset vector (DWORD based at 40:67) to point 881 * to the AP startup code ..." 882 */ 883 884 dwordptr[0] = 0; 885 dwordptr[1] = target >> 4; 886 887 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 888 memcpy ((uint8_t *) 0x467, dwordptr, 4); 889 pmap_kremove (0, PAGE_SIZE); 890 891 #if NLAPIC > 0 892 /* 893 * ... prior to executing the following sequence:" 894 */ 895 896 if (ci->ci_flags & CPUF_AP) { 897 if ((error = x86_ipi_init(ci->ci_cpuid)) != 0) 898 return error; 899 900 delay(10000); 901 902 if (cpu_feature & CPUID_APIC) { 903 error = x86_ipi_init(ci->ci_cpuid); 904 if (error != 0) { 905 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 906 __func__); 907 return error; 908 } 909 910 delay(10000); 911 912 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 913 LAPIC_DLMODE_STARTUP); 914 if (error != 0) { 915 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 916 __func__); 917 return error; 918 } 919 delay(200); 920 921 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 922 LAPIC_DLMODE_STARTUP); 923 if (error != 0) { 924 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 925 __func__); 926 return error; 927 } 928 delay(200); 929 } 930 } 931 #endif 932 #endif /* 0 */ 933 return 0; 934 } 935 936 void 937 mp_cpu_start_cleanup(struct cpu_info *ci) 938 { 939 #if 0 940 /* 941 * Ensure the NVRAM reset byte contains something vaguely sane. 942 */ 943 944 outb(IO_RTC, NVRAM_RESET); 945 outb(IO_RTC+1, NVRAM_RESET_RST); 946 #endif 947 } 948 949 #ifdef __x86_64__ 950 951 void 952 cpu_init_msrs(struct cpu_info *ci, bool full) 953 { 954 if (full) { 955 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 956 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 957 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 958 } 959 } 960 #endif /* __x86_64__ */ 961 962 void 963 cpu_offline_md(void) 964 { 965 int s; 966 967 s = splhigh(); 968 #ifdef __i386__ 969 npxsave_cpu(true); 970 #else 971 fpusave_cpu(true); 972 #endif 973 splx(s); 974 } 975 976 #if 0 977 /* XXX joerg restructure and restart CPUs individually */ 978 static bool 979 cpu_suspend(device_t dv PMF_FN_ARGS) 980 { 981 struct cpu_softc *sc = device_private(dv); 982 struct cpu_info *ci = sc->sc_info; 983 int err; 984 985 if (ci->ci_flags & CPUF_PRIMARY) 986 return true; 987 if (ci->ci_data.cpu_idlelwp == NULL) 988 return true; 989 if ((ci->ci_flags & CPUF_PRESENT) == 0) 990 return true; 991 992 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 993 994 if (sc->sc_wasonline) { 995 mutex_enter(&cpu_lock); 996 err = cpu_setstate(ci, false); 997 mutex_exit(&cpu_lock); 998 999 if (err) 1000 return false; 1001 } 1002 1003 return true; 1004 } 1005 1006 static bool 1007 cpu_resume(device_t dv PMF_FN_ARGS) 1008 { 1009 struct cpu_softc *sc = device_private(dv); 1010 struct cpu_info *ci = sc->sc_info; 1011 int err = 0; 1012 1013 if (ci->ci_flags & CPUF_PRIMARY) 1014 return true; 1015 if (ci->ci_data.cpu_idlelwp == NULL) 1016 return true; 1017 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1018 return true; 1019 1020 if (sc->sc_wasonline) { 1021 mutex_enter(&cpu_lock); 1022 err = cpu_setstate(ci, true); 1023 mutex_exit(&cpu_lock); 1024 } 1025 1026 return err == 0; 1027 } 1028 #endif 1029 1030 void 1031 cpu_get_tsc_freq(struct cpu_info *ci) 1032 { 1033 #ifdef XEN3 1034 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1035 delay(1000000); 1036 uint64_t freq = 1000000000ULL << 32; 1037 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1038 if ( tinfo->tsc_shift < 0 ) 1039 freq = freq << -tinfo->tsc_shift; 1040 else 1041 freq = freq >> tinfo->tsc_shift; 1042 ci->ci_data.cpu_cc_freq = freq; 1043 #else 1044 /* Xen2 */ 1045 /* XXX this needs to read the shared_info of the CPU being probed.. */ 1046 ci->ci_data.cpu_cc_freq = HYPERVISOR_shared_info->cpu_freq; 1047 #endif /* XEN3 */ 1048 } 1049 1050 void 1051 x86_cpu_idle_xen(void) 1052 { 1053 struct cpu_info *ci = curcpu(); 1054 1055 KASSERT(ci->ci_ilevel == IPL_NONE); 1056 1057 x86_disable_intr(); 1058 if (!__predict_false(ci->ci_want_resched)) { 1059 idle_block(); 1060 } else { 1061 x86_enable_intr(); 1062 } 1063 } 1064
Indexes created Fri Oct 03 02:09:57 GMT 2025