cpu.c revision 1.31.2.3
1 /* $NetBSD: cpu.c,v 1.31.2.3 2009/07/23 23:31:37 jym Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.31.2.3 2009/07/23 23:31:37 jym Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/user.h> 83 #include <sys/systm.h> 84 #include <sys/device.h> 85 #include <sys/kmem.h> 86 #include <sys/cpu.h> 87 #include <sys/atomic.h> 88 #include <sys/reboot.h> 89 90 #include <uvm/uvm_extern.h> 91 92 #include <machine/cpufunc.h> 93 #include <machine/cpuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/vmparam.h> 96 #include <machine/mpbiosvar.h> 97 #include <machine/pcb.h> 98 #include <machine/specialreg.h> 99 #include <machine/segments.h> 100 #include <machine/gdt.h> 101 #include <machine/mtrr.h> 102 #include <machine/pio.h> 103 104 #ifdef XEN3 105 #include <xen/vcpuvar.h> 106 #endif 107 108 #if NLAPIC > 0 109 #include <machine/apicvar.h> 110 #include <machine/i82489reg.h> 111 #include <machine/i82489var.h> 112 #endif 113 114 #include <dev/ic/mc146818reg.h> 115 #include <dev/isa/isareg.h> 116 117 #define X86_MAXPROCS 32 118 119 int cpu_match(device_t, cfdata_t, void *); 120 void cpu_attach(device_t, device_t, void *); 121 #ifdef XEN3 122 int vcpu_match(device_t, cfdata_t, void *); 123 void vcpu_attach(device_t, device_t, void *); 124 #endif 125 void cpu_attach_common(device_t, device_t, void *); 126 void cpu_offline_md(void); 127 128 struct cpu_softc { 129 device_t sc_dev; /* device tree glue */ 130 struct cpu_info *sc_info; /* pointer to CPU info */ 131 bool sc_wasonline; 132 }; 133 134 int mp_cpu_start(struct cpu_info *, paddr_t); 135 void mp_cpu_start_cleanup(struct cpu_info *); 136 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 137 mp_cpu_start_cleanup }; 138 139 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 140 cpu_match, cpu_attach, NULL, NULL); 141 #ifdef XEN3 142 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 143 vcpu_match, vcpu_attach, NULL, NULL); 144 #endif 145 146 /* 147 * Statically-allocated CPU info for the primary CPU (or the only 148 * CPU, on uniprocessors). The CPU info list is initialized to 149 * point at it. 150 */ 151 #ifdef TRAPLOG 152 #include <machine/tlog.h> 153 struct tlog tlog_primary; 154 #endif 155 struct cpu_info cpu_info_primary = { 156 .ci_dev = 0, 157 .ci_self = &cpu_info_primary, 158 .ci_idepth = -1, 159 .ci_curlwp = &lwp0, 160 .ci_curldt = -1, 161 #ifdef TRAPLOG 162 .ci_tlog = &tlog_primary, 163 #endif 164 165 }; 166 struct cpu_info phycpu_info_primary = { 167 .ci_dev = 0, 168 .ci_self = &phycpu_info_primary, 169 }; 170 171 struct cpu_info *cpu_info_list = &cpu_info_primary; 172 173 static void cpu_set_tss_gates(struct cpu_info *ci); 174 175 uint32_t cpus_attached = 0; 176 uint32_t cpus_running = 0; 177 178 bool x86_mp_online; 179 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 180 181 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 182 183 #ifdef MULTIPROCESSOR 184 /* 185 * Array of CPU info structures. Must be statically-allocated because 186 * curproc, etc. are used early. 187 */ 188 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 189 190 void cpu_hatch(void *); 191 static void cpu_boot_secondary(struct cpu_info *ci); 192 static void cpu_start_secondary(struct cpu_info *ci); 193 static void cpu_copy_trampoline(void); 194 195 /* 196 * Runs once per boot once multiprocessor goo has been detected and 197 * the local APIC on the boot processor has been mapped. 198 * 199 * Called from lapic_boot_init() (from mpbios_scan()). 200 */ 201 void 202 cpu_init_first(void) 203 { 204 int cpunum = lapic_cpu_number(); 205 206 if (cpunum != 0) { 207 cpu_info[0] = NULL; 208 cpu_info[cpunum] = &cpu_info_primary; 209 } 210 211 cpu_copy_trampoline(); 212 } 213 #endif 214 215 int 216 cpu_match(device_t parent, cfdata_t match, void *aux) 217 { 218 219 return 1; 220 } 221 222 void 223 cpu_attach(device_t parent, device_t self, void *aux) 224 { 225 #ifdef XEN3 226 struct cpu_softc *sc = device_private(self); 227 struct cpu_attach_args *caa = aux; 228 struct cpu_info *ci; 229 int cpunum = caa->cpu_number; 230 231 sc->sc_dev = self; 232 233 /* 234 * If we're an Application Processor, allocate a cpu_info 235 * structure, otherwise use the primary's. 236 */ 237 if (caa->cpu_role == CPU_ROLE_AP) { 238 if ((boothowto & RB_MD1) != 0) { 239 aprint_error(": multiprocessor boot disabled\n"); 240 if (!pmf_device_register(self, NULL, NULL)) 241 aprint_error_dev(self, 242 "couldn't establish power handler\n"); 243 return; 244 } 245 aprint_naive(": Application Processor\n"); 246 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 247 ci->ci_curldt = -1; 248 if (phycpu_info[cpunum] != NULL) 249 panic("cpu at apic id %d already attached?", cpunum); 250 phycpu_info[cpunum] = ci; 251 } else { 252 aprint_naive(": %s Processor\n", 253 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 254 ci = &phycpu_info_primary; 255 if (cpunum != 0) { 256 phycpu_info[0] = NULL; 257 phycpu_info[cpunum] = ci; 258 } 259 } 260 261 ci->ci_self = ci; 262 sc->sc_info = ci; 263 264 ci->ci_dev = self; 265 ci->ci_cpuid = caa->cpu_number; 266 ci->ci_vcpu = NULL; 267 268 printf(": "); 269 switch (caa->cpu_role) { 270 case CPU_ROLE_SP: 271 printf("(uniprocessor)\n"); 272 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 273 break; 274 275 case CPU_ROLE_BP: 276 printf("(boot processor)\n"); 277 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 278 break; 279 280 case CPU_ROLE_AP: 281 /* 282 * report on an AP 283 */ 284 printf("(application processor)\n"); 285 break; 286 287 default: 288 panic("unknown processor type??\n"); 289 } 290 291 if (!pmf_device_register(self, NULL, NULL)) 292 aprint_error_dev(self, "couldn't establish power handler\n"); 293 294 return; 295 #else 296 cpu_attach_common(parent, self, aux); 297 #endif 298 } 299 300 #ifdef XEN3 301 int 302 vcpu_match(device_t parent, cfdata_t match, void *aux) 303 { 304 struct vcpu_attach_args *vcaa = aux; 305 306 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 307 return 1; 308 return 0; 309 } 310 311 void 312 vcpu_attach(device_t parent, device_t self, void *aux) 313 { 314 struct vcpu_attach_args *vcaa = aux; 315 316 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 317 318 if (!pmf_device_register(self, NULL, NULL)) 319 aprint_error_dev(self, "couldn't establish power handler\n"); 320 } 321 #endif 322 323 static void 324 cpu_vm_init(struct cpu_info *ci) 325 { 326 int ncolors = 2, i; 327 328 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 329 struct x86_cache_info *cai; 330 int tcolors; 331 332 cai = &ci->ci_cinfo[i]; 333 334 tcolors = atop(cai->cai_totalsize); 335 switch(cai->cai_associativity) { 336 case 0xff: 337 tcolors = 1; /* fully associative */ 338 break; 339 case 0: 340 case 1: 341 break; 342 default: 343 tcolors /= cai->cai_associativity; 344 } 345 ncolors = max(ncolors, tcolors); 346 } 347 348 /* 349 * Knowing the size of the largest cache on this CPU, re-color 350 * our pages. 351 */ 352 if (ncolors <= uvmexp.ncolors) 353 return; 354 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 355 uvm_page_recolor(ncolors); 356 } 357 358 void 359 cpu_attach_common(device_t parent, device_t self, void *aux) 360 { 361 struct cpu_softc *sc = device_private(self); 362 struct cpu_attach_args *caa = aux; 363 struct cpu_info *ci; 364 uintptr_t ptr; 365 int cpunum = caa->cpu_number; 366 367 sc->sc_dev = self; 368 369 /* 370 * If we're an Application Processor, allocate a cpu_info 371 * structure, otherwise use the primary's. 372 */ 373 if (caa->cpu_role == CPU_ROLE_AP) { 374 if (cpunum >= X86_MAXPROCS) { 375 aprint_error(": apic id %d ignored, " 376 "please increase X86_MAXPROCS\n", cpunum); 377 } 378 379 aprint_naive(": Application Processor\n"); 380 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 381 KM_SLEEP); 382 ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) & 383 ~(CACHE_LINE_SIZE - 1)); 384 memset(ci, 0, sizeof(*ci)); 385 #if defined(MULTIPROCESSOR) 386 if (cpu_info[cpunum] != NULL) 387 panic("cpu at apic id %d already attached?", cpunum); 388 cpu_info[cpunum] = ci; 389 #endif 390 #ifdef TRAPLOG 391 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 392 #endif 393 } else { 394 aprint_naive(": %s Processor\n", 395 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 396 ci = &cpu_info_primary; 397 #if defined(MULTIPROCESSOR) 398 if (cpunum != lapic_cpu_number()) { 399 panic("%s: running CPU is at apic %d" 400 " instead of at expected %d", 401 device_xname(sc->sc_dev), lapic_cpu_number(), cpunum); 402 } 403 #endif 404 } 405 406 ci->ci_self = ci; 407 sc->sc_info = ci; 408 409 ci->ci_dev = self; 410 ci->ci_cpuid = cpunum; 411 412 KASSERT(HYPERVISOR_shared_info != NULL); 413 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 414 415 ci->ci_func = caa->cpu_func; 416 417 if (caa->cpu_role == CPU_ROLE_AP) { 418 #if defined(MULTIPROCESSOR) 419 int error; 420 421 error = mi_cpu_attach(ci); 422 if (error != 0) { 423 aprint_normal("\n"); 424 aprint_error_dev(sc->sc_dev, "mi_cpu_attach failed with %d\n", 425 error); 426 return; 427 } 428 #endif 429 } else { 430 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 431 } 432 433 ci->ci_cpumask = (1 << cpu_index(ci)); 434 pmap_reference(pmap_kernel()); 435 ci->ci_pmap = pmap_kernel(); 436 ci->ci_tlbstate = TLBSTATE_STALE; 437 438 /* further PCB init done later. */ 439 440 switch (caa->cpu_role) { 441 case CPU_ROLE_SP: 442 atomic_or_32(&ci->ci_flags, 443 CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY); 444 cpu_intr_init(ci); 445 cpu_get_tsc_freq(ci); 446 cpu_identify(ci); 447 cpu_init(ci); 448 cpu_set_tss_gates(ci); 449 pmap_cpu_init_late(ci); 450 x86_cpu_idle_init(); 451 #if 0 452 x86_errata(); 453 #endif 454 break; 455 456 case CPU_ROLE_BP: 457 atomic_or_32(&ci->ci_flags, 458 CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY); 459 cpu_intr_init(ci); 460 cpu_get_tsc_freq(ci); 461 cpu_identify(ci); 462 cpu_init(ci); 463 cpu_set_tss_gates(ci); 464 pmap_cpu_init_late(ci); 465 x86_cpu_idle_init(); 466 #if NLAPIC > 0 467 /* 468 * Enable local apic 469 */ 470 lapic_enable(); 471 lapic_set_lvt(); 472 lapic_calibrate_timer(ci); 473 #endif 474 #if 0 475 x86_errata(); 476 #endif 477 break; 478 479 case CPU_ROLE_AP: 480 /* 481 * report on an AP 482 */ 483 484 #if defined(MULTIPROCESSOR) 485 cpu_intr_init(ci); 486 gdt_alloc_cpu(ci); 487 cpu_set_tss_gates(ci); 488 pmap_cpu_init_early(ci); 489 pmap_cpu_init_late(ci); 490 cpu_start_secondary(ci); 491 if (ci->ci_flags & CPUF_PRESENT) { 492 struct cpu_info *tmp; 493 494 identifycpu(ci); 495 tmp = cpu_info_list; 496 while (tmp->ci_next) 497 tmp = tmp->ci_next; 498 499 tmp->ci_next = ci; 500 } 501 #else 502 aprint_normal_dev(sc->sc_dev, "not started\n"); 503 #endif 504 break; 505 506 default: 507 aprint_normal("\n"); 508 panic("unknown processor type??\n"); 509 } 510 cpu_vm_init(ci); 511 512 cpus_attached |= (1 << ci->ci_cpuid); 513 514 #if 0 515 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 516 aprint_error_dev(self, "couldn't establish power handler\n"); 517 #endif 518 519 #if defined(MULTIPROCESSOR) 520 if (mp_verbose) { 521 struct lwp *l = ci->ci_data.cpu_idlelwp; 522 523 aprint_verbose_dev(sc->sc_dev, "idle lwp at %p, idle sp at 0x%p\n", 524 l, 525 #ifdef i386 526 (void *)l->l_addr->u_pcb.pcb_esp 527 #else 528 (void *)l->l_addr->u_pcb.pcb_rsp 529 #endif 530 ); 531 532 } 533 #endif 534 } 535 536 /* 537 * Initialize the processor appropriately. 538 */ 539 540 void 541 cpu_init(struct cpu_info *ci) 542 { 543 544 /* 545 * On a P6 or above, enable global TLB caching if the 546 * hardware supports it. 547 */ 548 if (cpu_feature & CPUID_PGE) 549 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 550 551 #ifdef XXXMTRR 552 /* 553 * On a P6 or above, initialize MTRR's if the hardware supports them. 554 */ 555 if (cpu_feature & CPUID_MTRR) { 556 if ((ci->ci_flags & CPUF_AP) == 0) 557 i686_mtrr_init_first(); 558 mtrr_init_cpu(ci); 559 } 560 #endif 561 /* 562 * If we have FXSAVE/FXRESTOR, use them. 563 */ 564 if (cpu_feature & CPUID_FXSR) { 565 lcr4(rcr4() | CR4_OSFXSR); 566 567 /* 568 * If we have SSE/SSE2, enable XMM exceptions. 569 */ 570 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 571 lcr4(rcr4() | CR4_OSXMMEXCPT); 572 } 573 574 #ifdef MULTIPROCESSOR 575 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 576 atomic_or_32(&cpus_running, ci->ci_cpumask); 577 #endif 578 } 579 580 581 #ifdef MULTIPROCESSOR 582 void 583 cpu_boot_secondary_processors(void) 584 { 585 struct cpu_info *ci; 586 u_long i; 587 588 for (i = 0; i < X86_MAXPROCS; i++) { 589 ci = cpu_info[i]; 590 if (ci == NULL) 591 continue; 592 if (ci->ci_data.cpu_idlelwp == NULL) 593 continue; 594 if ((ci->ci_flags & CPUF_PRESENT) == 0) 595 continue; 596 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 597 continue; 598 cpu_boot_secondary(ci); 599 } 600 601 x86_mp_online = true; 602 } 603 604 static void 605 cpu_init_idle_lwp(struct cpu_info *ci) 606 { 607 struct lwp *l = ci->ci_data.cpu_idlelwp; 608 struct pcb *pcb = &l->l_addr->u_pcb; 609 610 pcb->pcb_cr0 = rcr0(); 611 } 612 613 void 614 cpu_init_idle_lwps(void) 615 { 616 struct cpu_info *ci; 617 u_long i; 618 619 for (i = 0; i < X86_MAXPROCS; i++) { 620 ci = cpu_info[i]; 621 if (ci == NULL) 622 continue; 623 if (ci->ci_data.cpu_idlelwp == NULL) 624 continue; 625 if ((ci->ci_flags & CPUF_PRESENT) == 0) 626 continue; 627 cpu_init_idle_lwp(ci); 628 } 629 } 630 631 void 632 cpu_start_secondary(struct cpu_info *ci) 633 { 634 int i; 635 struct pmap *kpm = pmap_kernel(); 636 extern uint32_t mp_pdirpa; 637 638 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 639 640 atomic_or_32(&ci->ci_flags, CPUF_AP); 641 642 aprint_debug_dev(ci->ci_dev, "starting\n"); 643 644 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 645 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 646 return; 647 648 /* 649 * wait for it to become ready 650 */ 651 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 652 #ifdef MPDEBUG 653 extern int cpu_trace[3]; 654 static int otrace[3]; 655 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 656 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 657 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 658 memcpy(otrace, cpu_trace, sizeof(otrace)); 659 } 660 #endif 661 delay(10); 662 } 663 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 664 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 665 #if defined(MPDEBUG) && defined(DDB) 666 printf("dropping into debugger; continue from here to resume boot\n"); 667 Debugger(); 668 #endif 669 } 670 671 CPU_START_CLEANUP(ci); 672 } 673 674 void 675 cpu_boot_secondary(struct cpu_info *ci) 676 { 677 int i; 678 679 atomic_or_32(&ci->ci_flags, CPUF_GO); 680 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 681 delay(10); 682 } 683 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 684 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 685 #if defined(MPDEBUG) && defined(DDB) 686 printf("dropping into debugger; continue from here to resume boot\n"); 687 Debugger(); 688 #endif 689 } 690 } 691 692 /* 693 * The CPU ends up here when its ready to run 694 * This is called from code in mptramp.s; at this point, we are running 695 * in the idle pcb/idle stack of the new CPU. When this function returns, 696 * this processor will enter the idle loop and start looking for work. 697 * 698 * XXX should share some of this with init386 in machdep.c 699 */ 700 void 701 cpu_hatch(void *v) 702 { 703 struct cpu_info *ci = (struct cpu_info *)v; 704 int s, i; 705 uint32_t blacklist_features; 706 707 #ifdef __x86_64__ 708 cpu_init_msrs(ci, true); 709 #endif 710 711 cpu_probe(ci); 712 713 /* not on Xen... */ 714 blacklist_features = ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); /* XXX add CPUID_SVM */ 715 716 cpu_feature &= blacklist_features; 717 718 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 719 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 720 while ((ci->ci_flags & CPUF_GO) == 0) { 721 /* Don't use delay, boot CPU may be patching the text. */ 722 for (i = 10000; i != 0; i--) 723 x86_pause(); 724 } 725 726 /* Because the text may have been patched in x86_patch(). */ 727 wbinvd(); 728 x86_flush(); 729 730 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 731 732 lcr3(pmap_kernel()->pm_pdirpa); 733 curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa; 734 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 735 cpu_init_idt(); 736 gdt_init_cpu(ci); 737 lapic_enable(); 738 lapic_set_lvt(); 739 lapic_initclocks(); 740 741 #ifdef i386 742 npxinit(ci); 743 #else 744 fpuinit(ci); 745 #endif 746 747 lldt(GSEL(GLDT_SEL, SEL_KPL)); 748 ltr(ci->ci_tss_sel); 749 750 cpu_init(ci); 751 cpu_get_tsc_freq(ci); 752 753 s = splhigh(); 754 #ifdef i386 755 lapic_tpr = 0; 756 #else 757 lcr8(0); 758 #endif 759 x86_enable_intr(); 760 splx(s); 761 #if 0 762 x86_errata(); 763 #endif 764 765 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 766 (long)ci->ci_cpuid); 767 } 768 769 #if defined(DDB) 770 771 #include <ddb/db_output.h> 772 #include <machine/db_machdep.h> 773 774 /* 775 * Dump CPU information from ddb. 776 */ 777 void 778 cpu_debug_dump(void) 779 { 780 struct cpu_info *ci; 781 CPU_INFO_ITERATOR cii; 782 783 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 784 for (CPU_INFO_FOREACH(cii, ci)) { 785 db_printf("%p %s %ld %x %x %10p %10p\n", 786 ci, 787 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 788 (long)ci->ci_cpuid, 789 ci->ci_flags, ci->ci_ipis, 790 ci->ci_curlwp, 791 ci->ci_fpcurlwp); 792 } 793 } 794 #endif 795 796 static void 797 cpu_copy_trampoline(void) 798 { 799 /* 800 * Copy boot code. 801 */ 802 extern u_char cpu_spinup_trampoline[]; 803 extern u_char cpu_spinup_trampoline_end[]; 804 805 vaddr_t mp_trampoline_vaddr; 806 807 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 808 UVM_KMF_VAONLY); 809 810 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 811 VM_PROT_READ | VM_PROT_WRITE); 812 pmap_update(pmap_kernel()); 813 memcpy((void *)mp_trampoline_vaddr, 814 cpu_spinup_trampoline, 815 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 816 817 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 818 pmap_update(pmap_kernel()); 819 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 820 } 821 822 #endif 823 824 #ifdef i386 825 #if 0 826 static void 827 tss_init(struct i386tss *tss, void *stack, void *func) 828 { 829 memset(tss, 0, sizeof *tss); 830 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 831 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 832 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 833 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 834 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 835 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 836 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 837 tss->tss_esp = (int)((char *)stack + USPACE - 16); 838 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 839 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 840 tss->__tss_eip = (int)func; 841 } 842 #endif 843 844 /* XXX */ 845 #define IDTVEC(name) __CONCAT(X, name) 846 typedef void (vector)(void); 847 extern vector IDTVEC(tss_trap08); 848 #ifdef DDB 849 extern vector Xintrddbipi; 850 extern int ddb_vec; 851 #endif 852 853 static void 854 cpu_set_tss_gates(struct cpu_info *ci) 855 { 856 #if 0 857 struct segment_descriptor sd; 858 859 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 860 UVM_KMF_WIRED); 861 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 862 IDTVEC(tss_trap08)); 863 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 864 SDT_SYS386TSS, SEL_KPL, 0, 0); 865 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 866 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 867 GSEL(GTRAPTSS_SEL, SEL_KPL)); 868 #endif 869 870 #if defined(DDB) && defined(MULTIPROCESSOR) 871 /* 872 * Set up separate handler for the DDB IPI, so that it doesn't 873 * stomp on a possibly corrupted stack. 874 * 875 * XXX overwriting the gate set in db_machine_init. 876 * Should rearrange the code so that it's set only once. 877 */ 878 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 879 UVM_KMF_WIRED); 880 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 881 Xintrddbipi); 882 883 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 884 SDT_SYS386TSS, SEL_KPL, 0, 0); 885 ci->ci_gdt[GIPITSS_SEL].sd = sd; 886 887 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 888 GSEL(GIPITSS_SEL, SEL_KPL)); 889 #endif 890 } 891 #else 892 static void 893 cpu_set_tss_gates(struct cpu_info *ci) 894 { 895 896 } 897 #endif /* i386 */ 898 899 int 900 mp_cpu_start(struct cpu_info *ci, paddr_t target) 901 { 902 #if 0 903 #if NLAPIC > 0 904 int error; 905 #endif 906 unsigned short dwordptr[2]; 907 908 /* 909 * Bootstrap code must be addressable in real mode 910 * and it must be page aligned. 911 */ 912 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 913 914 /* 915 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 916 */ 917 918 outb(IO_RTC, NVRAM_RESET); 919 outb(IO_RTC+1, NVRAM_RESET_JUMP); 920 921 /* 922 * "and the warm reset vector (DWORD based at 40:67) to point 923 * to the AP startup code ..." 924 */ 925 926 dwordptr[0] = 0; 927 dwordptr[1] = target >> 4; 928 929 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 930 memcpy ((uint8_t *) 0x467, dwordptr, 4); 931 pmap_kremove (0, PAGE_SIZE); 932 933 #if NLAPIC > 0 934 /* 935 * ... prior to executing the following sequence:" 936 */ 937 938 if (ci->ci_flags & CPUF_AP) { 939 if ((error = x86_ipi_init(ci->ci_cpuid)) != 0) 940 return error; 941 942 delay(10000); 943 944 if (cpu_feature & CPUID_APIC) { 945 error = x86_ipi_init(ci->ci_cpuid); 946 if (error != 0) { 947 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 948 __func__); 949 return error; 950 } 951 952 delay(10000); 953 954 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 955 LAPIC_DLMODE_STARTUP); 956 if (error != 0) { 957 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 958 __func__); 959 return error; 960 } 961 delay(200); 962 963 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 964 LAPIC_DLMODE_STARTUP); 965 if (error != 0) { 966 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 967 __func__); 968 return error; 969 } 970 delay(200); 971 } 972 } 973 #endif 974 #endif /* 0 */ 975 return 0; 976 } 977 978 void 979 mp_cpu_start_cleanup(struct cpu_info *ci) 980 { 981 #if 0 982 /* 983 * Ensure the NVRAM reset byte contains something vaguely sane. 984 */ 985 986 outb(IO_RTC, NVRAM_RESET); 987 outb(IO_RTC+1, NVRAM_RESET_RST); 988 #endif 989 } 990 991 #ifdef __x86_64__ 992 993 void 994 cpu_init_msrs(struct cpu_info *ci, bool full) 995 { 996 if (full) { 997 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 998 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 999 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1000 } 1001 } 1002 #endif /* __x86_64__ */ 1003 1004 void 1005 cpu_offline_md(void) 1006 { 1007 int s; 1008 1009 s = splhigh(); 1010 #ifdef __i386__ 1011 npxsave_cpu(true); 1012 #else 1013 fpusave_cpu(true); 1014 #endif 1015 splx(s); 1016 } 1017 1018 #if 0 1019 /* XXX joerg restructure and restart CPUs individually */ 1020 static bool 1021 cpu_suspend(device_t dv PMF_FN_ARGS) 1022 { 1023 struct cpu_softc *sc = device_private(dv); 1024 struct cpu_info *ci = sc->sc_info; 1025 int err; 1026 1027 if (ci->ci_flags & CPUF_PRIMARY) 1028 return true; 1029 if (ci->ci_data.cpu_idlelwp == NULL) 1030 return true; 1031 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1032 return true; 1033 1034 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1035 1036 if (sc->sc_wasonline) { 1037 mutex_enter(&cpu_lock); 1038 err = cpu_setstate(ci, false); 1039 mutex_exit(&cpu_lock); 1040 1041 if (err) 1042 return false; 1043 } 1044 1045 return true; 1046 } 1047 1048 static bool 1049 cpu_resume(device_t dv PMF_FN_ARGS) 1050 { 1051 struct cpu_softc *sc = device_private(dv); 1052 struct cpu_info *ci = sc->sc_info; 1053 int err = 0; 1054 1055 if (ci->ci_flags & CPUF_PRIMARY) 1056 return true; 1057 if (ci->ci_data.cpu_idlelwp == NULL) 1058 return true; 1059 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1060 return true; 1061 1062 if (sc->sc_wasonline) { 1063 mutex_enter(&cpu_lock); 1064 err = cpu_setstate(ci, true); 1065 mutex_exit(&cpu_lock); 1066 } 1067 1068 return err == 0; 1069 } 1070 #endif 1071 1072 void 1073 cpu_get_tsc_freq(struct cpu_info *ci) 1074 { 1075 #ifdef XEN3 1076 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1077 delay(1000000); 1078 uint64_t freq = 1000000000ULL << 32; 1079 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1080 if ( tinfo->tsc_shift < 0 ) 1081 freq = freq << -tinfo->tsc_shift; 1082 else 1083 freq = freq >> tinfo->tsc_shift; 1084 ci->ci_data.cpu_cc_freq = freq; 1085 #else 1086 /* Xen2 */ 1087 /* XXX this needs to read the shared_info of the CPU being probed.. */ 1088 ci->ci_data.cpu_cc_freq = HYPERVISOR_shared_info->cpu_freq; 1089 #endif /* XEN3 */ 1090 } 1091 1092 void 1093 x86_cpu_idle_xen(void) 1094 { 1095 struct cpu_info *ci = curcpu(); 1096 1097 KASSERT(ci->ci_ilevel == IPL_NONE); 1098 1099 x86_disable_intr(); 1100 if (!__predict_false(ci->ci_want_resched)) { 1101 idle_block(); 1102 } else { 1103 x86_enable_intr(); 1104 } 1105 } 1106
Indexes created Fri Oct 03 02:09:57 GMT 2025