cpu.c revision 1.46
1 /* $NetBSD: cpu.c,v 1.46 2010/07/06 20:50:35 cegger Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.46 2010/07/06 20:50:35 cegger Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm_extern.h> 90 91 #include <machine/cpufunc.h> 92 #include <machine/cpuvar.h> 93 #include <machine/pmap.h> 94 #include <machine/vmparam.h> 95 #include <machine/mpbiosvar.h> 96 #include <machine/pcb.h> 97 #include <machine/specialreg.h> 98 #include <machine/segments.h> 99 #include <machine/gdt.h> 100 #include <machine/mtrr.h> 101 #include <machine/pio.h> 102 103 #include <xen/vcpuvar.h> 104 105 #if NLAPIC > 0 106 #include <machine/apicvar.h> 107 #include <machine/i82489reg.h> 108 #include <machine/i82489var.h> 109 #endif 110 111 #include <dev/ic/mc146818reg.h> 112 #include <dev/isa/isareg.h> 113 114 #if MAXCPUS > 32 115 #error cpu_info contains 32bit bitmasks 116 #endif 117 118 int cpu_match(device_t, cfdata_t, void *); 119 void cpu_attach(device_t, device_t, void *); 120 int vcpu_match(device_t, cfdata_t, void *); 121 void vcpu_attach(device_t, device_t, void *); 122 void cpu_attach_common(device_t, device_t, void *); 123 void cpu_offline_md(void); 124 125 struct cpu_softc { 126 device_t sc_dev; /* device tree glue */ 127 struct cpu_info *sc_info; /* pointer to CPU info */ 128 bool sc_wasonline; 129 }; 130 131 int mp_cpu_start(struct cpu_info *, paddr_t); 132 void mp_cpu_start_cleanup(struct cpu_info *); 133 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 134 mp_cpu_start_cleanup }; 135 136 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 137 cpu_match, cpu_attach, NULL, NULL); 138 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 139 vcpu_match, vcpu_attach, NULL, NULL); 140 141 /* 142 * Statically-allocated CPU info for the primary CPU (or the only 143 * CPU, on uniprocessors). The CPU info list is initialized to 144 * point at it. 145 */ 146 #ifdef TRAPLOG 147 #include <machine/tlog.h> 148 struct tlog tlog_primary; 149 #endif 150 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 151 .ci_dev = 0, 152 .ci_self = &cpu_info_primary, 153 .ci_idepth = -1, 154 .ci_curlwp = &lwp0, 155 .ci_curldt = -1, 156 #ifdef TRAPLOG 157 .ci_tlog = &tlog_primary, 158 #endif 159 160 }; 161 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 162 .ci_dev = 0, 163 .ci_self = &phycpu_info_primary, 164 }; 165 166 struct cpu_info *cpu_info_list = &cpu_info_primary; 167 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 168 169 static void cpu_set_tss_gates(struct cpu_info *ci); 170 171 uint32_t cpus_attached = 0; 172 uint32_t cpus_running = 0; 173 174 uint32_t phycpus_attached = 0; 175 uint32_t phycpus_running = 0; 176 177 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 178 * [0] basic features %edx 179 * [1] basic features %ecx 180 * [2] extended features %edx 181 * [3] extended features %ecx 182 * [4] VIA padlock features 183 */ 184 185 bool x86_mp_online; 186 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 187 188 #if defined(MULTIPROCESSOR) 189 void cpu_hatch(void *); 190 static void cpu_boot_secondary(struct cpu_info *ci); 191 static void cpu_start_secondary(struct cpu_info *ci); 192 static void cpu_copy_trampoline(void); 193 194 /* 195 * Runs once per boot once multiprocessor goo has been detected and 196 * the local APIC on the boot processor has been mapped. 197 * 198 * Called from lapic_boot_init() (from mpbios_scan()). 199 */ 200 void 201 cpu_init_first(void) 202 { 203 204 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 205 cpu_copy_trampoline(); 206 } 207 #endif /* MULTIPROCESSOR */ 208 209 int 210 cpu_match(device_t parent, cfdata_t match, void *aux) 211 { 212 213 return 1; 214 } 215 216 void 217 cpu_attach(device_t parent, device_t self, void *aux) 218 { 219 struct cpu_softc *sc = device_private(self); 220 struct cpu_attach_args *caa = aux; 221 struct cpu_info *ci; 222 uintptr_t ptr; 223 static bool again = false; 224 225 sc->sc_dev = self; 226 227 if (phycpus_attached == ~0) { 228 aprint_error(": increase MAXCPUS\n"); 229 return; 230 } 231 232 /* 233 * If we're an Application Processor, allocate a cpu_info 234 * structure, otherwise use the primary's. 235 */ 236 if (caa->cpu_role == CPU_ROLE_AP) { 237 if ((boothowto & RB_MD1) != 0) { 238 aprint_error(": multiprocessor boot disabled\n"); 239 if (!pmf_device_register(self, NULL, NULL)) 240 aprint_error_dev(self, 241 "couldn't establish power handler\n"); 242 return; 243 } 244 aprint_naive(": Application Processor\n"); 245 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 246 KM_SLEEP); 247 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 248 ci->ci_curldt = -1; 249 } else { 250 aprint_naive(": %s Processor\n", 251 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 252 ci = &phycpu_info_primary; 253 } 254 255 ci->ci_self = ci; 256 sc->sc_info = ci; 257 258 ci->ci_dev = self; 259 ci->ci_cpuid = caa->cpu_number; 260 ci->ci_vcpu = NULL; 261 262 /* 263 * Boot processor may not be attached first, but the below 264 * must be done to allow booting other processors. 265 */ 266 if (!again) { 267 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 268 /* Basic init */ 269 again = true; 270 } 271 272 printf(": "); 273 switch (caa->cpu_role) { 274 case CPU_ROLE_SP: 275 printf("(uniprocessor)\n"); 276 atomic_or_32(&ci->ci_flags, CPUF_SP); 277 break; 278 279 case CPU_ROLE_BP: 280 printf("(boot processor)\n"); 281 atomic_or_32(&ci->ci_flags, CPUF_BSP); 282 break; 283 284 case CPU_ROLE_AP: 285 /* 286 * report on an AP 287 */ 288 printf("(application processor)\n"); 289 if (ci->ci_flags & CPUF_PRESENT) { 290 struct cpu_info *tmp; 291 292 tmp = phycpu_info_list; 293 while (tmp->ci_next) 294 tmp = tmp->ci_next; 295 296 tmp->ci_next = ci; 297 } 298 break; 299 300 default: 301 panic("unknown processor type??\n"); 302 } 303 304 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 305 306 return; 307 } 308 309 int 310 vcpu_match(device_t parent, cfdata_t match, void *aux) 311 { 312 struct vcpu_attach_args *vcaa = aux; 313 314 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 315 return 1; 316 return 0; 317 } 318 319 void 320 vcpu_attach(device_t parent, device_t self, void *aux) 321 { 322 struct vcpu_attach_args *vcaa = aux; 323 324 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 325 } 326 327 static void 328 cpu_vm_init(struct cpu_info *ci) 329 { 330 int ncolors = 2, i; 331 332 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 333 struct x86_cache_info *cai; 334 int tcolors; 335 336 cai = &ci->ci_cinfo[i]; 337 338 tcolors = atop(cai->cai_totalsize); 339 switch(cai->cai_associativity) { 340 case 0xff: 341 tcolors = 1; /* fully associative */ 342 break; 343 case 0: 344 case 1: 345 break; 346 default: 347 tcolors /= cai->cai_associativity; 348 } 349 ncolors = max(ncolors, tcolors); 350 } 351 352 /* 353 * Knowing the size of the largest cache on this CPU, re-color 354 * our pages. 355 */ 356 if (ncolors <= uvmexp.ncolors) 357 return; 358 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 359 uvm_page_recolor(ncolors); 360 } 361 362 void 363 cpu_attach_common(device_t parent, device_t self, void *aux) 364 { 365 struct cpu_softc *sc = device_private(self); 366 struct cpu_attach_args *caa = aux; 367 struct cpu_info *ci; 368 uintptr_t ptr; 369 int cpunum = caa->cpu_number; 370 static bool again = false; 371 372 sc->sc_dev = self; 373 374 /* 375 * If we're an Application Processor, allocate a cpu_info 376 * structure, otherwise use the primary's. 377 */ 378 if (caa->cpu_role == CPU_ROLE_AP) { 379 aprint_naive(": Application Processor\n"); 380 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 381 KM_SLEEP); 382 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 383 memset(ci, 0, sizeof(*ci)); 384 #ifdef TRAPLOG 385 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 386 #endif 387 } else { 388 aprint_naive(": %s Processor\n", 389 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 390 ci = &cpu_info_primary; 391 #if NLAPIC > 0 392 if (cpunum != lapic_cpu_number()) { 393 /* XXX should be done earlier */ 394 uint32_t reg; 395 aprint_verbose("\n"); 396 aprint_verbose_dev(self, "running CPU at apic %d" 397 " instead of at expected %d", lapic_cpu_number(), 398 cpunum); 399 reg = i82489_readreg(LAPIC_ID); 400 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 401 (cpunum << LAPIC_ID_SHIFT)); 402 } 403 if (cpunum != lapic_cpu_number()) { 404 aprint_error_dev(self, "unable to reset apic id\n"); 405 } 406 #endif 407 } 408 409 ci->ci_self = ci; 410 sc->sc_info = ci; 411 ci->ci_dev = self; 412 ci->ci_cpuid = cpunum; 413 414 KASSERT(HYPERVISOR_shared_info != NULL); 415 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 416 417 ci->ci_func = caa->cpu_func; 418 419 /* Must be called before mi_cpu_attach(). */ 420 cpu_vm_init(ci); 421 422 if (caa->cpu_role == CPU_ROLE_AP) { 423 int error; 424 425 error = mi_cpu_attach(ci); 426 if (error != 0) { 427 aprint_normal("\n"); 428 aprint_error_dev(self, 429 "mi_cpu_attach failed with %d\n", error); 430 return; 431 } 432 } else { 433 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 434 } 435 436 ci->ci_cpumask = (1 << cpu_index(ci)); 437 pmap_reference(pmap_kernel()); 438 ci->ci_pmap = pmap_kernel(); 439 ci->ci_tlbstate = TLBSTATE_STALE; 440 441 /* 442 * Boot processor may not be attached first, but the below 443 * must be done to allow booting other processors. 444 */ 445 if (!again) { 446 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 447 /* Basic init. */ 448 cpu_intr_init(ci); 449 cpu_get_tsc_freq(ci); 450 cpu_init(ci); 451 cpu_set_tss_gates(ci); 452 pmap_cpu_init_late(ci); 453 #if NLAPIC > 0 454 if (caa->cpu_role != CPU_ROLE_SP) { 455 /* Enable lapic. */ 456 lapic_enable(); 457 lapic_set_lvt(); 458 lapic_calibrate_timer(); 459 } 460 #endif 461 /* Make sure DELAY() is initialized. */ 462 DELAY(1); 463 again = true; 464 } 465 466 /* further PCB init done later. */ 467 468 switch (caa->cpu_role) { 469 case CPU_ROLE_SP: 470 atomic_or_32(&ci->ci_flags, CPUF_SP); 471 cpu_identify(ci); 472 #if 0 473 x86_errata(); 474 #endif 475 x86_cpu_idle_init(); 476 break; 477 478 case CPU_ROLE_BP: 479 atomic_or_32(&ci->ci_flags, CPUF_BSP); 480 cpu_identify(ci); 481 cpu_init(ci); 482 #if 0 483 x86_errata(); 484 #endif 485 x86_cpu_idle_init(); 486 break; 487 488 case CPU_ROLE_AP: 489 /* 490 * report on an AP 491 */ 492 493 #if defined(MULTIPROCESSOR) 494 cpu_intr_init(ci); 495 gdt_alloc_cpu(ci); 496 cpu_set_tss_gates(ci); 497 pmap_cpu_init_early(ci); 498 pmap_cpu_init_late(ci); 499 cpu_start_secondary(ci); 500 if (ci->ci_flags & CPUF_PRESENT) { 501 struct cpu_info *tmp; 502 503 identifycpu(ci); 504 tmp = cpu_info_list; 505 while (tmp->ci_next) 506 tmp = tmp->ci_next; 507 508 tmp->ci_next = ci; 509 } 510 #else 511 aprint_error_dev(self, "not started\n"); 512 #endif 513 break; 514 515 default: 516 aprint_normal("\n"); 517 panic("unknown processor type??\n"); 518 } 519 520 pat_init(ci); 521 atomic_or_32(&cpus_attached, ci->ci_cpumask); 522 523 #if 0 524 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 525 aprint_error_dev(self, "couldn't establish power handler\n"); 526 #endif 527 528 #if defined(MULTIPROCESSOR) 529 if (mp_verbose) { 530 struct lwp *l = ci->ci_data.cpu_idlelwp; 531 struct pcb *pcb = lwp_getpcb(l); 532 533 aprint_verbose_dev(self, 534 "idle lwp at %p, idle sp at 0x%p\n", 535 l, 536 #ifdef i386 537 (void *)pcb->pcb_esp 538 #else 539 (void *)pcb->pcb_rsp 540 #endif 541 ); 542 543 } 544 #endif 545 } 546 547 /* 548 * Initialize the processor appropriately. 549 */ 550 551 void 552 cpu_init(struct cpu_info *ci) 553 { 554 555 /* 556 * On a P6 or above, enable global TLB caching if the 557 * hardware supports it. 558 */ 559 if (cpu_feature[0] & CPUID_PGE) 560 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 561 562 #ifdef XXXMTRR 563 /* 564 * On a P6 or above, initialize MTRR's if the hardware supports them. 565 */ 566 if (cpu_feature[0] & CPUID_MTRR) { 567 if ((ci->ci_flags & CPUF_AP) == 0) 568 i686_mtrr_init_first(); 569 mtrr_init_cpu(ci); 570 } 571 #endif 572 /* 573 * If we have FXSAVE/FXRESTOR, use them. 574 */ 575 if (cpu_feature[0] & CPUID_FXSR) { 576 lcr4(rcr4() | CR4_OSFXSR); 577 578 /* 579 * If we have SSE/SSE2, enable XMM exceptions. 580 */ 581 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 582 lcr4(rcr4() | CR4_OSXMMEXCPT); 583 } 584 585 atomic_or_32(&cpus_running, ci->ci_cpumask); 586 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 587 } 588 589 590 #ifdef MULTIPROCESSOR 591 void 592 cpu_boot_secondary_processors(void) 593 { 594 struct cpu_info *ci; 595 u_long i; 596 597 for (i = 0; i < maxcpus; i++) { 598 ci = cpu_lookup(i); 599 if (ci == NULL) 600 continue; 601 if (ci->ci_data.cpu_idlelwp == NULL) 602 continue; 603 if ((ci->ci_flags & CPUF_PRESENT) == 0) 604 continue; 605 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 606 continue; 607 cpu_boot_secondary(ci); 608 } 609 610 x86_mp_online = true; 611 } 612 613 static void 614 cpu_init_idle_lwp(struct cpu_info *ci) 615 { 616 struct lwp *l = ci->ci_data.cpu_idlelwp; 617 struct pcb *pcb = lwp_getpcb(l); 618 619 pcb->pcb_cr0 = rcr0(); 620 } 621 622 void 623 cpu_init_idle_lwps(void) 624 { 625 struct cpu_info *ci; 626 u_long i; 627 628 for (i = 0; i < maxcpus; i++) { 629 ci = cpu_lookup(i); 630 if (ci == NULL) 631 continue; 632 if (ci->ci_data.cpu_idlelwp == NULL) 633 continue; 634 if ((ci->ci_flags & CPUF_PRESENT) == 0) 635 continue; 636 cpu_init_idle_lwp(ci); 637 } 638 } 639 640 void 641 cpu_start_secondary(struct cpu_info *ci) 642 { 643 int i; 644 struct pmap *kpm = pmap_kernel(); 645 extern uint32_t mp_pdirpa; 646 647 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 648 649 atomic_or_32(&ci->ci_flags, CPUF_AP); 650 651 aprint_debug_dev(ci->ci_dev, "starting\n"); 652 653 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 654 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 655 return; 656 657 /* 658 * wait for it to become ready 659 */ 660 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 661 #ifdef MPDEBUG 662 extern int cpu_trace[3]; 663 static int otrace[3]; 664 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 665 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 666 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 667 memcpy(otrace, cpu_trace, sizeof(otrace)); 668 } 669 #endif 670 delay(10); 671 } 672 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 673 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 674 #if defined(MPDEBUG) && defined(DDB) 675 printf("dropping into debugger; continue from here to resume boot\n"); 676 Debugger(); 677 #endif 678 } 679 680 CPU_START_CLEANUP(ci); 681 } 682 683 void 684 cpu_boot_secondary(struct cpu_info *ci) 685 { 686 int i; 687 688 atomic_or_32(&ci->ci_flags, CPUF_GO); 689 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 690 delay(10); 691 } 692 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 693 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 694 #if defined(MPDEBUG) && defined(DDB) 695 printf("dropping into debugger; continue from here to resume boot\n"); 696 Debugger(); 697 #endif 698 } 699 } 700 701 /* 702 * The CPU ends up here when its ready to run 703 * This is called from code in mptramp.s; at this point, we are running 704 * in the idle pcb/idle stack of the new CPU. When this function returns, 705 * this processor will enter the idle loop and start looking for work. 706 * 707 * XXX should share some of this with init386 in machdep.c 708 */ 709 void 710 cpu_hatch(void *v) 711 { 712 struct cpu_info *ci = (struct cpu_info *)v; 713 struct pcb *pcb; 714 int s, i; 715 716 cpu_probe(ci); 717 718 cpu_feature[0] &= ~CPUID_FEAT_BLACKLIST; 719 cpu_feature[2] &= ~CPUID_FEAT_EXT_BLACKLIST; 720 721 cpu_init_msrs(ci, true); 722 723 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 724 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 725 while ((ci->ci_flags & CPUF_GO) == 0) { 726 /* Don't use delay, boot CPU may be patching the text. */ 727 for (i = 10000; i != 0; i--) 728 x86_pause(); 729 } 730 731 /* Because the text may have been patched in x86_patch(). */ 732 wbinvd(); 733 x86_flush(); 734 735 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 736 737 pcb = lwp_getpcb(curlwp); 738 lcr3(pmap_kernel()->pm_pdirpa); 739 pcb->pcb_cr3 = pmap_kernel()->pm_pdirpa; 740 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 741 lcr0(pcb->pcb_cr0); 742 743 cpu_init_idt(); 744 gdt_init_cpu(ci); 745 lapic_enable(); 746 lapic_set_lvt(); 747 lapic_initclocks(); 748 749 #ifdef i386 750 npxinit(ci); 751 #else 752 fpuinit(ci); 753 #endif 754 755 lldt(GSEL(GLDT_SEL, SEL_KPL)); 756 ltr(ci->ci_tss_sel); 757 758 cpu_init(ci); 759 cpu_get_tsc_freq(ci); 760 761 s = splhigh(); 762 #ifdef i386 763 lapic_tpr = 0; 764 #else 765 lcr8(0); 766 #endif 767 x86_enable_intr(); 768 splx(s); 769 #if 0 770 x86_errata(); 771 #endif 772 773 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 774 (long)ci->ci_cpuid); 775 } 776 777 #if defined(DDB) 778 779 #include <ddb/db_output.h> 780 #include <machine/db_machdep.h> 781 782 /* 783 * Dump CPU information from ddb. 784 */ 785 void 786 cpu_debug_dump(void) 787 { 788 struct cpu_info *ci; 789 CPU_INFO_ITERATOR cii; 790 791 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 792 for (CPU_INFO_FOREACH(cii, ci)) { 793 db_printf("%p %s %ld %x %x %10p %10p\n", 794 ci, 795 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 796 (long)ci->ci_cpuid, 797 ci->ci_flags, ci->ci_ipis, 798 ci->ci_curlwp, 799 ci->ci_fpcurlwp); 800 } 801 } 802 #endif /* DDB */ 803 804 static void 805 cpu_copy_trampoline(void) 806 { 807 /* 808 * Copy boot code. 809 */ 810 extern u_char cpu_spinup_trampoline[]; 811 extern u_char cpu_spinup_trampoline_end[]; 812 813 vaddr_t mp_trampoline_vaddr; 814 815 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 816 UVM_KMF_VAONLY); 817 818 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 819 VM_PROT_READ | VM_PROT_WRITE, 0); 820 pmap_update(pmap_kernel()); 821 memcpy((void *)mp_trampoline_vaddr, 822 cpu_spinup_trampoline, 823 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 824 825 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 826 pmap_update(pmap_kernel()); 827 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 828 } 829 830 #endif /* MULTIPROCESSOR */ 831 832 #ifdef i386 833 #if 0 834 static void 835 tss_init(struct i386tss *tss, void *stack, void *func) 836 { 837 memset(tss, 0, sizeof *tss); 838 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 839 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 840 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 841 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 842 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 843 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 844 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 845 tss->tss_esp = (int)((char *)stack + USPACE - 16); 846 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 847 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 848 tss->__tss_eip = (int)func; 849 } 850 #endif 851 852 /* XXX */ 853 #define IDTVEC(name) __CONCAT(X, name) 854 typedef void (vector)(void); 855 extern vector IDTVEC(tss_trap08); 856 #ifdef DDB 857 extern vector Xintrddbipi; 858 extern int ddb_vec; 859 #endif 860 861 static void 862 cpu_set_tss_gates(struct cpu_info *ci) 863 { 864 #if 0 865 struct segment_descriptor sd; 866 867 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 868 UVM_KMF_WIRED); 869 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 870 IDTVEC(tss_trap08)); 871 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 872 SDT_SYS386TSS, SEL_KPL, 0, 0); 873 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 874 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 875 GSEL(GTRAPTSS_SEL, SEL_KPL)); 876 #endif 877 878 #if defined(DDB) && defined(MULTIPROCESSOR) 879 /* 880 * Set up separate handler for the DDB IPI, so that it doesn't 881 * stomp on a possibly corrupted stack. 882 * 883 * XXX overwriting the gate set in db_machine_init. 884 * Should rearrange the code so that it's set only once. 885 */ 886 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 887 UVM_KMF_WIRED); 888 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 889 Xintrddbipi); 890 891 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 892 SDT_SYS386TSS, SEL_KPL, 0, 0); 893 ci->ci_gdt[GIPITSS_SEL].sd = sd; 894 895 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 896 GSEL(GIPITSS_SEL, SEL_KPL)); 897 #endif 898 } 899 #else 900 static void 901 cpu_set_tss_gates(struct cpu_info *ci) 902 { 903 904 } 905 #endif /* i386 */ 906 907 int 908 mp_cpu_start(struct cpu_info *ci, paddr_t target) 909 { 910 #if 0 911 #if NLAPIC > 0 912 int error; 913 #endif 914 unsigned short dwordptr[2]; 915 916 /* 917 * Bootstrap code must be addressable in real mode 918 * and it must be page aligned. 919 */ 920 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 921 922 /* 923 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 924 */ 925 926 outb(IO_RTC, NVRAM_RESET); 927 outb(IO_RTC+1, NVRAM_RESET_JUMP); 928 929 /* 930 * "and the warm reset vector (DWORD based at 40:67) to point 931 * to the AP startup code ..." 932 */ 933 934 dwordptr[0] = 0; 935 dwordptr[1] = target >> 4; 936 937 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 938 pmap_update(pmap_kernel()); 939 940 memcpy ((uint8_t *) 0x467, dwordptr, 4); 941 942 pmap_kremove (0, PAGE_SIZE); 943 pmap_update(pmap_kernel()); 944 945 #if NLAPIC > 0 946 /* 947 * ... prior to executing the following sequence:" 948 */ 949 950 if (ci->ci_flags & CPUF_AP) { 951 if ((error = x86_ipi_init(ci->ci_cpuid)) != 0) 952 return error; 953 954 delay(10000); 955 956 if (cpu_feature & CPUID_APIC) { 957 error = x86_ipi_init(ci->ci_cpuid); 958 if (error != 0) { 959 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 960 __func__); 961 return error; 962 } 963 964 delay(10000); 965 966 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 967 LAPIC_DLMODE_STARTUP); 968 if (error != 0) { 969 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 970 __func__); 971 return error; 972 } 973 delay(200); 974 975 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 976 LAPIC_DLMODE_STARTUP); 977 if (error != 0) { 978 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 979 __func__); 980 return error; 981 } 982 delay(200); 983 } 984 } 985 #endif 986 #endif /* 0 */ 987 return 0; 988 } 989 990 void 991 mp_cpu_start_cleanup(struct cpu_info *ci) 992 { 993 #if 0 994 /* 995 * Ensure the NVRAM reset byte contains something vaguely sane. 996 */ 997 998 outb(IO_RTC, NVRAM_RESET); 999 outb(IO_RTC+1, NVRAM_RESET_RST); 1000 #endif 1001 } 1002 1003 void 1004 cpu_init_msrs(struct cpu_info *ci, bool full) 1005 { 1006 #ifdef __x86_64__ 1007 if (full) { 1008 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1009 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1010 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1011 } 1012 #endif /* __x86_64__ */ 1013 1014 if (cpu_feature[2] & CPUID_NOX) 1015 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1016 } 1017 1018 void 1019 cpu_offline_md(void) 1020 { 1021 int s; 1022 1023 s = splhigh(); 1024 #ifdef __i386__ 1025 npxsave_cpu(true); 1026 #else 1027 fpusave_cpu(true); 1028 #endif 1029 splx(s); 1030 } 1031 1032 #if 0 1033 /* XXX joerg restructure and restart CPUs individually */ 1034 static bool 1035 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1036 { 1037 struct cpu_softc *sc = device_private(dv); 1038 struct cpu_info *ci = sc->sc_info; 1039 int err; 1040 1041 if (ci->ci_flags & CPUF_PRIMARY) 1042 return true; 1043 if (ci->ci_data.cpu_idlelwp == NULL) 1044 return true; 1045 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1046 return true; 1047 1048 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1049 1050 if (sc->sc_wasonline) { 1051 mutex_enter(&cpu_lock); 1052 err = cpu_setstate(ci, false); 1053 mutex_exit(&cpu_lock); 1054 1055 if (err) 1056 return false; 1057 } 1058 1059 return true; 1060 } 1061 1062 static bool 1063 cpu_resume(device_t dv, const pmf_qual_t *qual) 1064 { 1065 struct cpu_softc *sc = device_private(dv); 1066 struct cpu_info *ci = sc->sc_info; 1067 int err = 0; 1068 1069 if (ci->ci_flags & CPUF_PRIMARY) 1070 return true; 1071 if (ci->ci_data.cpu_idlelwp == NULL) 1072 return true; 1073 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1074 return true; 1075 1076 if (sc->sc_wasonline) { 1077 mutex_enter(&cpu_lock); 1078 err = cpu_setstate(ci, true); 1079 mutex_exit(&cpu_lock); 1080 } 1081 1082 return err == 0; 1083 } 1084 #endif 1085 1086 void 1087 cpu_get_tsc_freq(struct cpu_info *ci) 1088 { 1089 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1090 delay(1000000); 1091 uint64_t freq = 1000000000ULL << 32; 1092 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1093 if ( tinfo->tsc_shift < 0 ) 1094 freq = freq << -tinfo->tsc_shift; 1095 else 1096 freq = freq >> tinfo->tsc_shift; 1097 ci->ci_data.cpu_cc_freq = freq; 1098 } 1099 1100 void 1101 x86_cpu_idle_xen(void) 1102 { 1103 struct cpu_info *ci = curcpu(); 1104 1105 KASSERT(ci->ci_ilevel == IPL_NONE); 1106 1107 x86_disable_intr(); 1108 if (!__predict_false(ci->ci_want_resched)) { 1109 idle_block(); 1110 } else { 1111 x86_enable_intr(); 1112 } 1113 } 1114
Indexes created Tue Sep 23 01:09:51 GMT 2025