cpu.c revision 1.52
1 /* $NetBSD: cpu.c,v 1.52 2010/11/14 13:43:04 bouyer Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.52 2010/11/14 13:43:04 bouyer Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm.h> 90 91 #include <machine/cpufunc.h> 92 #include <machine/cpuvar.h> 93 #include <machine/pmap.h> 94 #include <machine/vmparam.h> 95 #include <machine/mpbiosvar.h> 96 #include <machine/pcb.h> 97 #include <machine/specialreg.h> 98 #include <machine/segments.h> 99 #include <machine/gdt.h> 100 #include <machine/mtrr.h> 101 #include <machine/pio.h> 102 103 #include <xen/vcpuvar.h> 104 105 #if NLAPIC > 0 106 #include <machine/apicvar.h> 107 #include <machine/i82489reg.h> 108 #include <machine/i82489var.h> 109 #endif 110 111 #include <dev/ic/mc146818reg.h> 112 #include <dev/isa/isareg.h> 113 114 #if MAXCPUS > 32 115 #error cpu_info contains 32bit bitmasks 116 #endif 117 118 int cpu_match(device_t, cfdata_t, void *); 119 void cpu_attach(device_t, device_t, void *); 120 int vcpu_match(device_t, cfdata_t, void *); 121 void vcpu_attach(device_t, device_t, void *); 122 void cpu_attach_common(device_t, device_t, void *); 123 void cpu_offline_md(void); 124 125 struct cpu_softc { 126 device_t sc_dev; /* device tree glue */ 127 struct cpu_info *sc_info; /* pointer to CPU info */ 128 bool sc_wasonline; 129 }; 130 131 int mp_cpu_start(struct cpu_info *, paddr_t); 132 void mp_cpu_start_cleanup(struct cpu_info *); 133 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 134 mp_cpu_start_cleanup }; 135 136 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 137 cpu_match, cpu_attach, NULL, NULL); 138 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 139 vcpu_match, vcpu_attach, NULL, NULL); 140 141 /* 142 * Statically-allocated CPU info for the primary CPU (or the only 143 * CPU, on uniprocessors). The CPU info list is initialized to 144 * point at it. 145 */ 146 #ifdef TRAPLOG 147 #include <machine/tlog.h> 148 struct tlog tlog_primary; 149 #endif 150 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 151 .ci_dev = 0, 152 .ci_self = &cpu_info_primary, 153 .ci_idepth = -1, 154 .ci_curlwp = &lwp0, 155 .ci_curldt = -1, 156 #ifdef TRAPLOG 157 .ci_tlog = &tlog_primary, 158 #endif 159 160 }; 161 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 162 .ci_dev = 0, 163 .ci_self = &phycpu_info_primary, 164 }; 165 166 struct cpu_info *cpu_info_list = &cpu_info_primary; 167 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 168 169 static void cpu_set_tss_gates(struct cpu_info *ci); 170 171 uint32_t cpus_attached = 0; 172 uint32_t cpus_running = 0; 173 174 uint32_t phycpus_attached = 0; 175 uint32_t phycpus_running = 0; 176 177 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 178 * [0] basic features %edx 179 * [1] basic features %ecx 180 * [2] extended features %edx 181 * [3] extended features %ecx 182 * [4] VIA padlock features 183 */ 184 185 bool x86_mp_online; 186 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 187 188 #if defined(MULTIPROCESSOR) 189 void cpu_hatch(void *); 190 static void cpu_boot_secondary(struct cpu_info *ci); 191 static void cpu_start_secondary(struct cpu_info *ci); 192 static void cpu_copy_trampoline(void); 193 194 /* 195 * Runs once per boot once multiprocessor goo has been detected and 196 * the local APIC on the boot processor has been mapped. 197 * 198 * Called from lapic_boot_init() (from mpbios_scan()). 199 */ 200 void 201 cpu_init_first(void) 202 { 203 204 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 205 cpu_copy_trampoline(); 206 } 207 #endif /* MULTIPROCESSOR */ 208 209 int 210 cpu_match(device_t parent, cfdata_t match, void *aux) 211 { 212 213 return 1; 214 } 215 216 void 217 cpu_attach(device_t parent, device_t self, void *aux) 218 { 219 struct cpu_softc *sc = device_private(self); 220 struct cpu_attach_args *caa = aux; 221 struct cpu_info *ci; 222 uintptr_t ptr; 223 static int nphycpu = 0; 224 225 sc->sc_dev = self; 226 227 if (phycpus_attached == ~0) { 228 aprint_error(": increase MAXCPUS\n"); 229 return; 230 } 231 232 /* 233 * If we're an Application Processor, allocate a cpu_info 234 * If we're the first attached CPU use the primary cpu_info, 235 * otherwise allocate a new one 236 */ 237 aprint_naive("\n"); 238 aprint_normal("\n"); 239 if (nphycpu > 0) { 240 struct cpu_info *tmp; 241 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 242 KM_SLEEP); 243 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 244 ci->ci_curldt = -1; 245 246 tmp = phycpu_info_list; 247 while (tmp->ci_next) 248 tmp = tmp->ci_next; 249 250 tmp->ci_next = ci; 251 } else { 252 ci = &phycpu_info_primary; 253 } 254 255 ci->ci_self = ci; 256 sc->sc_info = ci; 257 258 ci->ci_dev = self; 259 ci->ci_acpiid = caa->cpu_id; 260 ci->ci_cpuid = caa->cpu_number; 261 ci->ci_vcpu = NULL; 262 ci->ci_index = nphycpu++; 263 ci->ci_cpumask = (1 << cpu_index(ci)); 264 265 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 266 267 if (!pmf_device_register(self, NULL, NULL)) 268 aprint_error_dev(self, "couldn't establish power handler\n"); 269 270 return; 271 } 272 273 int 274 vcpu_match(device_t parent, cfdata_t match, void *aux) 275 { 276 struct vcpu_attach_args *vcaa = aux; 277 278 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 279 return 1; 280 return 0; 281 } 282 283 void 284 vcpu_attach(device_t parent, device_t self, void *aux) 285 { 286 struct vcpu_attach_args *vcaa = aux; 287 288 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 289 } 290 291 static void 292 cpu_vm_init(struct cpu_info *ci) 293 { 294 int ncolors = 2, i; 295 296 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 297 struct x86_cache_info *cai; 298 int tcolors; 299 300 cai = &ci->ci_cinfo[i]; 301 302 tcolors = atop(cai->cai_totalsize); 303 switch(cai->cai_associativity) { 304 case 0xff: 305 tcolors = 1; /* fully associative */ 306 break; 307 case 0: 308 case 1: 309 break; 310 default: 311 tcolors /= cai->cai_associativity; 312 } 313 ncolors = max(ncolors, tcolors); 314 } 315 316 /* 317 * Knowing the size of the largest cache on this CPU, re-color 318 * our pages. 319 */ 320 if (ncolors <= uvmexp.ncolors) 321 return; 322 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 323 uvm_page_recolor(ncolors); 324 } 325 326 void 327 cpu_attach_common(device_t parent, device_t self, void *aux) 328 { 329 struct cpu_softc *sc = device_private(self); 330 struct cpu_attach_args *caa = aux; 331 struct cpu_info *ci; 332 uintptr_t ptr; 333 int cpunum = caa->cpu_number; 334 static bool again = false; 335 336 sc->sc_dev = self; 337 338 /* 339 * If we're an Application Processor, allocate a cpu_info 340 * structure, otherwise use the primary's. 341 */ 342 if (caa->cpu_role == CPU_ROLE_AP) { 343 aprint_naive(": Application Processor\n"); 344 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 345 KM_SLEEP); 346 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 347 memset(ci, 0, sizeof(*ci)); 348 #ifdef TRAPLOG 349 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 350 #endif 351 } else { 352 aprint_naive(": %s Processor\n", 353 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 354 ci = &cpu_info_primary; 355 #if NLAPIC > 0 356 if (cpunum != lapic_cpu_number()) { 357 /* XXX should be done earlier */ 358 uint32_t reg; 359 aprint_verbose("\n"); 360 aprint_verbose_dev(self, "running CPU at apic %d" 361 " instead of at expected %d", lapic_cpu_number(), 362 cpunum); 363 reg = i82489_readreg(LAPIC_ID); 364 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 365 (cpunum << LAPIC_ID_SHIFT)); 366 } 367 if (cpunum != lapic_cpu_number()) { 368 aprint_error_dev(self, "unable to reset apic id\n"); 369 } 370 #endif 371 } 372 373 ci->ci_self = ci; 374 sc->sc_info = ci; 375 ci->ci_dev = self; 376 ci->ci_cpuid = cpunum; 377 378 KASSERT(HYPERVISOR_shared_info != NULL); 379 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 380 381 ci->ci_func = caa->cpu_func; 382 383 /* Must be called before mi_cpu_attach(). */ 384 cpu_vm_init(ci); 385 386 if (caa->cpu_role == CPU_ROLE_AP) { 387 int error; 388 389 error = mi_cpu_attach(ci); 390 if (error != 0) { 391 aprint_normal("\n"); 392 aprint_error_dev(self, 393 "mi_cpu_attach failed with %d\n", error); 394 return; 395 } 396 } else { 397 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 398 } 399 400 ci->ci_cpumask = (1 << cpu_index(ci)); 401 pmap_reference(pmap_kernel()); 402 ci->ci_pmap = pmap_kernel(); 403 ci->ci_tlbstate = TLBSTATE_STALE; 404 405 /* 406 * Boot processor may not be attached first, but the below 407 * must be done to allow booting other processors. 408 */ 409 if (!again) { 410 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 411 /* Basic init. */ 412 cpu_intr_init(ci); 413 cpu_get_tsc_freq(ci); 414 cpu_init(ci); 415 cpu_set_tss_gates(ci); 416 pmap_cpu_init_late(ci); 417 #if NLAPIC > 0 418 if (caa->cpu_role != CPU_ROLE_SP) { 419 /* Enable lapic. */ 420 lapic_enable(); 421 lapic_set_lvt(); 422 lapic_calibrate_timer(); 423 } 424 #endif 425 /* Make sure DELAY() is initialized. */ 426 DELAY(1); 427 again = true; 428 } 429 430 /* further PCB init done later. */ 431 432 switch (caa->cpu_role) { 433 case CPU_ROLE_SP: 434 atomic_or_32(&ci->ci_flags, CPUF_SP); 435 cpu_identify(ci); 436 #if 0 437 x86_errata(); 438 #endif 439 x86_cpu_idle_init(); 440 break; 441 442 case CPU_ROLE_BP: 443 atomic_or_32(&ci->ci_flags, CPUF_BSP); 444 cpu_identify(ci); 445 cpu_init(ci); 446 #if 0 447 x86_errata(); 448 #endif 449 x86_cpu_idle_init(); 450 break; 451 452 case CPU_ROLE_AP: 453 /* 454 * report on an AP 455 */ 456 457 #if defined(MULTIPROCESSOR) 458 cpu_intr_init(ci); 459 gdt_alloc_cpu(ci); 460 cpu_set_tss_gates(ci); 461 pmap_cpu_init_early(ci); 462 pmap_cpu_init_late(ci); 463 cpu_start_secondary(ci); 464 if (ci->ci_flags & CPUF_PRESENT) { 465 struct cpu_info *tmp; 466 467 identifycpu(ci); 468 tmp = cpu_info_list; 469 while (tmp->ci_next) 470 tmp = tmp->ci_next; 471 472 tmp->ci_next = ci; 473 } 474 #else 475 aprint_error_dev(self, "not started\n"); 476 #endif 477 break; 478 479 default: 480 aprint_normal("\n"); 481 panic("unknown processor type??\n"); 482 } 483 484 pat_init(ci); 485 atomic_or_32(&cpus_attached, ci->ci_cpumask); 486 487 #if 0 488 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 489 aprint_error_dev(self, "couldn't establish power handler\n"); 490 #endif 491 492 #if defined(MULTIPROCESSOR) 493 if (mp_verbose) { 494 struct lwp *l = ci->ci_data.cpu_idlelwp; 495 struct pcb *pcb = lwp_getpcb(l); 496 497 aprint_verbose_dev(self, 498 "idle lwp at %p, idle sp at 0x%p\n", 499 l, 500 #ifdef i386 501 (void *)pcb->pcb_esp 502 #else 503 (void *)pcb->pcb_rsp 504 #endif 505 ); 506 507 } 508 #endif 509 } 510 511 /* 512 * Initialize the processor appropriately. 513 */ 514 515 void 516 cpu_init(struct cpu_info *ci) 517 { 518 519 /* 520 * On a P6 or above, enable global TLB caching if the 521 * hardware supports it. 522 */ 523 if (cpu_feature[0] & CPUID_PGE) 524 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 525 526 #ifdef XXXMTRR 527 /* 528 * On a P6 or above, initialize MTRR's if the hardware supports them. 529 */ 530 if (cpu_feature[0] & CPUID_MTRR) { 531 if ((ci->ci_flags & CPUF_AP) == 0) 532 i686_mtrr_init_first(); 533 mtrr_init_cpu(ci); 534 } 535 #endif 536 /* 537 * If we have FXSAVE/FXRESTOR, use them. 538 */ 539 if (cpu_feature[0] & CPUID_FXSR) { 540 lcr4(rcr4() | CR4_OSFXSR); 541 542 /* 543 * If we have SSE/SSE2, enable XMM exceptions. 544 */ 545 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 546 lcr4(rcr4() | CR4_OSXMMEXCPT); 547 } 548 549 #ifdef __x86_64__ 550 /* No user PGD mapped for this CPU yet */ 551 ci->ci_xen_current_user_pgd = 0; 552 #endif 553 554 atomic_or_32(&cpus_running, ci->ci_cpumask); 555 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 556 } 557 558 559 #ifdef MULTIPROCESSOR 560 void 561 cpu_boot_secondary_processors(void) 562 { 563 struct cpu_info *ci; 564 u_long i; 565 566 for (i = 0; i < maxcpus; i++) { 567 ci = cpu_lookup(i); 568 if (ci == NULL) 569 continue; 570 if (ci->ci_data.cpu_idlelwp == NULL) 571 continue; 572 if ((ci->ci_flags & CPUF_PRESENT) == 0) 573 continue; 574 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 575 continue; 576 cpu_boot_secondary(ci); 577 } 578 579 x86_mp_online = true; 580 } 581 582 static void 583 cpu_init_idle_lwp(struct cpu_info *ci) 584 { 585 struct lwp *l = ci->ci_data.cpu_idlelwp; 586 struct pcb *pcb = lwp_getpcb(l); 587 588 pcb->pcb_cr0 = rcr0(); 589 } 590 591 void 592 cpu_init_idle_lwps(void) 593 { 594 struct cpu_info *ci; 595 u_long i; 596 597 for (i = 0; i < maxcpus; i++) { 598 ci = cpu_lookup(i); 599 if (ci == NULL) 600 continue; 601 if (ci->ci_data.cpu_idlelwp == NULL) 602 continue; 603 if ((ci->ci_flags & CPUF_PRESENT) == 0) 604 continue; 605 cpu_init_idle_lwp(ci); 606 } 607 } 608 609 void 610 cpu_start_secondary(struct cpu_info *ci) 611 { 612 int i; 613 struct pmap *kpm = pmap_kernel(); 614 extern uint32_t mp_pdirpa; 615 616 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 617 618 atomic_or_32(&ci->ci_flags, CPUF_AP); 619 620 aprint_debug_dev(ci->ci_dev, "starting\n"); 621 622 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 623 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 624 return; 625 626 /* 627 * wait for it to become ready 628 */ 629 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 630 #ifdef MPDEBUG 631 extern int cpu_trace[3]; 632 static int otrace[3]; 633 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 634 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 635 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 636 memcpy(otrace, cpu_trace, sizeof(otrace)); 637 } 638 #endif 639 delay(10); 640 } 641 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 642 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 643 #if defined(MPDEBUG) && defined(DDB) 644 printf("dropping into debugger; continue from here to resume boot\n"); 645 Debugger(); 646 #endif 647 } 648 649 CPU_START_CLEANUP(ci); 650 } 651 652 void 653 cpu_boot_secondary(struct cpu_info *ci) 654 { 655 int i; 656 657 atomic_or_32(&ci->ci_flags, CPUF_GO); 658 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 659 delay(10); 660 } 661 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 662 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 663 #if defined(MPDEBUG) && defined(DDB) 664 printf("dropping into debugger; continue from here to resume boot\n"); 665 Debugger(); 666 #endif 667 } 668 } 669 670 /* 671 * The CPU ends up here when its ready to run 672 * This is called from code in mptramp.s; at this point, we are running 673 * in the idle pcb/idle stack of the new CPU. When this function returns, 674 * this processor will enter the idle loop and start looking for work. 675 * 676 * XXX should share some of this with init386 in machdep.c 677 */ 678 void 679 cpu_hatch(void *v) 680 { 681 struct cpu_info *ci = (struct cpu_info *)v; 682 struct pcb *pcb; 683 int s, i; 684 685 cpu_probe(ci); 686 687 cpu_feature[0] &= ~CPUID_FEAT_BLACKLIST; 688 cpu_feature[2] &= ~CPUID_FEAT_EXT_BLACKLIST; 689 690 cpu_init_msrs(ci, true); 691 692 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 693 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 694 while ((ci->ci_flags & CPUF_GO) == 0) { 695 /* Don't use delay, boot CPU may be patching the text. */ 696 for (i = 10000; i != 0; i--) 697 x86_pause(); 698 } 699 700 /* Because the text may have been patched in x86_patch(). */ 701 wbinvd(); 702 x86_flush(); 703 704 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 705 706 pcb = lwp_getpcb(curlwp); 707 lcr3(pmap_kernel()->pm_pdirpa); 708 pcb->pcb_cr3 = pmap_kernel()->pm_pdirpa; 709 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 710 lcr0(pcb->pcb_cr0); 711 712 cpu_init_idt(); 713 gdt_init_cpu(ci); 714 lapic_enable(); 715 lapic_set_lvt(); 716 lapic_initclocks(); 717 718 #ifdef i386 719 npxinit(ci); 720 #else 721 fpuinit(ci); 722 #endif 723 724 lldt(GSEL(GLDT_SEL, SEL_KPL)); 725 ltr(ci->ci_tss_sel); 726 727 cpu_init(ci); 728 cpu_get_tsc_freq(ci); 729 730 s = splhigh(); 731 #ifdef i386 732 lapic_tpr = 0; 733 #else 734 lcr8(0); 735 #endif 736 x86_enable_intr(); 737 splx(s); 738 #if 0 739 x86_errata(); 740 #endif 741 742 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 743 (long)ci->ci_cpuid); 744 } 745 746 #if defined(DDB) 747 748 #include <ddb/db_output.h> 749 #include <machine/db_machdep.h> 750 751 /* 752 * Dump CPU information from ddb. 753 */ 754 void 755 cpu_debug_dump(void) 756 { 757 struct cpu_info *ci; 758 CPU_INFO_ITERATOR cii; 759 760 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 761 for (CPU_INFO_FOREACH(cii, ci)) { 762 db_printf("%p %s %ld %x %x %10p %10p\n", 763 ci, 764 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 765 (long)ci->ci_cpuid, 766 ci->ci_flags, ci->ci_ipis, 767 ci->ci_curlwp, 768 ci->ci_fpcurlwp); 769 } 770 } 771 #endif /* DDB */ 772 773 static void 774 cpu_copy_trampoline(void) 775 { 776 /* 777 * Copy boot code. 778 */ 779 extern u_char cpu_spinup_trampoline[]; 780 extern u_char cpu_spinup_trampoline_end[]; 781 782 vaddr_t mp_trampoline_vaddr; 783 784 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 785 UVM_KMF_VAONLY); 786 787 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 788 VM_PROT_READ | VM_PROT_WRITE, 0); 789 pmap_update(pmap_kernel()); 790 memcpy((void *)mp_trampoline_vaddr, 791 cpu_spinup_trampoline, 792 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 793 794 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 795 pmap_update(pmap_kernel()); 796 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 797 } 798 799 #endif /* MULTIPROCESSOR */ 800 801 #ifdef i386 802 #if 0 803 static void 804 tss_init(struct i386tss *tss, void *stack, void *func) 805 { 806 memset(tss, 0, sizeof *tss); 807 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 808 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 809 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 810 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 811 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 812 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 813 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 814 tss->tss_esp = (int)((char *)stack + USPACE - 16); 815 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 816 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 817 tss->__tss_eip = (int)func; 818 } 819 #endif 820 821 /* XXX */ 822 #define IDTVEC(name) __CONCAT(X, name) 823 typedef void (vector)(void); 824 extern vector IDTVEC(tss_trap08); 825 #ifdef DDB 826 extern vector Xintrddbipi; 827 extern int ddb_vec; 828 #endif 829 830 static void 831 cpu_set_tss_gates(struct cpu_info *ci) 832 { 833 #if 0 834 struct segment_descriptor sd; 835 836 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 837 UVM_KMF_WIRED); 838 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 839 IDTVEC(tss_trap08)); 840 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 841 SDT_SYS386TSS, SEL_KPL, 0, 0); 842 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 843 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 844 GSEL(GTRAPTSS_SEL, SEL_KPL)); 845 #endif 846 847 #if defined(DDB) && defined(MULTIPROCESSOR) 848 /* 849 * Set up separate handler for the DDB IPI, so that it doesn't 850 * stomp on a possibly corrupted stack. 851 * 852 * XXX overwriting the gate set in db_machine_init. 853 * Should rearrange the code so that it's set only once. 854 */ 855 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 856 UVM_KMF_WIRED); 857 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 858 Xintrddbipi); 859 860 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 861 SDT_SYS386TSS, SEL_KPL, 0, 0); 862 ci->ci_gdt[GIPITSS_SEL].sd = sd; 863 864 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 865 GSEL(GIPITSS_SEL, SEL_KPL)); 866 #endif 867 } 868 #else 869 static void 870 cpu_set_tss_gates(struct cpu_info *ci) 871 { 872 873 } 874 #endif /* i386 */ 875 876 int 877 mp_cpu_start(struct cpu_info *ci, paddr_t target) 878 { 879 #if 0 880 #if NLAPIC > 0 881 int error; 882 #endif 883 unsigned short dwordptr[2]; 884 885 /* 886 * Bootstrap code must be addressable in real mode 887 * and it must be page aligned. 888 */ 889 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 890 891 /* 892 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 893 */ 894 895 outb(IO_RTC, NVRAM_RESET); 896 outb(IO_RTC+1, NVRAM_RESET_JUMP); 897 898 /* 899 * "and the warm reset vector (DWORD based at 40:67) to point 900 * to the AP startup code ..." 901 */ 902 903 dwordptr[0] = 0; 904 dwordptr[1] = target >> 4; 905 906 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 907 pmap_update(pmap_kernel()); 908 909 memcpy ((uint8_t *) 0x467, dwordptr, 4); 910 911 pmap_kremove (0, PAGE_SIZE); 912 pmap_update(pmap_kernel()); 913 914 #if NLAPIC > 0 915 /* 916 * ... prior to executing the following sequence:" 917 */ 918 919 if (ci->ci_flags & CPUF_AP) { 920 if ((error = x86_ipi_init(ci->ci_cpuid)) != 0) 921 return error; 922 923 delay(10000); 924 925 if (cpu_feature & CPUID_APIC) { 926 error = x86_ipi_init(ci->ci_cpuid); 927 if (error != 0) { 928 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 929 __func__); 930 return error; 931 } 932 933 delay(10000); 934 935 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 936 LAPIC_DLMODE_STARTUP); 937 if (error != 0) { 938 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 939 __func__); 940 return error; 941 } 942 delay(200); 943 944 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 945 LAPIC_DLMODE_STARTUP); 946 if (error != 0) { 947 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 948 __func__); 949 return error; 950 } 951 delay(200); 952 } 953 } 954 #endif 955 #endif /* 0 */ 956 return 0; 957 } 958 959 void 960 mp_cpu_start_cleanup(struct cpu_info *ci) 961 { 962 #if 0 963 /* 964 * Ensure the NVRAM reset byte contains something vaguely sane. 965 */ 966 967 outb(IO_RTC, NVRAM_RESET); 968 outb(IO_RTC+1, NVRAM_RESET_RST); 969 #endif 970 } 971 972 void 973 cpu_init_msrs(struct cpu_info *ci, bool full) 974 { 975 #ifdef __x86_64__ 976 if (full) { 977 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 978 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 979 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 980 } 981 #endif /* __x86_64__ */ 982 983 if (cpu_feature[2] & CPUID_NOX) 984 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 985 } 986 987 void 988 cpu_offline_md(void) 989 { 990 int s; 991 992 s = splhigh(); 993 #ifdef __i386__ 994 npxsave_cpu(true); 995 #else 996 fpusave_cpu(true); 997 #endif 998 splx(s); 999 } 1000 1001 #if 0 1002 /* XXX joerg restructure and restart CPUs individually */ 1003 static bool 1004 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1005 { 1006 struct cpu_softc *sc = device_private(dv); 1007 struct cpu_info *ci = sc->sc_info; 1008 int err; 1009 1010 if (ci->ci_flags & CPUF_PRIMARY) 1011 return true; 1012 if (ci->ci_data.cpu_idlelwp == NULL) 1013 return true; 1014 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1015 return true; 1016 1017 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1018 1019 if (sc->sc_wasonline) { 1020 mutex_enter(&cpu_lock); 1021 err = cpu_setstate(ci, false); 1022 mutex_exit(&cpu_lock); 1023 1024 if (err) 1025 return false; 1026 } 1027 1028 return true; 1029 } 1030 1031 static bool 1032 cpu_resume(device_t dv, const pmf_qual_t *qual) 1033 { 1034 struct cpu_softc *sc = device_private(dv); 1035 struct cpu_info *ci = sc->sc_info; 1036 int err = 0; 1037 1038 if (ci->ci_flags & CPUF_PRIMARY) 1039 return true; 1040 if (ci->ci_data.cpu_idlelwp == NULL) 1041 return true; 1042 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1043 return true; 1044 1045 if (sc->sc_wasonline) { 1046 mutex_enter(&cpu_lock); 1047 err = cpu_setstate(ci, true); 1048 mutex_exit(&cpu_lock); 1049 } 1050 1051 return err == 0; 1052 } 1053 #endif 1054 1055 void 1056 cpu_get_tsc_freq(struct cpu_info *ci) 1057 { 1058 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1059 delay(1000000); 1060 uint64_t freq = 1000000000ULL << 32; 1061 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1062 if ( tinfo->tsc_shift < 0 ) 1063 freq = freq << -tinfo->tsc_shift; 1064 else 1065 freq = freq >> tinfo->tsc_shift; 1066 ci->ci_data.cpu_cc_freq = freq; 1067 } 1068 1069 void 1070 x86_cpu_idle_xen(void) 1071 { 1072 struct cpu_info *ci = curcpu(); 1073 1074 KASSERT(ci->ci_ilevel == IPL_NONE); 1075 1076 x86_disable_intr(); 1077 if (!__predict_false(ci->ci_want_resched)) { 1078 idle_block(); 1079 } else { 1080 x86_enable_intr(); 1081 } 1082 } 1083 1084 /* 1085 * Loads pmap for the current CPU. 1086 */ 1087 void 1088 cpu_load_pmap(struct pmap *pmap) 1089 { 1090 #ifdef i386 1091 #ifdef PAE 1092 int i, s; 1093 struct cpu_info *ci; 1094 1095 s = splvm(); /* just to be safe */ 1096 ci = curcpu(); 1097 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1098 /* don't update the kernel L3 slot */ 1099 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1100 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1101 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1102 } 1103 splx(s); 1104 tlbflush(); 1105 #else /* PAE */ 1106 lcr3(pmap_pdirpa(pmap, 0)); 1107 #endif /* PAE */ 1108 #endif /* i386 */ 1109 1110 #ifdef __x86_64__ 1111 int i, s; 1112 pd_entry_t *old_pgd, *new_pgd; 1113 paddr_t addr; 1114 struct cpu_info *ci; 1115 1116 /* kernel pmap always in cr3 and should never go in user cr3 */ 1117 if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) { 1118 ci = curcpu(); 1119 /* 1120 * Map user space address in kernel space and load 1121 * user cr3 1122 */ 1123 s = splvm(); 1124 new_pgd = pmap->pm_pdir; 1125 old_pgd = pmap_kernel()->pm_pdir; 1126 addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0)); 1127 for (i = 0; i < PDIR_SLOT_PTE; 1128 i++, addr += sizeof(pd_entry_t)) { 1129 if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V)) 1130 xpq_queue_pte_update(addr, new_pgd[i]); 1131 } 1132 tlbflush(); 1133 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1134 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1135 splx(s); 1136 } 1137 #endif /* __x86_64__ */ 1138 } 1139
Indexes created Tue Sep 23 02:09:52 GMT 2025