cpu.c revision 1.56
1 /* $NetBSD: cpu.c,v 1.56 2011/02/26 14:43:18 jruoho Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.56 2011/02/26 14:43:18 jruoho Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm.h> 90 91 #include <machine/cpufunc.h> 92 #include <machine/cpuvar.h> 93 #include <machine/pmap.h> 94 #include <machine/vmparam.h> 95 #include <machine/mpbiosvar.h> 96 #include <machine/pcb.h> 97 #include <machine/specialreg.h> 98 #include <machine/segments.h> 99 #include <machine/gdt.h> 100 #include <machine/mtrr.h> 101 #include <machine/pio.h> 102 103 #include <xen/vcpuvar.h> 104 105 #if NLAPIC > 0 106 #include <machine/apicvar.h> 107 #include <machine/i82489reg.h> 108 #include <machine/i82489var.h> 109 #endif 110 111 #include <dev/ic/mc146818reg.h> 112 #include <dev/isa/isareg.h> 113 114 #if MAXCPUS > 32 115 #error cpu_info contains 32bit bitmasks 116 #endif 117 118 static int cpu_match(device_t, cfdata_t, void *); 119 static void cpu_attach(device_t, device_t, void *); 120 static void cpu_defer(device_t); 121 static int cpu_rescan(device_t, const char *, const int *); 122 static void cpu_childdetached(device_t, device_t); 123 static int vcpu_match(device_t, cfdata_t, void *); 124 static void vcpu_attach(device_t, device_t, void *); 125 static void cpu_attach_common(device_t, device_t, void *); 126 void cpu_offline_md(void); 127 128 struct cpu_softc { 129 device_t sc_dev; /* device tree glue */ 130 struct cpu_info *sc_info; /* pointer to CPU info */ 131 bool sc_wasonline; 132 }; 133 134 int mp_cpu_start(struct cpu_info *, paddr_t); 135 void mp_cpu_start_cleanup(struct cpu_info *); 136 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 137 mp_cpu_start_cleanup }; 138 139 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 140 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 141 142 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 143 vcpu_match, vcpu_attach, NULL, NULL); 144 145 /* 146 * Statically-allocated CPU info for the primary CPU (or the only 147 * CPU, on uniprocessors). The CPU info list is initialized to 148 * point at it. 149 */ 150 #ifdef TRAPLOG 151 #include <machine/tlog.h> 152 struct tlog tlog_primary; 153 #endif 154 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 155 .ci_dev = 0, 156 .ci_self = &cpu_info_primary, 157 .ci_idepth = -1, 158 .ci_curlwp = &lwp0, 159 .ci_curldt = -1, 160 #ifdef TRAPLOG 161 .ci_tlog = &tlog_primary, 162 #endif 163 164 }; 165 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 166 .ci_dev = 0, 167 .ci_self = &phycpu_info_primary, 168 }; 169 170 struct cpu_info *cpu_info_list = &cpu_info_primary; 171 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 172 173 static void cpu_set_tss_gates(struct cpu_info *ci); 174 175 uint32_t cpus_attached = 0; 176 uint32_t cpus_running = 0; 177 178 uint32_t phycpus_attached = 0; 179 uint32_t phycpus_running = 0; 180 181 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 182 * [0] basic features %edx 183 * [1] basic features %ecx 184 * [2] extended features %edx 185 * [3] extended features %ecx 186 * [4] VIA padlock features 187 */ 188 189 bool x86_mp_online; 190 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 191 192 #if defined(MULTIPROCESSOR) 193 void cpu_hatch(void *); 194 static void cpu_boot_secondary(struct cpu_info *ci); 195 static void cpu_start_secondary(struct cpu_info *ci); 196 static void cpu_copy_trampoline(void); 197 198 /* 199 * Runs once per boot once multiprocessor goo has been detected and 200 * the local APIC on the boot processor has been mapped. 201 * 202 * Called from lapic_boot_init() (from mpbios_scan()). 203 */ 204 void 205 cpu_init_first(void) 206 { 207 208 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 209 cpu_copy_trampoline(); 210 } 211 #endif /* MULTIPROCESSOR */ 212 213 static int 214 cpu_match(device_t parent, cfdata_t match, void *aux) 215 { 216 217 return 1; 218 } 219 220 static void 221 cpu_attach(device_t parent, device_t self, void *aux) 222 { 223 struct cpu_softc *sc = device_private(self); 224 struct cpu_attach_args *caa = aux; 225 struct cpu_info *ci; 226 uintptr_t ptr; 227 static int nphycpu = 0; 228 229 sc->sc_dev = self; 230 231 if (phycpus_attached == ~0) { 232 aprint_error(": increase MAXCPUS\n"); 233 return; 234 } 235 236 /* 237 * If we're an Application Processor, allocate a cpu_info 238 * If we're the first attached CPU use the primary cpu_info, 239 * otherwise allocate a new one 240 */ 241 aprint_naive("\n"); 242 aprint_normal("\n"); 243 if (nphycpu > 0) { 244 struct cpu_info *tmp; 245 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 246 KM_SLEEP); 247 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 248 ci->ci_curldt = -1; 249 250 tmp = phycpu_info_list; 251 while (tmp->ci_next) 252 tmp = tmp->ci_next; 253 254 tmp->ci_next = ci; 255 } else { 256 ci = &phycpu_info_primary; 257 } 258 259 ci->ci_self = ci; 260 sc->sc_info = ci; 261 262 ci->ci_dev = self; 263 ci->ci_acpiid = caa->cpu_id; 264 ci->ci_cpuid = caa->cpu_number; 265 ci->ci_vcpu = NULL; 266 ci->ci_index = nphycpu++; 267 ci->ci_cpumask = (1 << cpu_index(ci)); 268 269 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 270 271 if (!pmf_device_register(self, NULL, NULL)) 272 aprint_error_dev(self, "couldn't establish power handler\n"); 273 274 (void)config_defer(self, cpu_defer); 275 } 276 277 static void 278 cpu_defer(device_t self) 279 { 280 cpu_rescan(self, NULL, NULL); 281 } 282 283 static int 284 cpu_rescan(device_t self, const char *ifattr, const int *locators) 285 { 286 struct cpu_softc *sc = device_private(self); 287 struct cpufeature_attach_args cfaa; 288 struct cpu_info *ci = sc->sc_info; 289 290 memset(&cfaa, 0, sizeof(cfaa)); 291 cfaa.ci = ci; 292 293 if (ifattr_match(ifattr, "cpufeaturebus")) { 294 295 if (ci->ci_frequency == NULL) { 296 cfaa.name = "frequency"; 297 ci->ci_frequency = config_found_ia(self, 298 "cpufeaturebus", &cfaa, NULL); 299 } 300 } 301 302 return 0; 303 } 304 305 static void 306 cpu_childdetached(device_t self, device_t child) 307 { 308 struct cpu_softc *sc = device_private(self); 309 struct cpu_info *ci = sc->sc_info; 310 311 if (ci->ci_frequency == child) 312 ci->ci_frequency = NULL; 313 } 314 315 static int 316 vcpu_match(device_t parent, cfdata_t match, void *aux) 317 { 318 struct vcpu_attach_args *vcaa = aux; 319 320 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 321 return 1; 322 return 0; 323 } 324 325 static void 326 vcpu_attach(device_t parent, device_t self, void *aux) 327 { 328 struct vcpu_attach_args *vcaa = aux; 329 330 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 331 } 332 333 static void 334 cpu_vm_init(struct cpu_info *ci) 335 { 336 int ncolors = 2, i; 337 338 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 339 struct x86_cache_info *cai; 340 int tcolors; 341 342 cai = &ci->ci_cinfo[i]; 343 344 tcolors = atop(cai->cai_totalsize); 345 switch(cai->cai_associativity) { 346 case 0xff: 347 tcolors = 1; /* fully associative */ 348 break; 349 case 0: 350 case 1: 351 break; 352 default: 353 tcolors /= cai->cai_associativity; 354 } 355 ncolors = max(ncolors, tcolors); 356 } 357 358 /* 359 * Knowing the size of the largest cache on this CPU, re-color 360 * our pages. 361 */ 362 if (ncolors <= uvmexp.ncolors) 363 return; 364 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 365 uvm_page_recolor(ncolors); 366 } 367 368 static void 369 cpu_attach_common(device_t parent, device_t self, void *aux) 370 { 371 struct cpu_softc *sc = device_private(self); 372 struct cpu_attach_args *caa = aux; 373 struct cpu_info *ci; 374 uintptr_t ptr; 375 int cpunum = caa->cpu_number; 376 static bool again = false; 377 378 sc->sc_dev = self; 379 380 /* 381 * If we're an Application Processor, allocate a cpu_info 382 * structure, otherwise use the primary's. 383 */ 384 if (caa->cpu_role == CPU_ROLE_AP) { 385 aprint_naive(": Application Processor\n"); 386 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 387 KM_SLEEP); 388 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 389 memset(ci, 0, sizeof(*ci)); 390 #ifdef TRAPLOG 391 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 392 #endif 393 } else { 394 aprint_naive(": %s Processor\n", 395 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 396 ci = &cpu_info_primary; 397 #if NLAPIC > 0 398 if (cpunum != lapic_cpu_number()) { 399 /* XXX should be done earlier */ 400 uint32_t reg; 401 aprint_verbose("\n"); 402 aprint_verbose_dev(self, "running CPU at apic %d" 403 " instead of at expected %d", lapic_cpu_number(), 404 cpunum); 405 reg = i82489_readreg(LAPIC_ID); 406 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 407 (cpunum << LAPIC_ID_SHIFT)); 408 } 409 if (cpunum != lapic_cpu_number()) { 410 aprint_error_dev(self, "unable to reset apic id\n"); 411 } 412 #endif 413 } 414 415 ci->ci_self = ci; 416 sc->sc_info = ci; 417 ci->ci_dev = self; 418 ci->ci_cpuid = cpunum; 419 420 KASSERT(HYPERVISOR_shared_info != NULL); 421 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 422 423 ci->ci_func = caa->cpu_func; 424 425 /* Must be called before mi_cpu_attach(). */ 426 cpu_vm_init(ci); 427 428 if (caa->cpu_role == CPU_ROLE_AP) { 429 int error; 430 431 error = mi_cpu_attach(ci); 432 if (error != 0) { 433 aprint_normal("\n"); 434 aprint_error_dev(self, 435 "mi_cpu_attach failed with %d\n", error); 436 return; 437 } 438 } else { 439 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 440 } 441 442 ci->ci_cpumask = (1 << cpu_index(ci)); 443 pmap_reference(pmap_kernel()); 444 ci->ci_pmap = pmap_kernel(); 445 ci->ci_tlbstate = TLBSTATE_STALE; 446 447 /* 448 * Boot processor may not be attached first, but the below 449 * must be done to allow booting other processors. 450 */ 451 if (!again) { 452 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 453 /* Basic init. */ 454 cpu_intr_init(ci); 455 cpu_get_tsc_freq(ci); 456 cpu_init(ci); 457 cpu_set_tss_gates(ci); 458 pmap_cpu_init_late(ci); 459 #if NLAPIC > 0 460 if (caa->cpu_role != CPU_ROLE_SP) { 461 /* Enable lapic. */ 462 lapic_enable(); 463 lapic_set_lvt(); 464 lapic_calibrate_timer(); 465 } 466 #endif 467 /* Make sure DELAY() is initialized. */ 468 DELAY(1); 469 again = true; 470 } 471 472 /* further PCB init done later. */ 473 474 switch (caa->cpu_role) { 475 case CPU_ROLE_SP: 476 atomic_or_32(&ci->ci_flags, CPUF_SP); 477 cpu_identify(ci); 478 #if 0 479 x86_errata(); 480 #endif 481 x86_cpu_idle_init(); 482 break; 483 484 case CPU_ROLE_BP: 485 atomic_or_32(&ci->ci_flags, CPUF_BSP); 486 cpu_identify(ci); 487 cpu_init(ci); 488 #if 0 489 x86_errata(); 490 #endif 491 x86_cpu_idle_init(); 492 break; 493 494 case CPU_ROLE_AP: 495 /* 496 * report on an AP 497 */ 498 499 #if defined(MULTIPROCESSOR) 500 cpu_intr_init(ci); 501 gdt_alloc_cpu(ci); 502 cpu_set_tss_gates(ci); 503 pmap_cpu_init_early(ci); 504 pmap_cpu_init_late(ci); 505 cpu_start_secondary(ci); 506 if (ci->ci_flags & CPUF_PRESENT) { 507 struct cpu_info *tmp; 508 509 identifycpu(ci); 510 tmp = cpu_info_list; 511 while (tmp->ci_next) 512 tmp = tmp->ci_next; 513 514 tmp->ci_next = ci; 515 } 516 #else 517 aprint_error_dev(self, "not started\n"); 518 #endif 519 break; 520 521 default: 522 aprint_normal("\n"); 523 panic("unknown processor type??\n"); 524 } 525 526 pat_init(ci); 527 atomic_or_32(&cpus_attached, ci->ci_cpumask); 528 529 #if 0 530 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 531 aprint_error_dev(self, "couldn't establish power handler\n"); 532 #endif 533 534 #if defined(MULTIPROCESSOR) 535 if (mp_verbose) { 536 struct lwp *l = ci->ci_data.cpu_idlelwp; 537 struct pcb *pcb = lwp_getpcb(l); 538 539 aprint_verbose_dev(self, 540 "idle lwp at %p, idle sp at 0x%p\n", 541 l, 542 #ifdef i386 543 (void *)pcb->pcb_esp 544 #else 545 (void *)pcb->pcb_rsp 546 #endif 547 ); 548 549 } 550 #endif 551 } 552 553 /* 554 * Initialize the processor appropriately. 555 */ 556 557 void 558 cpu_init(struct cpu_info *ci) 559 { 560 561 /* 562 * On a P6 or above, enable global TLB caching if the 563 * hardware supports it. 564 */ 565 if (cpu_feature[0] & CPUID_PGE) 566 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 567 568 #ifdef XXXMTRR 569 /* 570 * On a P6 or above, initialize MTRR's if the hardware supports them. 571 */ 572 if (cpu_feature[0] & CPUID_MTRR) { 573 if ((ci->ci_flags & CPUF_AP) == 0) 574 i686_mtrr_init_first(); 575 mtrr_init_cpu(ci); 576 } 577 #endif 578 /* 579 * If we have FXSAVE/FXRESTOR, use them. 580 */ 581 if (cpu_feature[0] & CPUID_FXSR) { 582 lcr4(rcr4() | CR4_OSFXSR); 583 584 /* 585 * If we have SSE/SSE2, enable XMM exceptions. 586 */ 587 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 588 lcr4(rcr4() | CR4_OSXMMEXCPT); 589 } 590 591 #ifdef __x86_64__ 592 /* No user PGD mapped for this CPU yet */ 593 ci->ci_xen_current_user_pgd = 0; 594 #endif 595 596 atomic_or_32(&cpus_running, ci->ci_cpumask); 597 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 598 } 599 600 601 #ifdef MULTIPROCESSOR 602 void 603 cpu_boot_secondary_processors(void) 604 { 605 struct cpu_info *ci; 606 u_long i; 607 608 for (i = 0; i < maxcpus; i++) { 609 ci = cpu_lookup(i); 610 if (ci == NULL) 611 continue; 612 if (ci->ci_data.cpu_idlelwp == NULL) 613 continue; 614 if ((ci->ci_flags & CPUF_PRESENT) == 0) 615 continue; 616 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 617 continue; 618 cpu_boot_secondary(ci); 619 } 620 621 x86_mp_online = true; 622 } 623 624 static void 625 cpu_init_idle_lwp(struct cpu_info *ci) 626 { 627 struct lwp *l = ci->ci_data.cpu_idlelwp; 628 struct pcb *pcb = lwp_getpcb(l); 629 630 pcb->pcb_cr0 = rcr0(); 631 } 632 633 void 634 cpu_init_idle_lwps(void) 635 { 636 struct cpu_info *ci; 637 u_long i; 638 639 for (i = 0; i < maxcpus; i++) { 640 ci = cpu_lookup(i); 641 if (ci == NULL) 642 continue; 643 if (ci->ci_data.cpu_idlelwp == NULL) 644 continue; 645 if ((ci->ci_flags & CPUF_PRESENT) == 0) 646 continue; 647 cpu_init_idle_lwp(ci); 648 } 649 } 650 651 void 652 cpu_start_secondary(struct cpu_info *ci) 653 { 654 int i; 655 struct pmap *kpm = pmap_kernel(); 656 extern uint32_t mp_pdirpa; 657 658 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 659 660 atomic_or_32(&ci->ci_flags, CPUF_AP); 661 662 aprint_debug_dev(ci->ci_dev, "starting\n"); 663 664 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 665 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) 666 return; 667 668 /* 669 * wait for it to become ready 670 */ 671 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 672 #ifdef MPDEBUG 673 extern int cpu_trace[3]; 674 static int otrace[3]; 675 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 676 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 677 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 678 memcpy(otrace, cpu_trace, sizeof(otrace)); 679 } 680 #endif 681 delay(10); 682 } 683 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 684 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 685 #if defined(MPDEBUG) && defined(DDB) 686 printf("dropping into debugger; continue from here to resume boot\n"); 687 Debugger(); 688 #endif 689 } 690 691 CPU_START_CLEANUP(ci); 692 } 693 694 void 695 cpu_boot_secondary(struct cpu_info *ci) 696 { 697 int i; 698 699 atomic_or_32(&ci->ci_flags, CPUF_GO); 700 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 701 delay(10); 702 } 703 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 704 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 705 #if defined(MPDEBUG) && defined(DDB) 706 printf("dropping into debugger; continue from here to resume boot\n"); 707 Debugger(); 708 #endif 709 } 710 } 711 712 /* 713 * The CPU ends up here when its ready to run 714 * This is called from code in mptramp.s; at this point, we are running 715 * in the idle pcb/idle stack of the new CPU. When this function returns, 716 * this processor will enter the idle loop and start looking for work. 717 * 718 * XXX should share some of this with init386 in machdep.c 719 */ 720 void 721 cpu_hatch(void *v) 722 { 723 struct cpu_info *ci = (struct cpu_info *)v; 724 struct pcb *pcb; 725 int s, i; 726 727 cpu_probe(ci); 728 729 cpu_feature[0] &= ~CPUID_FEAT_BLACKLIST; 730 cpu_feature[2] &= ~CPUID_FEAT_EXT_BLACKLIST; 731 732 cpu_init_msrs(ci, true); 733 734 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 735 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 736 while ((ci->ci_flags & CPUF_GO) == 0) { 737 /* Don't use delay, boot CPU may be patching the text. */ 738 for (i = 10000; i != 0; i--) 739 x86_pause(); 740 } 741 742 /* Because the text may have been patched in x86_patch(). */ 743 wbinvd(); 744 x86_flush(); 745 746 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 747 748 pcb = lwp_getpcb(curlwp); 749 lcr3(pmap_kernel()->pm_pdirpa); 750 pcb->pcb_cr3 = pmap_kernel()->pm_pdirpa; 751 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 752 lcr0(pcb->pcb_cr0); 753 754 cpu_init_idt(); 755 gdt_init_cpu(ci); 756 lapic_enable(); 757 lapic_set_lvt(); 758 lapic_initclocks(); 759 760 #ifdef i386 761 npxinit(ci); 762 #else 763 fpuinit(ci); 764 #endif 765 766 lldt(GSEL(GLDT_SEL, SEL_KPL)); 767 ltr(ci->ci_tss_sel); 768 769 cpu_init(ci); 770 cpu_get_tsc_freq(ci); 771 772 s = splhigh(); 773 #ifdef i386 774 lapic_tpr = 0; 775 #else 776 lcr8(0); 777 #endif 778 x86_enable_intr(); 779 splx(s); 780 #if 0 781 x86_errata(); 782 #endif 783 784 aprint_debug_dev(ci->ci_dev, "CPU %ld running\n", 785 (long)ci->ci_cpuid); 786 } 787 788 #if defined(DDB) 789 790 #include <ddb/db_output.h> 791 #include <machine/db_machdep.h> 792 793 /* 794 * Dump CPU information from ddb. 795 */ 796 void 797 cpu_debug_dump(void) 798 { 799 struct cpu_info *ci; 800 CPU_INFO_ITERATOR cii; 801 802 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 803 for (CPU_INFO_FOREACH(cii, ci)) { 804 db_printf("%p %s %ld %x %x %10p %10p\n", 805 ci, 806 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 807 (long)ci->ci_cpuid, 808 ci->ci_flags, ci->ci_ipis, 809 ci->ci_curlwp, 810 ci->ci_fpcurlwp); 811 } 812 } 813 #endif /* DDB */ 814 815 static void 816 cpu_copy_trampoline(void) 817 { 818 /* 819 * Copy boot code. 820 */ 821 extern u_char cpu_spinup_trampoline[]; 822 extern u_char cpu_spinup_trampoline_end[]; 823 824 vaddr_t mp_trampoline_vaddr; 825 826 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 827 UVM_KMF_VAONLY); 828 829 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 830 VM_PROT_READ | VM_PROT_WRITE, 0); 831 pmap_update(pmap_kernel()); 832 memcpy((void *)mp_trampoline_vaddr, 833 cpu_spinup_trampoline, 834 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 835 836 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 837 pmap_update(pmap_kernel()); 838 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 839 } 840 841 #endif /* MULTIPROCESSOR */ 842 843 #ifdef i386 844 #if 0 845 static void 846 tss_init(struct i386tss *tss, void *stack, void *func) 847 { 848 memset(tss, 0, sizeof *tss); 849 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 850 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 851 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 852 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 853 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 854 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 855 tss->tss_cr3 = pmap_kernel()->pm_pdirpa; 856 tss->tss_esp = (int)((char *)stack + USPACE - 16); 857 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 858 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 859 tss->__tss_eip = (int)func; 860 } 861 #endif 862 863 /* XXX */ 864 #define IDTVEC(name) __CONCAT(X, name) 865 typedef void (vector)(void); 866 extern vector IDTVEC(tss_trap08); 867 #ifdef DDB 868 extern vector Xintrddbipi; 869 extern int ddb_vec; 870 #endif 871 872 static void 873 cpu_set_tss_gates(struct cpu_info *ci) 874 { 875 #if 0 876 struct segment_descriptor sd; 877 878 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 879 UVM_KMF_WIRED); 880 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 881 IDTVEC(tss_trap08)); 882 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 883 SDT_SYS386TSS, SEL_KPL, 0, 0); 884 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 885 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 886 GSEL(GTRAPTSS_SEL, SEL_KPL)); 887 #endif 888 889 #if defined(DDB) && defined(MULTIPROCESSOR) 890 /* 891 * Set up separate handler for the DDB IPI, so that it doesn't 892 * stomp on a possibly corrupted stack. 893 * 894 * XXX overwriting the gate set in db_machine_init. 895 * Should rearrange the code so that it's set only once. 896 */ 897 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 898 UVM_KMF_WIRED); 899 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 900 Xintrddbipi); 901 902 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 903 SDT_SYS386TSS, SEL_KPL, 0, 0); 904 ci->ci_gdt[GIPITSS_SEL].sd = sd; 905 906 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 907 GSEL(GIPITSS_SEL, SEL_KPL)); 908 #endif 909 } 910 #else 911 static void 912 cpu_set_tss_gates(struct cpu_info *ci) 913 { 914 915 } 916 #endif /* i386 */ 917 918 int 919 mp_cpu_start(struct cpu_info *ci, paddr_t target) 920 { 921 #if 0 922 #if NLAPIC > 0 923 int error; 924 #endif 925 unsigned short dwordptr[2]; 926 927 /* 928 * Bootstrap code must be addressable in real mode 929 * and it must be page aligned. 930 */ 931 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 932 933 /* 934 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 935 */ 936 937 outb(IO_RTC, NVRAM_RESET); 938 outb(IO_RTC+1, NVRAM_RESET_JUMP); 939 940 /* 941 * "and the warm reset vector (DWORD based at 40:67) to point 942 * to the AP startup code ..." 943 */ 944 945 dwordptr[0] = 0; 946 dwordptr[1] = target >> 4; 947 948 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 949 pmap_update(pmap_kernel()); 950 951 memcpy ((uint8_t *) 0x467, dwordptr, 4); 952 953 pmap_kremove (0, PAGE_SIZE); 954 pmap_update(pmap_kernel()); 955 956 #if NLAPIC > 0 957 /* 958 * ... prior to executing the following sequence:" 959 */ 960 961 if (ci->ci_flags & CPUF_AP) { 962 if ((error = x86_ipi_init(ci->ci_cpuid)) != 0) 963 return error; 964 965 delay(10000); 966 967 if (cpu_feature & CPUID_APIC) { 968 error = x86_ipi_init(ci->ci_cpuid); 969 if (error != 0) { 970 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 971 __func__); 972 return error; 973 } 974 975 delay(10000); 976 977 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 978 LAPIC_DLMODE_STARTUP); 979 if (error != 0) { 980 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 981 __func__); 982 return error; 983 } 984 delay(200); 985 986 error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid, 987 LAPIC_DLMODE_STARTUP); 988 if (error != 0) { 989 aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n", 990 __func__); 991 return error; 992 } 993 delay(200); 994 } 995 } 996 #endif 997 #endif /* 0 */ 998 return 0; 999 } 1000 1001 void 1002 mp_cpu_start_cleanup(struct cpu_info *ci) 1003 { 1004 #if 0 1005 /* 1006 * Ensure the NVRAM reset byte contains something vaguely sane. 1007 */ 1008 1009 outb(IO_RTC, NVRAM_RESET); 1010 outb(IO_RTC+1, NVRAM_RESET_RST); 1011 #endif 1012 } 1013 1014 void 1015 cpu_init_msrs(struct cpu_info *ci, bool full) 1016 { 1017 #ifdef __x86_64__ 1018 if (full) { 1019 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1020 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1021 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1022 } 1023 #endif /* __x86_64__ */ 1024 1025 if (cpu_feature[2] & CPUID_NOX) 1026 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1027 } 1028 1029 void 1030 cpu_offline_md(void) 1031 { 1032 int s; 1033 1034 s = splhigh(); 1035 #ifdef __i386__ 1036 npxsave_cpu(true); 1037 #else 1038 fpusave_cpu(true); 1039 #endif 1040 splx(s); 1041 } 1042 1043 #if 0 1044 /* XXX joerg restructure and restart CPUs individually */ 1045 static bool 1046 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1047 { 1048 struct cpu_softc *sc = device_private(dv); 1049 struct cpu_info *ci = sc->sc_info; 1050 int err; 1051 1052 if (ci->ci_flags & CPUF_PRIMARY) 1053 return true; 1054 if (ci->ci_data.cpu_idlelwp == NULL) 1055 return true; 1056 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1057 return true; 1058 1059 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1060 1061 if (sc->sc_wasonline) { 1062 mutex_enter(&cpu_lock); 1063 err = cpu_setstate(ci, false); 1064 mutex_exit(&cpu_lock); 1065 1066 if (err) 1067 return false; 1068 } 1069 1070 return true; 1071 } 1072 1073 static bool 1074 cpu_resume(device_t dv, const pmf_qual_t *qual) 1075 { 1076 struct cpu_softc *sc = device_private(dv); 1077 struct cpu_info *ci = sc->sc_info; 1078 int err = 0; 1079 1080 if (ci->ci_flags & CPUF_PRIMARY) 1081 return true; 1082 if (ci->ci_data.cpu_idlelwp == NULL) 1083 return true; 1084 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1085 return true; 1086 1087 if (sc->sc_wasonline) { 1088 mutex_enter(&cpu_lock); 1089 err = cpu_setstate(ci, true); 1090 mutex_exit(&cpu_lock); 1091 } 1092 1093 return err == 0; 1094 } 1095 #endif 1096 1097 void 1098 cpu_get_tsc_freq(struct cpu_info *ci) 1099 { 1100 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1101 delay(1000000); 1102 uint64_t freq = 1000000000ULL << 32; 1103 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1104 if ( tinfo->tsc_shift < 0 ) 1105 freq = freq << -tinfo->tsc_shift; 1106 else 1107 freq = freq >> tinfo->tsc_shift; 1108 ci->ci_data.cpu_cc_freq = freq; 1109 } 1110 1111 void 1112 x86_cpu_idle_xen(void) 1113 { 1114 struct cpu_info *ci = curcpu(); 1115 1116 KASSERT(ci->ci_ilevel == IPL_NONE); 1117 1118 x86_disable_intr(); 1119 if (!__predict_false(ci->ci_want_resched)) { 1120 idle_block(); 1121 } else { 1122 x86_enable_intr(); 1123 } 1124 } 1125 1126 /* 1127 * Loads pmap for the current CPU. 1128 */ 1129 void 1130 cpu_load_pmap(struct pmap *pmap) 1131 { 1132 #ifdef i386 1133 #ifdef PAE 1134 int i, s; 1135 struct cpu_info *ci; 1136 1137 s = splvm(); /* just to be safe */ 1138 ci = curcpu(); 1139 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1140 /* don't update the kernel L3 slot */ 1141 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1142 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1143 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1144 } 1145 splx(s); 1146 tlbflush(); 1147 #else /* PAE */ 1148 lcr3(pmap_pdirpa(pmap, 0)); 1149 #endif /* PAE */ 1150 #endif /* i386 */ 1151 1152 #ifdef __x86_64__ 1153 int i, s; 1154 pd_entry_t *old_pgd, *new_pgd; 1155 paddr_t addr; 1156 struct cpu_info *ci; 1157 1158 /* kernel pmap always in cr3 and should never go in user cr3 */ 1159 if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) { 1160 ci = curcpu(); 1161 /* 1162 * Map user space address in kernel space and load 1163 * user cr3 1164 */ 1165 s = splvm(); 1166 new_pgd = pmap->pm_pdir; 1167 old_pgd = pmap_kernel()->pm_pdir; 1168 addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0)); 1169 for (i = 0; i < PDIR_SLOT_PTE; 1170 i++, addr += sizeof(pd_entry_t)) { 1171 if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V)) 1172 xpq_queue_pte_update(addr, new_pgd[i]); 1173 } 1174 tlbflush(); 1175 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1176 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1177 splx(s); 1178 } 1179 #endif /* __x86_64__ */ 1180 } 1181
Indexes created Fri Oct 03 02:09:57 GMT 2025