cpu.c revision 1.7
1 /* $NetBSD: cpu.c,v 1.7 2008/01/11 20:00:50 bouyer Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Copyright (c) 1999 Stefan Grefen 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the NetBSD 56 * Foundation, Inc. and its contributors. 57 * 4. Neither the name of The NetBSD Foundation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 62 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.7 2008/01/11 20:00:50 bouyer Exp $"); 76 77 #include "opt_ddb.h" 78 #include "opt_multiprocessor.h" 79 #include "opt_mpbios.h" /* for MPDEBUG */ 80 #include "opt_mtrr.h" 81 #include "opt_xen.h" 82 83 #include "lapic.h" 84 #include "ioapic.h" 85 86 #include <sys/param.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/cpu.h> 96 #include <machine/cpufunc.h> 97 #include <machine/cpuvar.h> 98 #include <machine/pmap.h> 99 #include <machine/vmparam.h> 100 #include <machine/mpbiosvar.h> 101 #include <machine/pcb.h> 102 #include <machine/specialreg.h> 103 #include <machine/segments.h> 104 #include <machine/gdt.h> 105 #include <machine/mtrr.h> 106 #include <machine/pio.h> 107 108 #ifdef XEN3 109 #include <xen/vcpuvar.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #if NIOAPIC > 0 119 #include <machine/i82093var.h> 120 #endif 121 122 #include <dev/ic/mc146818reg.h> 123 #include <dev/isa/isareg.h> 124 125 int cpu_match(struct device *, struct cfdata *, void *); 126 void cpu_attach(struct device *, struct device *, void *); 127 #ifdef XEN3 128 int vcpu_match(struct device *, struct cfdata *, void *); 129 void vcpu_attach(struct device *, struct device *, void *); 130 #endif 131 void cpu_attach_common(struct device *, struct device *, void *); 132 133 struct cpu_softc { 134 struct device sc_dev; /* device tree glue */ 135 struct cpu_info *sc_info; /* pointer to CPU info */ 136 }; 137 138 int mp_cpu_start(struct cpu_info *, paddr_t); 139 void mp_cpu_start_cleanup(struct cpu_info *); 140 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 141 mp_cpu_start_cleanup }; 142 143 CFATTACH_DECL(cpu, sizeof(struct cpu_softc), 144 cpu_match, cpu_attach, NULL, NULL); 145 #ifdef XEN3 146 CFATTACH_DECL(vcpu, sizeof(struct cpu_softc), 147 vcpu_match, vcpu_attach, NULL, NULL); 148 #endif 149 150 /* 151 * Statically-allocated CPU info for the primary CPU (or the only 152 * CPU, on uniprocessors). The CPU info list is initialized to 153 * point at it. 154 */ 155 #ifdef TRAPLOG 156 #include <machine/tlog.h> 157 struct tlog tlog_primary; 158 #endif 159 struct cpu_info cpu_info_primary = { 160 .ci_dev = 0, 161 .ci_self = &cpu_info_primary, 162 .ci_idepth = -1, 163 .ci_curlwp = &lwp0, 164 #ifdef TRAPLOG 165 .ci_tlog = &tlog_primary, 166 #endif 167 168 }; 169 struct cpu_info phycpu_info_primary = { 170 .ci_dev = 0, 171 .ci_self = &phycpu_info_primary, 172 }; 173 174 struct cpu_info *cpu_info_list = &cpu_info_primary; 175 176 static void cpu_set_tss_gates(struct cpu_info *ci); 177 178 u_int32_t cpus_attached = 0; 179 180 struct cpu_info *phycpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 181 182 #ifdef MULTIPROCESSOR 183 /* 184 * Array of CPU info structures. Must be statically-allocated because 185 * curproc, etc. are used early. 186 */ 187 struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary }; 188 189 u_int32_t cpus_running = 0; 190 191 void cpu_hatch(void *); 192 static void cpu_boot_secondary(struct cpu_info *ci); 193 static void cpu_start_secondary(struct cpu_info *ci); 194 static void cpu_copy_trampoline(void); 195 196 /* 197 * Runs once per boot once multiprocessor goo has been detected and 198 * the local APIC on the boot processor has been mapped. 199 * 200 * Called from lapic_boot_init() (from mpbios_scan()). 201 */ 202 void 203 cpu_init_first() 204 { 205 int cpunum = lapic_cpu_number(); 206 207 if (cpunum != 0) { 208 cpu_info[0] = NULL; 209 cpu_info[cpunum] = &cpu_info_primary; 210 } 211 212 cpu_copy_trampoline(); 213 } 214 #endif 215 216 int 217 cpu_match(parent, match, aux) 218 struct device *parent; 219 struct cfdata *match; 220 void *aux; 221 { 222 223 return 1; 224 } 225 226 void 227 cpu_attach(parent, self, aux) 228 struct device *parent, *self; 229 void *aux; 230 { 231 #ifdef XEN3 232 struct cpu_softc *sc = (void *) self; 233 struct cpu_attach_args *caa = aux; 234 struct cpu_info *ci; 235 int cpunum = caa->cpu_number; 236 237 /* 238 * If we're an Application Processor, allocate a cpu_info 239 * structure, otherwise use the primary's. 240 */ 241 if (caa->cpu_role == CPU_ROLE_AP) { 242 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 243 if (phycpu_info[cpunum] != NULL) 244 panic("cpu at apic id %d already attached?", cpunum); 245 phycpu_info[cpunum] = ci; 246 } else { 247 ci = &phycpu_info_primary; 248 if (cpunum != 0) { 249 phycpu_info[0] = NULL; 250 phycpu_info[cpunum] = ci; 251 } 252 } 253 254 ci->ci_self = ci; 255 sc->sc_info = ci; 256 257 ci->ci_dev = self; 258 ci->ci_apicid = caa->cpu_number; 259 ci->ci_cpuid = ci->ci_apicid; 260 261 printf(": "); 262 switch (caa->cpu_role) { 263 case CPU_ROLE_SP: 264 printf("(uniprocessor)\n"); 265 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 266 break; 267 268 case CPU_ROLE_BP: 269 printf("(boot processor)\n"); 270 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 271 #if NIOAPIC > 0 272 ioapic_bsp_id = caa->cpu_number; 273 #endif 274 break; 275 276 case CPU_ROLE_AP: 277 /* 278 * report on an AP 279 */ 280 printf("(application processor)\n"); 281 break; 282 283 default: 284 panic("unknown processor type??\n"); 285 } 286 return; 287 #else 288 cpu_attach_common(parent, self, aux); 289 #endif 290 } 291 292 #ifdef XEN3 293 int 294 vcpu_match(parent, match, aux) 295 struct device *parent; 296 struct cfdata *match; 297 void *aux; 298 { 299 struct vcpu_attach_args *vcaa = aux; 300 301 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) 302 return 1; 303 return 0; 304 } 305 306 void 307 vcpu_attach(parent, self, aux) 308 struct device *parent, *self; 309 void *aux; 310 { 311 struct vcpu_attach_args *vcaa = aux; 312 313 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 314 } 315 #endif 316 317 static void 318 cpu_vm_init(struct cpu_info *ci) 319 { 320 int ncolors = 2, i; 321 322 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 323 struct x86_cache_info *cai; 324 int tcolors; 325 326 cai = &ci->ci_cinfo[i]; 327 328 tcolors = atop(cai->cai_totalsize); 329 switch(cai->cai_associativity) { 330 case 0xff: 331 tcolors = 1; /* fully associative */ 332 break; 333 case 0: 334 case 1: 335 break; 336 default: 337 tcolors /= cai->cai_associativity; 338 } 339 ncolors = max(ncolors, tcolors); 340 } 341 342 /* 343 * Knowing the size of the largest cache on this CPU, re-color 344 * our pages. 345 */ 346 if (ncolors <= uvmexp.ncolors) 347 return; 348 printf("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors); 349 uvm_page_recolor(ncolors); 350 } 351 352 void 353 cpu_attach_common(parent, self, aux) 354 struct device *parent, *self; 355 void *aux; 356 { 357 struct cpu_softc *sc = (void *) self; 358 struct cpu_attach_args *caa = aux; 359 struct cpu_info *ci; 360 #if defined(MULTIPROCESSOR) 361 int cpunum = caa->cpu_number; 362 #endif 363 364 /* 365 * If we're an Application Processor, allocate a cpu_info 366 * structure, otherwise use the primary's. 367 */ 368 if (caa->cpu_role == CPU_ROLE_AP) { 369 ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK | M_ZERO); 370 #if defined(MULTIPROCESSOR) 371 if (cpu_info[cpunum] != NULL) 372 panic("cpu at apic id %d already attached?", cpunum); 373 cpu_info[cpunum] = ci; 374 #endif 375 #ifdef TRAPLOG 376 ci->ci_tlog_base = malloc(sizeof(struct tlog), 377 M_DEVBUF, M_WAITOK); 378 #endif 379 } else { 380 ci = &cpu_info_primary; 381 #if defined(MULTIPROCESSOR) 382 if (cpunum != lapic_cpu_number()) { 383 panic("%s: running CPU is at apic %d" 384 " instead of at expected %d", 385 sc->sc_dev.dv_xname, lapic_cpu_number(), cpunum); 386 } 387 #endif 388 } 389 390 ci->ci_self = ci; 391 sc->sc_info = ci; 392 393 ci->ci_dev = self; 394 ci->ci_apicid = caa->cpu_number; 395 #ifdef MULTIPROCESSOR 396 ci->ci_cpuid = ci->ci_apicid; 397 #else 398 ci->ci_cpuid = 0; /* False for APs, but they're not used anyway */ 399 #endif 400 ci->ci_cpumask = (1 << ci->ci_cpuid); 401 ci->ci_func = caa->cpu_func; 402 403 if (caa->cpu_role == CPU_ROLE_AP) { 404 #if defined(MULTIPROCESSOR) 405 int error; 406 407 error = mi_cpu_attach(ci); 408 if (error != 0) { 409 aprint_normal("\n"); 410 aprint_error("%s: mi_cpu_attach failed with %d\n", 411 sc->sc_dev.dv_xname, error); 412 return; 413 } 414 #endif 415 } else { 416 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 417 } 418 419 pmap_reference(pmap_kernel()); 420 ci->ci_pmap = pmap_kernel(); 421 ci->ci_tlbstate = TLBSTATE_STALE; 422 423 /* further PCB init done later. */ 424 425 printf(": "); 426 427 switch (caa->cpu_role) { 428 case CPU_ROLE_SP: 429 printf("(uniprocessor)\n"); 430 ci->ci_flags |= CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY; 431 cpu_intr_init(ci); 432 identifycpu(ci); 433 cpu_init(ci); 434 cpu_set_tss_gates(ci); 435 break; 436 437 case CPU_ROLE_BP: 438 printf("apid %d (boot processor)\n", caa->cpu_number); 439 ci->ci_flags |= CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY; 440 cpu_intr_init(ci); 441 identifycpu(ci); 442 cpu_init(ci); 443 cpu_set_tss_gates(ci); 444 break; 445 446 case CPU_ROLE_AP: 447 /* 448 * report on an AP 449 */ 450 printf("apid %d (application processor)\n", caa->cpu_number); 451 452 #if defined(MULTIPROCESSOR) 453 cpu_intr_init(ci); 454 gdt_alloc_cpu(ci); 455 cpu_set_tss_gates(ci); 456 cpu_start_secondary(ci); 457 if (ci->ci_flags & CPUF_PRESENT) { 458 identifycpu(ci); 459 ci->ci_next = cpu_info_list->ci_next; 460 cpu_info_list->ci_next = ci; 461 } 462 #else 463 printf("%s: not started\n", sc->sc_dev.dv_xname); 464 #endif 465 break; 466 467 default: 468 panic("unknown processor type??\n"); 469 } 470 cpu_vm_init(ci); 471 472 cpus_attached |= (1 << ci->ci_cpuid); 473 474 #if defined(MULTIPROCESSOR) 475 if (mp_verbose) { 476 struct lwp *l = ci->ci_data.cpu_idlelwp; 477 478 aprint_verbose("%s: idle lwp at %p, idle sp at 0x%x\n", 479 sc->sc_dev.dv_xname, l, l->l_addr->u_pcb.pcb_esp); 480 } 481 #endif 482 } 483 484 /* 485 * Initialize the processor appropriately. 486 */ 487 488 void 489 cpu_init(ci) 490 struct cpu_info *ci; 491 { 492 /* configure the CPU if needed */ 493 if (ci->cpu_setup != NULL) 494 (*ci->cpu_setup)(ci); 495 496 /* 497 * On a P6 or above, enable global TLB caching if the 498 * hardware supports it. 499 */ 500 if (cpu_feature & CPUID_PGE) 501 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 502 503 #ifdef XXXMTRR 504 /* 505 * On a P6 or above, initialize MTRR's if the hardware supports them. 506 */ 507 if (cpu_feature & CPUID_MTRR) { 508 if ((ci->ci_flags & CPUF_AP) == 0) 509 i686_mtrr_init_first(); 510 mtrr_init_cpu(ci); 511 } 512 #endif 513 /* 514 * If we have FXSAVE/FXRESTOR, use them. 515 */ 516 if (cpu_feature & CPUID_FXSR) { 517 lcr4(rcr4() | CR4_OSFXSR); 518 519 /* 520 * If we have SSE/SSE2, enable XMM exceptions. 521 */ 522 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) 523 lcr4(rcr4() | CR4_OSXMMEXCPT); 524 } 525 526 #ifdef MULTIPROCESSOR 527 ci->ci_flags |= CPUF_RUNNING; 528 cpus_running |= 1 << ci->ci_cpuid; 529 #endif 530 } 531 532 533 #ifdef MULTIPROCESSOR 534 void 535 cpu_boot_secondary_processors() 536 { 537 struct cpu_info *ci; 538 u_long i; 539 540 for (i=0; i < X86_MAXPROCS; i++) { 541 ci = cpu_info[i]; 542 if (ci == NULL) 543 continue; 544 if (ci->ci_data.cpu_idlelwp == NULL) 545 continue; 546 if ((ci->ci_flags & CPUF_PRESENT) == 0) 547 continue; 548 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 549 continue; 550 cpu_boot_secondary(ci); 551 } 552 } 553 554 static void 555 cpu_init_idle_lwp(struct cpu_info *ci) 556 { 557 struct lwp *l = ci->ci_data.cpu_idlelwp; 558 struct pcb *pcb = &l->l_addr->u_pcb; 559 560 pcb->pcb_cr0 = rcr0(); 561 } 562 563 void 564 cpu_init_idle_lwps() 565 { 566 struct cpu_info *ci; 567 u_long i; 568 569 for (i = 0; i < X86_MAXPROCS; i++) { 570 ci = cpu_info[i]; 571 if (ci == NULL) 572 continue; 573 if (ci->ci_data.cpu_idlelwp == NULL) 574 continue; 575 if ((ci->ci_flags & CPUF_PRESENT) == 0) 576 continue; 577 cpu_init_idle_lwp(ci); 578 } 579 } 580 581 void 582 cpu_start_secondary (ci) 583 struct cpu_info *ci; 584 { 585 int i; 586 struct pmap *kpm = pmap_kernel(); 587 extern u_int32_t mp_pdirpa; 588 589 mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */ 590 591 ci->ci_flags |= CPUF_AP; 592 593 printf("%s: starting\n", ci->ci_dev->dv_xname); 594 595 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 596 CPU_STARTUP(ci); 597 598 /* 599 * wait for it to become ready 600 */ 601 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) { 602 delay(10); 603 } 604 if (! (ci->ci_flags & CPUF_PRESENT)) { 605 printf("%s: failed to become ready\n", ci->ci_dev->dv_xname); 606 #if defined(MPDEBUG) && defined(DDB) 607 printf("dropping into debugger; continue from here to resume boot\n"); 608 Debugger(); 609 #endif 610 } 611 612 CPU_START_CLEANUP(ci); 613 } 614 615 void 616 cpu_boot_secondary(ci) 617 struct cpu_info *ci; 618 { 619 int i; 620 621 ci->ci_flags |= CPUF_GO; /* XXX atomic */ 622 623 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) { 624 delay(10); 625 } 626 if (! (ci->ci_flags & CPUF_RUNNING)) { 627 printf("CPU failed to start\n"); 628 #if defined(MPDEBUG) && defined(DDB) 629 printf("dropping into debugger; continue from here to resume boot\n"); 630 Debugger(); 631 #endif 632 } 633 } 634 635 /* 636 * The CPU ends up here when its ready to run 637 * This is called from code in mptramp.s; at this point, we are running 638 * in the idle pcb/idle stack of the new CPU. When this function returns, 639 * this processor will enter the idle loop and start looking for work. 640 * 641 * XXX should share some of this with init386 in machdep.c 642 */ 643 void 644 cpu_hatch(void *v) 645 { 646 struct cpu_info *ci = (struct cpu_info *)v; 647 int s; 648 #ifdef __x86_64__ 649 cpu_init_msrs(ci); 650 #endif 651 652 cpu_probe_features(ci); 653 cpu_feature &= ci->ci_feature_flags; 654 /* not on Xen... */ 655 cpu_feature &= ~(CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR|CPUID_NOX); 656 657 #ifdef DEBUG 658 if (ci->ci_flags & CPUF_PRESENT) 659 panic("%s: already running!?", ci->ci_dev->dv_xname); 660 #endif 661 662 ci->ci_flags |= CPUF_PRESENT; 663 664 lapic_enable(); 665 lapic_initclocks(); 666 667 while ((ci->ci_flags & CPUF_GO) == 0) 668 delay(10); 669 #ifdef DEBUG 670 if (ci->ci_flags & CPUF_RUNNING) 671 panic("%s: already running!?", ci->ci_dev->dv_xname); 672 #endif 673 674 lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0); 675 cpu_init_idt(); 676 lapic_set_lvt(); 677 gdt_init_cpu(ci); 678 npxinit(ci); 679 680 lldt(GSEL(GLDT_SEL, SEL_KPL)); 681 682 cpu_init(ci); 683 684 s = splhigh(); 685 lapic_tpr = 0; 686 enable_intr(); 687 688 printf("%s: CPU %ld running\n",ci->ci_dev->dv_xname, ci->ci_cpuid); 689 if (ci->ci_feature_flags & CPUID_TSC) 690 cc_microset(ci); 691 splx(s); 692 } 693 694 #if defined(DDB) 695 696 #include <ddb/db_output.h> 697 #include <machine/db_machdep.h> 698 699 /* 700 * Dump CPU information from ddb. 701 */ 702 void 703 cpu_debug_dump(void) 704 { 705 struct cpu_info *ci; 706 CPU_INFO_ITERATOR cii; 707 708 db_printf("addr dev id flags ipis curproc fpcurproc\n"); 709 for (CPU_INFO_FOREACH(cii, ci)) { 710 db_printf("%p %s %ld %x %x %10p %10p\n", 711 ci, 712 ci->ci_dev == NULL ? "BOOT" : ci->ci_dev->dv_xname, 713 ci->ci_cpuid, 714 ci->ci_flags, ci->ci_ipis, 715 ci->ci_curlwp, 716 ci->ci_fpcurlwp); 717 } 718 } 719 #endif 720 721 static void 722 cpu_copy_trampoline() 723 { 724 /* 725 * Copy boot code. 726 */ 727 extern u_char cpu_spinup_trampoline[]; 728 extern u_char cpu_spinup_trampoline_end[]; 729 pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE, /* virtual */ 730 (paddr_t)MP_TRAMPOLINE, /* physical */ 731 VM_PROT_ALL); /* protection */ 732 memcpy((void *)MP_TRAMPOLINE, 733 cpu_spinup_trampoline, 734 cpu_spinup_trampoline_end-cpu_spinup_trampoline); 735 } 736 737 #endif 738 739 740 /* XXX */ 741 #define IDTVEC(name) __CONCAT(X, name) 742 typedef void (vector)(void); 743 extern vector IDTVEC(tss_trap08); 744 #ifdef DDB 745 extern vector Xintrddbipi; 746 extern int ddb_vec; 747 #endif 748 749 static void 750 cpu_set_tss_gates(struct cpu_info *ci) 751 { 752 #if defined(DDB) && defined(MULTIPROCESSOR) 753 /* 754 * Set up separate handler for the DDB IPI, so that it doesn't 755 * stomp on a possibly corrupted stack. 756 * 757 * XXX overwriting the gate set in db_machine_init. 758 * Should rearrange the code so that it's set only once. 759 */ 760 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 761 UVM_KMF_WIRED); 762 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, 763 Xintrddbipi); 764 765 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 766 SDT_SYS386TSS, SEL_KPL, 0, 0); 767 ci->ci_gdt[GIPITSS_SEL].sd = sd; 768 769 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 770 GSEL(GIPITSS_SEL, SEL_KPL)); 771 #endif 772 } 773 774 int 775 mp_cpu_start(struct cpu_info *ci, paddr_t target) 776 { 777 #if 0 778 #if NLAPIC > 0 779 int error; 780 #endif 781 unsigned short dwordptr[2]; 782 783 /* 784 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 785 */ 786 787 outb(IO_RTC, NVRAM_RESET); 788 outb(IO_RTC+1, NVRAM_RESET_JUMP); 789 790 /* 791 * "and the warm reset vector (DWORD based at 40:67) to point 792 * to the AP startup code ..." 793 */ 794 795 dwordptr[0] = 0; 796 dwordptr[1] = target >> 4; 797 798 pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE); 799 memcpy ((u_int8_t *) 0x467, dwordptr, 4); 800 pmap_kremove (0, PAGE_SIZE); 801 802 #if NLAPIC > 0 803 /* 804 * ... prior to executing the following sequence:" 805 */ 806 807 if (ci->ci_flags & CPUF_AP) { 808 if ((error = x86_ipi_init(ci->ci_apicid)) != 0) 809 return error; 810 811 delay(10000); 812 813 if (cpu_feature & CPUID_APIC) { 814 815 if ((error = x86_ipi(target/PAGE_SIZE, 816 ci->ci_apicid, 817 LAPIC_DLMODE_STARTUP)) != 0) 818 return error; 819 delay(200); 820 821 if ((error = x86_ipi(target/PAGE_SIZE, 822 ci->ci_apicid, 823 LAPIC_DLMODE_STARTUP)) != 0) 824 return error; 825 delay(200); 826 } 827 } 828 #endif 829 #endif /* 0 */ 830 return 0; 831 } 832 833 void 834 mp_cpu_start_cleanup(struct cpu_info *ci) 835 { 836 #if 0 837 /* 838 * Ensure the NVRAM reset byte contains something vaguely sane. 839 */ 840 841 outb(IO_RTC, NVRAM_RESET); 842 outb(IO_RTC+1, NVRAM_RESET_RST); 843 #endif 844 } 845 846 #ifdef __x86_64__ 847 848 void 849 cpu_init_msrs(struct cpu_info *ci, bool full) 850 { 851 if (full) { 852 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 853 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (u_int64_t) ci); 854 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 855 } 856 } 857 #endif /* __x86_64__ */ 858 859 void 860 cpu_get_tsc_freq(struct cpu_info *ci) 861 { 862 #ifdef XEN3 863 const volatile vcpu_time_info_t *tinfo = 864 &HYPERVISOR_shared_info->vcpu_info[0].time; 865 delay(1000000); 866 uint64_t freq = 1000000000ULL << 32; 867 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 868 if ( tinfo->tsc_shift < 0 ) 869 freq = freq << -tinfo->tsc_shift; 870 else 871 freq = freq >> tinfo->tsc_shift; 872 ci->ci_tsc_freq = freq; 873 #else 874 /* XXX this needs to read the shared_info of the CPU being probed.. */ 875 ci->ci_tsc_freq = HYPERVISOR_shared_info->cpu_freq; 876 #endif /* XEN3 */ 877 } 878
Indexes created Fri Oct 03 02:09:57 GMT 2025