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hypervisor_machdep.c revision 1.14.2.2
      1  1.14.2.2  cherry /*	$NetBSD: hypervisor_machdep.c,v 1.14.2.2 2011/08/04 09:07:47 cherry Exp $	*/
      2       1.2  bouyer 
      3       1.2  bouyer /*
      4       1.2  bouyer  *
      5       1.2  bouyer  * Copyright (c) 2004 Christian Limpach.
      6       1.2  bouyer  * All rights reserved.
      7       1.2  bouyer  *
      8       1.2  bouyer  * Redistribution and use in source and binary forms, with or without
      9       1.2  bouyer  * modification, are permitted provided that the following conditions
     10       1.2  bouyer  * are met:
     11       1.2  bouyer  * 1. Redistributions of source code must retain the above copyright
     12       1.2  bouyer  *    notice, this list of conditions and the following disclaimer.
     13       1.2  bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     14       1.2  bouyer  *    notice, this list of conditions and the following disclaimer in the
     15       1.2  bouyer  *    documentation and/or other materials provided with the distribution.
     16       1.2  bouyer  *
     17       1.2  bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18       1.2  bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19       1.2  bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20       1.2  bouyer  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21       1.2  bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22       1.2  bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23       1.2  bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24       1.2  bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25       1.2  bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26       1.2  bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27       1.2  bouyer  */
     28       1.2  bouyer 
     29       1.2  bouyer /******************************************************************************
     30       1.2  bouyer  * hypervisor.c
     31       1.2  bouyer  *
     32       1.2  bouyer  * Communication to/from hypervisor.
     33       1.2  bouyer  *
     34       1.2  bouyer  * Copyright (c) 2002-2004, K A Fraser
     35       1.2  bouyer  *
     36       1.2  bouyer  * Permission is hereby granted, free of charge, to any person obtaining a copy
     37       1.2  bouyer  * of this software and associated documentation files (the "Software"), to
     38       1.2  bouyer  * deal in the Software without restriction, including without limitation the
     39       1.2  bouyer  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
     40       1.2  bouyer  * sell copies of the Software, and to permit persons to whom the Software is
     41       1.2  bouyer  * furnished to do so, subject to the following conditions:
     42       1.2  bouyer  *
     43       1.2  bouyer  * The above copyright notice and this permission notice shall be included in
     44       1.2  bouyer  * all copies or substantial portions of the Software.
     45       1.2  bouyer  *
     46       1.2  bouyer  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     47       1.2  bouyer  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     48       1.2  bouyer  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
     49       1.2  bouyer  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     50       1.2  bouyer  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     51       1.2  bouyer  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     52       1.2  bouyer  * DEALINGS IN THE SOFTWARE.
     53       1.2  bouyer  */
     54       1.2  bouyer 
     55       1.2  bouyer 
     56       1.2  bouyer #include <sys/cdefs.h>
     57  1.14.2.2  cherry __KERNEL_RCSID(0, "$NetBSD: hypervisor_machdep.c,v 1.14.2.2 2011/08/04 09:07:47 cherry Exp $");
     58       1.2  bouyer 
     59       1.2  bouyer #include <sys/param.h>
     60       1.2  bouyer #include <sys/systm.h>
     61      1.10  bouyer #include <sys/kmem.h>
     62      1.10  bouyer 
     63      1.10  bouyer #include <uvm/uvm_extern.h>
     64      1.10  bouyer 
     65      1.10  bouyer #include <machine/vmparam.h>
     66      1.10  bouyer #include <machine/pmap.h>
     67       1.2  bouyer 
     68       1.2  bouyer #include <xen/xen.h>
     69       1.2  bouyer #include <xen/hypervisor.h>
     70       1.2  bouyer #include <xen/evtchn.h>
     71      1.10  bouyer #include <xen/xenpmap.h>
     72       1.2  bouyer 
     73       1.2  bouyer #include "opt_xen.h"
     74       1.2  bouyer 
     75      1.10  bouyer /*
     76      1.10  bouyer  * arch-dependent p2m frame lists list (L3 and L2)
     77      1.10  bouyer  * used by Xen for save/restore mappings
     78      1.10  bouyer  */
     79      1.10  bouyer static unsigned long * l3_p2m_page;
     80      1.10  bouyer static unsigned long * l2_p2m_page;
     81      1.10  bouyer static int l2_p2m_page_size; /* size of L2 page, in pages */
     82      1.10  bouyer 
     83      1.10  bouyer static void build_p2m_frame_list_list(void);
     84      1.10  bouyer static void update_p2m_frame_list_list(void);
     85      1.10  bouyer 
     86       1.2  bouyer // #define PORT_DEBUG 4
     87       1.2  bouyer // #define EARLY_DEBUG_EVENT
     88       1.2  bouyer 
     89  1.14.2.2  cherry static inline unsigned int
     90  1.14.2.2  cherry evt_bitstr_to_port(unsigned long l1, unsigned long l2)
     91  1.14.2.2  cherry {
     92  1.14.2.2  cherry 	unsigned int l1i, l2i, port;
     93  1.14.2.2  cherry 
     94  1.14.2.2  cherry 	l1i = xen_ffs(l1) - 1;
     95  1.14.2.2  cherry 	l2i = xen_ffs(l2) - 1;
     96  1.14.2.2  cherry 
     97  1.14.2.2  cherry 	port = (l1i << LONG_SHIFT) + l2i;
     98  1.14.2.2  cherry 	return port;
     99  1.14.2.2  cherry }
    100  1.14.2.2  cherry 
    101  1.14.2.2  cherry /* callback function type */
    102  1.14.2.2  cherry typedef void (*iterate_func_t)(struct cpu_info *,
    103  1.14.2.2  cherry 			       unsigned int,
    104  1.14.2.2  cherry 			       unsigned int,
    105  1.14.2.2  cherry 			       unsigned int,
    106  1.14.2.2  cherry 			       void *);
    107  1.14.2.2  cherry 
    108  1.14.2.2  cherry 
    109  1.14.2.2  cherry static inline void
    110  1.14.2.2  cherry evt_iterate_pending(struct cpu_info *ci,
    111  1.14.2.2  cherry 		    volatile unsigned long *pendingl1,
    112  1.14.2.2  cherry 		    volatile unsigned long *pendingl2,
    113  1.14.2.2  cherry 		    volatile unsigned long *mask,
    114  1.14.2.2  cherry 		    iterate_func_t iterate_pending,
    115  1.14.2.2  cherry 		    void *iterate_args)
    116  1.14.2.2  cherry {
    117  1.14.2.2  cherry 
    118  1.14.2.2  cherry 	KASSERT(pendingl1 != NULL);
    119  1.14.2.2  cherry 	KASSERT(pendingl2 != NULL);
    120  1.14.2.2  cherry 
    121  1.14.2.2  cherry 	unsigned long l1, l2;
    122  1.14.2.2  cherry 	unsigned int l1i, l2i, port;
    123  1.14.2.2  cherry 
    124  1.14.2.2  cherry 	l1 = xen_atomic_xchg(pendingl1, 0);
    125  1.14.2.2  cherry 	while ((l1i = xen_ffs(l1)) != 0) {
    126  1.14.2.2  cherry 		l1i--;
    127  1.14.2.2  cherry 		l1 &= ~(1UL << l1i);
    128  1.14.2.2  cherry 
    129  1.14.2.2  cherry 		l2 = pendingl2[l1i] & (mask != NULL ? ~mask[l1i] : -1UL);
    130  1.14.2.2  cherry 
    131  1.14.2.2  cherry 		if (mask != NULL) xen_atomic_setbits_l(&mask[l1i], l2);
    132  1.14.2.2  cherry 		xen_atomic_clearbits_l(&pendingl2[l1i], l2);
    133  1.14.2.2  cherry 
    134  1.14.2.2  cherry 		while ((l2i = xen_ffs(l2)) != 0) {
    135  1.14.2.2  cherry 			l2i--;
    136  1.14.2.2  cherry 			l2 &= ~(1UL << l2i);
    137  1.14.2.2  cherry 
    138  1.14.2.2  cherry 			port = (l1i << LONG_SHIFT) + l2i;
    139  1.14.2.2  cherry 
    140  1.14.2.2  cherry 			iterate_pending(ci, port, l1i, l2i, iterate_args);
    141  1.14.2.2  cherry 		}
    142  1.14.2.2  cherry 	}
    143  1.14.2.2  cherry }
    144  1.14.2.2  cherry 
    145  1.14.2.2  cherry /*
    146  1.14.2.2  cherry  * Set per-cpu "pending" information for outstanding events that
    147  1.14.2.2  cherry  * cannot be processed now.
    148  1.14.2.2  cherry  */
    149  1.14.2.2  cherry 
    150  1.14.2.2  cherry static inline void
    151  1.14.2.2  cherry evt_set_pending(struct cpu_info *ci,
    152  1.14.2.2  cherry 		unsigned int port,
    153  1.14.2.2  cherry 		unsigned int l1i,
    154  1.14.2.2  cherry 		unsigned int l2i,
    155  1.14.2.2  cherry 		void *args)
    156  1.14.2.2  cherry {
    157  1.14.2.2  cherry 
    158  1.14.2.2  cherry 	KASSERT(args != NULL);
    159  1.14.2.2  cherry 	KASSERT(ci != NULL);
    160  1.14.2.2  cherry 
    161  1.14.2.2  cherry 	int *ret = args;
    162  1.14.2.2  cherry 
    163  1.14.2.2  cherry 	if (evtsource[port]) {
    164  1.14.2.2  cherry 		hypervisor_set_ipending(ci,
    165  1.14.2.2  cherry 			evtsource[port]->ev_imask,
    166  1.14.2.2  cherry 			l1i, l2i);
    167  1.14.2.2  cherry 		evtsource[port]->ev_evcnt.ev_count++;
    168  1.14.2.2  cherry 		if (*ret == 0 && ci->ci_ilevel <
    169  1.14.2.2  cherry 		    evtsource[port]->ev_maxlevel)
    170  1.14.2.2  cherry 			*ret = 1;
    171  1.14.2.2  cherry 	}
    172  1.14.2.2  cherry #ifdef DOM0OPS
    173  1.14.2.2  cherry 	else  {
    174  1.14.2.2  cherry 		/* set pending event */
    175  1.14.2.2  cherry 		xenevt_setipending(l1i, l2i);
    176  1.14.2.2  cherry 	}
    177  1.14.2.2  cherry #endif
    178  1.14.2.2  cherry }
    179  1.14.2.2  cherry 
    180       1.2  bouyer int stipending(void);
    181       1.2  bouyer int
    182       1.7  cegger stipending(void)
    183       1.2  bouyer {
    184       1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    185       1.2  bouyer 	struct cpu_info *ci;
    186       1.8  cegger 	volatile struct vcpu_info *vci;
    187       1.2  bouyer 	int ret;
    188       1.2  bouyer 
    189       1.2  bouyer 	ret = 0;
    190       1.2  bouyer 	ci = curcpu();
    191       1.8  cegger 	vci = ci->ci_vcpu;
    192       1.2  bouyer 
    193       1.2  bouyer #if 0
    194       1.2  bouyer 	if (HYPERVISOR_shared_info->events)
    195       1.2  bouyer 		printf("stipending events %08lx mask %08lx ilevel %d\n",
    196       1.2  bouyer 		    HYPERVISOR_shared_info->events,
    197       1.2  bouyer 		    HYPERVISOR_shared_info->events_mask, ci->ci_ilevel);
    198       1.2  bouyer #endif
    199       1.2  bouyer 
    200       1.2  bouyer #ifdef EARLY_DEBUG_EVENT
    201       1.2  bouyer 	if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) {
    202       1.2  bouyer 		xen_debug_handler(NULL);
    203       1.2  bouyer 		xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port);
    204       1.2  bouyer 	}
    205       1.2  bouyer #endif
    206       1.2  bouyer 
    207       1.2  bouyer 	/*
    208       1.2  bouyer 	 * we're only called after STIC, so we know that we'll have to
    209       1.2  bouyer 	 * STI at the end
    210       1.2  bouyer 	 */
    211  1.14.2.2  cherry 
    212       1.8  cegger 	while (vci->evtchn_upcall_pending) {
    213       1.2  bouyer 		cli();
    214  1.14.2.2  cherry 
    215       1.8  cegger 		vci->evtchn_upcall_pending = 0;
    216  1.14.2.2  cherry 
    217  1.14.2.2  cherry 		evt_iterate_pending(ci,
    218  1.14.2.2  cherry 				    &vci->evtchn_pending_sel,
    219  1.14.2.2  cherry 				    s->evtchn_pending,
    220  1.14.2.2  cherry 				    s->evtchn_mask,
    221  1.14.2.2  cherry 				    evt_set_pending,
    222  1.14.2.2  cherry 				    &ret);
    223  1.14.2.2  cherry 
    224       1.2  bouyer 		sti();
    225       1.2  bouyer 	}
    226       1.2  bouyer 
    227       1.2  bouyer #if 0
    228       1.2  bouyer 	if (ci->ci_ipending & 0x1)
    229       1.2  bouyer 		printf("stipending events %08lx mask %08lx ilevel %d ipending %08x\n",
    230       1.2  bouyer 		    HYPERVISOR_shared_info->events,
    231       1.2  bouyer 		    HYPERVISOR_shared_info->events_mask, ci->ci_ilevel,
    232       1.2  bouyer 		    ci->ci_ipending);
    233       1.2  bouyer #endif
    234       1.2  bouyer 
    235       1.2  bouyer 	return (ret);
    236       1.2  bouyer }
    237       1.2  bouyer 
    238  1.14.2.2  cherry /* Iterate through pending events and call the event handler */
    239  1.14.2.2  cherry 
    240  1.14.2.2  cherry static inline void
    241  1.14.2.2  cherry evt_do_hypervisor_callback(struct cpu_info *ci,
    242  1.14.2.2  cherry 			   unsigned int port,
    243  1.14.2.2  cherry 			   unsigned int l1i,
    244  1.14.2.2  cherry 			   unsigned int l2i,
    245  1.14.2.2  cherry 			   void *args)
    246  1.14.2.2  cherry {
    247  1.14.2.2  cherry 	KASSERT(args != NULL);
    248  1.14.2.2  cherry 	KASSERT(ci == curcpu());
    249  1.14.2.2  cherry 
    250  1.14.2.2  cherry 	struct intrframe *regs = args;
    251  1.14.2.2  cherry 
    252  1.14.2.2  cherry #ifdef PORT_DEBUG
    253  1.14.2.2  cherry 	if (port == PORT_DEBUG)
    254  1.14.2.2  cherry 		printf("do_hypervisor_callback event %d\n", port);
    255  1.14.2.2  cherry #endif
    256  1.14.2.2  cherry 	if (evtsource[port])
    257  1.14.2.2  cherry 		call_evtchn_do_event(port, regs);
    258  1.14.2.2  cherry #ifdef DOM0OPS
    259  1.14.2.2  cherry 	else  {
    260  1.14.2.2  cherry 		if (ci->ci_ilevel < IPL_HIGH) {
    261  1.14.2.2  cherry 			/* fast path */
    262  1.14.2.2  cherry 			int oipl = ci->ci_ilevel;
    263  1.14.2.2  cherry 			ci->ci_ilevel = IPL_HIGH;
    264  1.14.2.2  cherry 			call_xenevt_event(port);
    265  1.14.2.2  cherry 			ci->ci_ilevel = oipl;
    266  1.14.2.2  cherry 		} else {
    267  1.14.2.2  cherry 			/* set pending event */
    268  1.14.2.2  cherry 			xenevt_setipending(l1i, l2i);
    269  1.14.2.2  cherry 		}
    270  1.14.2.2  cherry 	}
    271  1.14.2.2  cherry #endif
    272  1.14.2.2  cherry }
    273  1.14.2.2  cherry 
    274       1.2  bouyer void
    275       1.2  bouyer do_hypervisor_callback(struct intrframe *regs)
    276       1.2  bouyer {
    277       1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    278       1.2  bouyer 	struct cpu_info *ci;
    279       1.8  cegger 	volatile struct vcpu_info *vci;
    280       1.2  bouyer 	int level;
    281       1.2  bouyer 
    282       1.2  bouyer 	ci = curcpu();
    283       1.8  cegger 	vci = ci->ci_vcpu;
    284       1.2  bouyer 	level = ci->ci_ilevel;
    285       1.2  bouyer 
    286       1.2  bouyer 	// DDD printf("do_hypervisor_callback\n");
    287       1.2  bouyer 
    288       1.2  bouyer #ifdef EARLY_DEBUG_EVENT
    289       1.2  bouyer 	if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) {
    290       1.2  bouyer 		xen_debug_handler(NULL);
    291       1.2  bouyer 		xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port);
    292       1.2  bouyer 	}
    293       1.2  bouyer #endif
    294       1.2  bouyer 
    295       1.8  cegger 	while (vci->evtchn_upcall_pending) {
    296       1.8  cegger 		vci->evtchn_upcall_pending = 0;
    297       1.2  bouyer 
    298  1.14.2.2  cherry 		evt_iterate_pending(ci,
    299  1.14.2.2  cherry 				    &vci->evtchn_pending_sel,
    300  1.14.2.2  cherry 				    s->evtchn_pending,
    301  1.14.2.2  cherry 				    s->evtchn_mask,
    302  1.14.2.2  cherry 				    evt_do_hypervisor_callback,
    303  1.14.2.2  cherry 				    regs);
    304       1.2  bouyer 	}
    305       1.2  bouyer 
    306       1.2  bouyer #ifdef DIAGNOSTIC
    307       1.2  bouyer 	if (level != ci->ci_ilevel)
    308       1.2  bouyer 		printf("hypervisor done %08x level %d/%d ipending %08x\n",
    309       1.8  cegger 		    (uint)vci->evtchn_pending_sel,
    310       1.2  bouyer 		    level, ci->ci_ilevel, ci->ci_ipending);
    311       1.2  bouyer #endif
    312       1.2  bouyer }
    313       1.2  bouyer 
    314       1.2  bouyer void
    315       1.2  bouyer hypervisor_unmask_event(unsigned int ev)
    316       1.2  bouyer {
    317       1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    318       1.8  cegger 	volatile struct vcpu_info *vci = curcpu()->ci_vcpu;
    319       1.8  cegger 
    320       1.2  bouyer #ifdef PORT_DEBUG
    321       1.2  bouyer 	if (ev == PORT_DEBUG)
    322       1.2  bouyer 		printf("hypervisor_unmask_event %d\n", ev);
    323       1.2  bouyer #endif
    324       1.2  bouyer 
    325       1.2  bouyer 	xen_atomic_clear_bit(&s->evtchn_mask[0], ev);
    326       1.2  bouyer 	/*
    327       1.2  bouyer 	 * The following is basically the equivalent of
    328       1.2  bouyer 	 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose the
    329       1.2  bouyer 	 * interrupt edge' if the channel is masked.
    330       1.2  bouyer 	 */
    331       1.2  bouyer 	if (xen_atomic_test_bit(&s->evtchn_pending[0], ev) &&
    332       1.8  cegger 	    !xen_atomic_test_and_set_bit(&vci->evtchn_pending_sel, ev>>LONG_SHIFT)) {
    333       1.8  cegger 		xen_atomic_set_bit(&vci->evtchn_upcall_pending, 0);
    334       1.8  cegger 		if (!vci->evtchn_upcall_mask)
    335       1.2  bouyer 			hypervisor_force_callback();
    336       1.2  bouyer 	}
    337       1.2  bouyer }
    338       1.2  bouyer 
    339       1.2  bouyer void
    340       1.2  bouyer hypervisor_mask_event(unsigned int ev)
    341       1.2  bouyer {
    342       1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    343       1.2  bouyer #ifdef PORT_DEBUG
    344       1.2  bouyer 	if (ev == PORT_DEBUG)
    345       1.2  bouyer 		printf("hypervisor_mask_event %d\n", ev);
    346       1.2  bouyer #endif
    347       1.2  bouyer 
    348       1.2  bouyer 	xen_atomic_set_bit(&s->evtchn_mask[0], ev);
    349       1.2  bouyer }
    350       1.2  bouyer 
    351       1.2  bouyer void
    352       1.2  bouyer hypervisor_clear_event(unsigned int ev)
    353       1.2  bouyer {
    354       1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    355       1.2  bouyer #ifdef PORT_DEBUG
    356       1.2  bouyer 	if (ev == PORT_DEBUG)
    357       1.2  bouyer 		printf("hypervisor_clear_event %d\n", ev);
    358       1.2  bouyer #endif
    359       1.2  bouyer 
    360       1.2  bouyer 	xen_atomic_clear_bit(&s->evtchn_pending[0], ev);
    361       1.2  bouyer }
    362       1.2  bouyer 
    363  1.14.2.2  cherry static inline void
    364  1.14.2.2  cherry evt_enable_event(struct cpu_info *ci,
    365  1.14.2.2  cherry 	       unsigned int port,
    366  1.14.2.2  cherry 	       unsigned int l1i,
    367  1.14.2.2  cherry 	       unsigned int l2i,
    368  1.14.2.2  cherry 	       void *args)
    369  1.14.2.2  cherry {
    370  1.14.2.2  cherry 	KASSERT(ci != NULL);
    371  1.14.2.2  cherry 	KASSERT(args == NULL);
    372  1.14.2.2  cherry 	hypervisor_enable_event(port);
    373  1.14.2.2  cherry }
    374  1.14.2.2  cherry 
    375       1.2  bouyer void
    376       1.2  bouyer hypervisor_enable_ipl(unsigned int ipl)
    377       1.2  bouyer {
    378       1.2  bouyer 	struct cpu_info *ci = curcpu();
    379       1.2  bouyer 
    380       1.2  bouyer 	/*
    381       1.2  bouyer 	 * enable all events for ipl. As we only set an event in ipl_evt_mask
    382       1.2  bouyer 	 * for its lowest IPL, and pending IPLs are processed high to low,
    383       1.2  bouyer 	 * we know that all callback for this event have been processed.
    384       1.2  bouyer 	 */
    385       1.2  bouyer 
    386  1.14.2.2  cherry 	evt_iterate_pending(ci,
    387  1.14.2.2  cherry 			    &ci->ci_isources[ipl]->ipl_evt_mask1,
    388  1.14.2.2  cherry 			    ci->ci_isources[ipl]->ipl_evt_mask2,
    389  1.14.2.2  cherry 			    NULL,
    390  1.14.2.2  cherry 			    evt_enable_event,
    391  1.14.2.2  cherry 			    NULL);
    392       1.2  bouyer 
    393       1.2  bouyer }
    394       1.2  bouyer 
    395       1.2  bouyer void
    396  1.14.2.2  cherry hypervisor_set_ipending(struct cpu_info *ci,
    397  1.14.2.2  cherry 			uint32_t iplmask,
    398  1.14.2.2  cherry 			int l1, int l2)
    399       1.2  bouyer {
    400       1.2  bouyer 	int ipl;
    401       1.2  bouyer 
    402       1.2  bouyer 	/* set pending bit for the appropriate IPLs */
    403       1.2  bouyer 	ci->ci_ipending |= iplmask;
    404       1.2  bouyer 
    405       1.2  bouyer 	/*
    406       1.2  bouyer 	 * And set event pending bit for the lowest IPL. As IPL are handled
    407       1.2  bouyer 	 * from high to low, this ensure that all callbacks will have been
    408       1.2  bouyer 	 * called when we ack the event
    409       1.2  bouyer 	 */
    410       1.2  bouyer 	ipl = ffs(iplmask);
    411       1.2  bouyer 	KASSERT(ipl > 0);
    412       1.2  bouyer 	ipl--;
    413  1.14.2.1  cherry 	KASSERT(ipl < NIPL);
    414  1.14.2.1  cherry 	KASSERT(ci->ci_isources[ipl] != NULL);
    415       1.6  bouyer 	ci->ci_isources[ipl]->ipl_evt_mask1 |= 1UL << l1;
    416       1.6  bouyer 	ci->ci_isources[ipl]->ipl_evt_mask2[l1] |= 1UL << l2;
    417       1.2  bouyer }
    418      1.10  bouyer 
    419      1.10  bouyer void
    420      1.12  cegger hypervisor_machdep_attach(void)
    421      1.12  cegger {
    422      1.10  bouyer  	/* dom0 does not require the arch-dependent P2M translation table */
    423      1.11  cegger 	if ( !xendomain_is_dom0() ) {
    424      1.10  bouyer 		build_p2m_frame_list_list();
    425      1.10  bouyer 	}
    426      1.10  bouyer }
    427      1.10  bouyer 
    428      1.10  bouyer /*
    429      1.10  bouyer  * Generate the p2m_frame_list_list table,
    430      1.10  bouyer  * needed for guest save/restore
    431      1.10  bouyer  */
    432      1.10  bouyer static void
    433      1.12  cegger build_p2m_frame_list_list(void)
    434      1.12  cegger {
    435      1.10  bouyer         int fpp; /* number of page (frame) pointer per page */
    436      1.10  bouyer         unsigned long max_pfn;
    437      1.10  bouyer         /*
    438      1.10  bouyer          * The p2m list is composed of three levels of indirection,
    439      1.10  bouyer          * each layer containing MFNs pointing to lower level pages
    440      1.10  bouyer          * The indirection is used to convert a given PFN to its MFN
    441      1.10  bouyer          * Each N level page can point to @fpp (N-1) level pages
    442      1.10  bouyer          * For example, for x86 32bit, we have:
    443      1.10  bouyer          * - PAGE_SIZE: 4096 bytes
    444      1.10  bouyer          * - fpp: 1024 (one L3 page can address 1024 L2 pages)
    445      1.10  bouyer          * A L1 page contains the list of MFN we are looking for
    446      1.10  bouyer          */
    447      1.10  bouyer         max_pfn = xen_start_info.nr_pages;
    448      1.14     jym         fpp = PAGE_SIZE / sizeof(xen_pfn_t);
    449      1.10  bouyer 
    450      1.10  bouyer         /* we only need one L3 page */
    451      1.14     jym         l3_p2m_page = (vaddr_t *)uvm_km_alloc(kernel_map, PAGE_SIZE,
    452      1.14     jym 	    PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_NOWAIT);
    453      1.10  bouyer         if (l3_p2m_page == NULL)
    454      1.10  bouyer                 panic("could not allocate memory for l3_p2m_page");
    455      1.10  bouyer 
    456      1.10  bouyer         /*
    457      1.10  bouyer          * Determine how many L2 pages we need for the mapping
    458      1.10  bouyer          * Each L2 can map a total of @fpp L1 pages
    459      1.10  bouyer          */
    460      1.10  bouyer         l2_p2m_page_size = howmany(max_pfn, fpp);
    461      1.10  bouyer 
    462      1.14     jym         l2_p2m_page = (vaddr_t *)uvm_km_alloc(kernel_map,
    463      1.14     jym 	    l2_p2m_page_size * PAGE_SIZE,
    464      1.14     jym 	    PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_NOWAIT);
    465      1.10  bouyer         if (l2_p2m_page == NULL)
    466      1.10  bouyer                 panic("could not allocate memory for l2_p2m_page");
    467      1.10  bouyer 
    468      1.10  bouyer         /* We now have L3 and L2 pages ready, update L1 mapping */
    469      1.10  bouyer         update_p2m_frame_list_list();
    470      1.10  bouyer 
    471      1.10  bouyer }
    472      1.10  bouyer 
    473      1.10  bouyer /*
    474      1.10  bouyer  * Update the L1 p2m_frame_list_list mapping (during guest boot or resume)
    475      1.10  bouyer  */
    476      1.10  bouyer static void
    477      1.12  cegger update_p2m_frame_list_list(void)
    478      1.12  cegger {
    479      1.10  bouyer         int i;
    480      1.10  bouyer         int fpp; /* number of page (frame) pointer per page */
    481      1.10  bouyer         unsigned long max_pfn;
    482      1.10  bouyer 
    483      1.10  bouyer         max_pfn = xen_start_info.nr_pages;
    484      1.14     jym         fpp = PAGE_SIZE / sizeof(xen_pfn_t);
    485      1.10  bouyer 
    486      1.10  bouyer         for (i = 0; i < l2_p2m_page_size; i++) {
    487      1.10  bouyer                 /*
    488      1.10  bouyer                  * Each time we start a new L2 page,
    489      1.10  bouyer                  * store its MFN in the L3 page
    490      1.10  bouyer                  */
    491      1.10  bouyer                 if ((i % fpp) == 0) {
    492      1.10  bouyer                         l3_p2m_page[i/fpp] = vtomfn(
    493      1.10  bouyer                                 (vaddr_t)&l2_p2m_page[i]);
    494      1.10  bouyer                 }
    495      1.10  bouyer                 /*
    496      1.10  bouyer                  * we use a shortcut
    497      1.10  bouyer                  * since @xpmap_phys_to_machine_mapping array
    498      1.10  bouyer                  * already contains PFN to MFN mapping, we just
    499      1.10  bouyer                  * set the l2_p2m_page MFN pointer to the MFN of the
    500      1.10  bouyer                  * according frame of @xpmap_phys_to_machine_mapping
    501      1.10  bouyer                  */
    502      1.10  bouyer                 l2_p2m_page[i] = vtomfn((vaddr_t)
    503      1.10  bouyer                         &xpmap_phys_to_machine_mapping[i*fpp]);
    504      1.10  bouyer         }
    505      1.10  bouyer 
    506      1.10  bouyer         HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list_list =
    507      1.10  bouyer                                         vtomfn((vaddr_t)l3_p2m_page);
    508      1.10  bouyer         HYPERVISOR_shared_info->arch.max_pfn = max_pfn;
    509      1.10  bouyer 
    510      1.10  bouyer }
    511