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hypervisor_machdep.c revision 1.16
      1  1.16     jym /*	$NetBSD: hypervisor_machdep.c,v 1.16 2011/09/20 00:12:24 jym Exp $	*/
      2   1.2  bouyer 
      3   1.2  bouyer /*
      4   1.2  bouyer  *
      5   1.2  bouyer  * Copyright (c) 2004 Christian Limpach.
      6   1.2  bouyer  * All rights reserved.
      7   1.2  bouyer  *
      8   1.2  bouyer  * Redistribution and use in source and binary forms, with or without
      9   1.2  bouyer  * modification, are permitted provided that the following conditions
     10   1.2  bouyer  * are met:
     11   1.2  bouyer  * 1. Redistributions of source code must retain the above copyright
     12   1.2  bouyer  *    notice, this list of conditions and the following disclaimer.
     13   1.2  bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     14   1.2  bouyer  *    notice, this list of conditions and the following disclaimer in the
     15   1.2  bouyer  *    documentation and/or other materials provided with the distribution.
     16   1.2  bouyer  *
     17   1.2  bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18   1.2  bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19   1.2  bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20   1.2  bouyer  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21   1.2  bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22   1.2  bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23   1.2  bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24   1.2  bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25   1.2  bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26   1.2  bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27   1.2  bouyer  */
     28   1.2  bouyer 
     29   1.2  bouyer /******************************************************************************
     30   1.2  bouyer  * hypervisor.c
     31   1.2  bouyer  *
     32   1.2  bouyer  * Communication to/from hypervisor.
     33   1.2  bouyer  *
     34   1.2  bouyer  * Copyright (c) 2002-2004, K A Fraser
     35   1.2  bouyer  *
     36   1.2  bouyer  * Permission is hereby granted, free of charge, to any person obtaining a copy
     37   1.2  bouyer  * of this software and associated documentation files (the "Software"), to
     38   1.2  bouyer  * deal in the Software without restriction, including without limitation the
     39   1.2  bouyer  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
     40   1.2  bouyer  * sell copies of the Software, and to permit persons to whom the Software is
     41   1.2  bouyer  * furnished to do so, subject to the following conditions:
     42   1.2  bouyer  *
     43   1.2  bouyer  * The above copyright notice and this permission notice shall be included in
     44   1.2  bouyer  * all copies or substantial portions of the Software.
     45   1.2  bouyer  *
     46   1.2  bouyer  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     47   1.2  bouyer  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     48   1.2  bouyer  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
     49   1.2  bouyer  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     50   1.2  bouyer  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     51   1.2  bouyer  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     52   1.2  bouyer  * DEALINGS IN THE SOFTWARE.
     53   1.2  bouyer  */
     54   1.2  bouyer 
     55   1.2  bouyer 
     56   1.2  bouyer #include <sys/cdefs.h>
     57  1.16     jym __KERNEL_RCSID(0, "$NetBSD: hypervisor_machdep.c,v 1.16 2011/09/20 00:12:24 jym Exp $");
     58   1.2  bouyer 
     59   1.2  bouyer #include <sys/param.h>
     60   1.2  bouyer #include <sys/systm.h>
     61  1.10  bouyer #include <sys/kmem.h>
     62  1.10  bouyer 
     63  1.10  bouyer #include <uvm/uvm_extern.h>
     64  1.10  bouyer 
     65  1.10  bouyer #include <machine/vmparam.h>
     66  1.10  bouyer #include <machine/pmap.h>
     67   1.2  bouyer 
     68   1.2  bouyer #include <xen/xen.h>
     69   1.2  bouyer #include <xen/hypervisor.h>
     70   1.2  bouyer #include <xen/evtchn.h>
     71  1.10  bouyer #include <xen/xenpmap.h>
     72   1.2  bouyer 
     73   1.2  bouyer #include "opt_xen.h"
     74   1.2  bouyer 
     75  1.10  bouyer /*
     76  1.10  bouyer  * arch-dependent p2m frame lists list (L3 and L2)
     77  1.10  bouyer  * used by Xen for save/restore mappings
     78  1.10  bouyer  */
     79  1.10  bouyer static unsigned long * l3_p2m_page;
     80  1.10  bouyer static unsigned long * l2_p2m_page;
     81  1.10  bouyer static int l2_p2m_page_size; /* size of L2 page, in pages */
     82  1.10  bouyer 
     83  1.10  bouyer static void build_p2m_frame_list_list(void);
     84  1.10  bouyer static void update_p2m_frame_list_list(void);
     85  1.10  bouyer 
     86   1.2  bouyer // #define PORT_DEBUG 4
     87   1.2  bouyer // #define EARLY_DEBUG_EVENT
     88   1.2  bouyer 
     89  1.15  cherry /* callback function type */
     90  1.15  cherry typedef void (*iterate_func_t)(struct cpu_info *, unsigned int,
     91  1.15  cherry 			       unsigned int, unsigned int, void *);
     92  1.15  cherry 
     93  1.15  cherry static inline void
     94  1.15  cherry evt_iterate_bits(struct cpu_info *ci, volatile unsigned long *pendingl1,
     95  1.15  cherry 		 volatile unsigned long *pendingl2,
     96  1.15  cherry 		 volatile unsigned long *mask,
     97  1.15  cherry 		 iterate_func_t iterate_pending, void *iterate_args)
     98  1.15  cherry {
     99  1.15  cherry 
    100  1.15  cherry 	KASSERT(pendingl1 != NULL);
    101  1.15  cherry 	KASSERT(pendingl2 != NULL);
    102  1.15  cherry 
    103  1.15  cherry 	unsigned long l1, l2;
    104  1.15  cherry 	unsigned int l1i, l2i, port;
    105  1.15  cherry 
    106  1.15  cherry 	l1 = xen_atomic_xchg(pendingl1, 0);
    107  1.15  cherry 	while ((l1i = xen_ffs(l1)) != 0) {
    108  1.15  cherry 		l1i--;
    109  1.15  cherry 		l1 &= ~(1UL << l1i);
    110  1.15  cherry 
    111  1.15  cherry 		l2 = pendingl2[l1i] & (mask != NULL ? ~mask[l1i] : -1UL);
    112  1.15  cherry 
    113  1.15  cherry 		if (mask != NULL) xen_atomic_setbits_l(&mask[l1i], l2);
    114  1.15  cherry 		xen_atomic_clearbits_l(&pendingl2[l1i], l2);
    115  1.15  cherry 
    116  1.15  cherry 		while ((l2i = xen_ffs(l2)) != 0) {
    117  1.15  cherry 			l2i--;
    118  1.15  cherry 			l2 &= ~(1UL << l2i);
    119  1.15  cherry 
    120  1.15  cherry 			port = (l1i << LONG_SHIFT) + l2i;
    121  1.15  cherry 
    122  1.15  cherry 			iterate_pending(ci, port, l1i, l2i, iterate_args);
    123  1.15  cherry 		}
    124  1.15  cherry 	}
    125  1.15  cherry }
    126  1.15  cherry 
    127  1.15  cherry /*
    128  1.15  cherry  * Set per-cpu "pending" information for outstanding events that
    129  1.15  cherry  * cannot be processed now.
    130  1.15  cherry  */
    131  1.15  cherry 
    132  1.15  cherry static inline void
    133  1.15  cherry evt_set_pending(struct cpu_info *ci, unsigned int port, unsigned int l1i,
    134  1.15  cherry 		unsigned int l2i, void *args)
    135  1.15  cherry {
    136  1.15  cherry 
    137  1.15  cherry 	KASSERT(args != NULL);
    138  1.15  cherry 	KASSERT(ci != NULL);
    139  1.15  cherry 
    140  1.15  cherry 	int *ret = args;
    141  1.15  cherry 
    142  1.15  cherry 	if (evtsource[port]) {
    143  1.15  cherry 		hypervisor_set_ipending(ci, evtsource[port]->ev_imask,
    144  1.15  cherry 		    l1i, l2i);
    145  1.15  cherry 		evtsource[port]->ev_evcnt.ev_count++;
    146  1.15  cherry 		if (*ret == 0 && ci->ci_ilevel <
    147  1.15  cherry 		    evtsource[port]->ev_maxlevel)
    148  1.15  cherry 			*ret = 1;
    149  1.15  cherry 	}
    150  1.15  cherry #ifdef DOM0OPS
    151  1.15  cherry 	else  {
    152  1.15  cherry 		/* set pending event */
    153  1.15  cherry 		xenevt_setipending(l1i, l2i);
    154  1.15  cherry 	}
    155  1.15  cherry #endif
    156  1.15  cherry }
    157  1.15  cherry 
    158   1.2  bouyer int stipending(void);
    159   1.2  bouyer int
    160   1.7  cegger stipending(void)
    161   1.2  bouyer {
    162   1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    163   1.2  bouyer 	struct cpu_info *ci;
    164   1.8  cegger 	volatile struct vcpu_info *vci;
    165   1.2  bouyer 	int ret;
    166   1.2  bouyer 
    167   1.2  bouyer 	ret = 0;
    168   1.2  bouyer 	ci = curcpu();
    169   1.8  cegger 	vci = ci->ci_vcpu;
    170   1.2  bouyer 
    171   1.2  bouyer #if 0
    172   1.2  bouyer 	if (HYPERVISOR_shared_info->events)
    173   1.2  bouyer 		printf("stipending events %08lx mask %08lx ilevel %d\n",
    174   1.2  bouyer 		    HYPERVISOR_shared_info->events,
    175   1.2  bouyer 		    HYPERVISOR_shared_info->events_mask, ci->ci_ilevel);
    176   1.2  bouyer #endif
    177   1.2  bouyer 
    178   1.2  bouyer #ifdef EARLY_DEBUG_EVENT
    179   1.2  bouyer 	if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) {
    180   1.2  bouyer 		xen_debug_handler(NULL);
    181   1.2  bouyer 		xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port);
    182   1.2  bouyer 	}
    183   1.2  bouyer #endif
    184   1.2  bouyer 
    185   1.2  bouyer 	/*
    186   1.2  bouyer 	 * we're only called after STIC, so we know that we'll have to
    187   1.2  bouyer 	 * STI at the end
    188   1.2  bouyer 	 */
    189  1.15  cherry 
    190   1.8  cegger 	while (vci->evtchn_upcall_pending) {
    191   1.2  bouyer 		cli();
    192  1.15  cherry 
    193   1.8  cegger 		vci->evtchn_upcall_pending = 0;
    194  1.15  cherry 
    195  1.15  cherry 		evt_iterate_bits(ci, &vci->evtchn_pending_sel,
    196  1.15  cherry 		    s->evtchn_pending, s->evtchn_mask,
    197  1.15  cherry 		    evt_set_pending, &ret);
    198  1.15  cherry 
    199   1.2  bouyer 		sti();
    200   1.2  bouyer 	}
    201   1.2  bouyer 
    202   1.2  bouyer #if 0
    203   1.2  bouyer 	if (ci->ci_ipending & 0x1)
    204   1.2  bouyer 		printf("stipending events %08lx mask %08lx ilevel %d ipending %08x\n",
    205   1.2  bouyer 		    HYPERVISOR_shared_info->events,
    206   1.2  bouyer 		    HYPERVISOR_shared_info->events_mask, ci->ci_ilevel,
    207   1.2  bouyer 		    ci->ci_ipending);
    208   1.2  bouyer #endif
    209   1.2  bouyer 
    210   1.2  bouyer 	return (ret);
    211   1.2  bouyer }
    212   1.2  bouyer 
    213  1.15  cherry /* Iterate through pending events and call the event handler */
    214  1.15  cherry 
    215  1.15  cherry static inline void
    216  1.15  cherry evt_do_hypervisor_callback(struct cpu_info *ci, unsigned int port,
    217  1.15  cherry 			   unsigned int l1i, unsigned int l2i, void *args)
    218  1.15  cherry {
    219  1.15  cherry 	KASSERT(args != NULL);
    220  1.15  cherry 	KASSERT(ci == curcpu());
    221  1.15  cherry 
    222  1.15  cherry 	struct intrframe *regs = args;
    223  1.15  cherry 
    224  1.15  cherry #ifdef PORT_DEBUG
    225  1.15  cherry 	if (port == PORT_DEBUG)
    226  1.15  cherry 		printf("do_hypervisor_callback event %d\n", port);
    227  1.15  cherry #endif
    228  1.15  cherry 	if (evtsource[port])
    229  1.15  cherry 		call_evtchn_do_event(port, regs);
    230  1.15  cherry #ifdef DOM0OPS
    231  1.15  cherry 	else  {
    232  1.15  cherry 		if (ci->ci_ilevel < IPL_HIGH) {
    233  1.15  cherry 			/* fast path */
    234  1.15  cherry 			int oipl = ci->ci_ilevel;
    235  1.15  cherry 			ci->ci_ilevel = IPL_HIGH;
    236  1.15  cherry 			call_xenevt_event(port);
    237  1.15  cherry 			ci->ci_ilevel = oipl;
    238  1.15  cherry 		} else {
    239  1.15  cherry 			/* set pending event */
    240  1.15  cherry 			xenevt_setipending(l1i, l2i);
    241  1.15  cherry 		}
    242  1.15  cherry 	}
    243  1.15  cherry #endif
    244  1.15  cherry }
    245  1.15  cherry 
    246   1.2  bouyer void
    247   1.2  bouyer do_hypervisor_callback(struct intrframe *regs)
    248   1.2  bouyer {
    249   1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    250   1.2  bouyer 	struct cpu_info *ci;
    251   1.8  cegger 	volatile struct vcpu_info *vci;
    252   1.2  bouyer 	int level;
    253   1.2  bouyer 
    254   1.2  bouyer 	ci = curcpu();
    255   1.8  cegger 	vci = ci->ci_vcpu;
    256   1.2  bouyer 	level = ci->ci_ilevel;
    257   1.2  bouyer 
    258   1.2  bouyer 	// DDD printf("do_hypervisor_callback\n");
    259   1.2  bouyer 
    260   1.2  bouyer #ifdef EARLY_DEBUG_EVENT
    261   1.2  bouyer 	if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) {
    262   1.2  bouyer 		xen_debug_handler(NULL);
    263   1.2  bouyer 		xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port);
    264   1.2  bouyer 	}
    265   1.2  bouyer #endif
    266   1.2  bouyer 
    267   1.8  cegger 	while (vci->evtchn_upcall_pending) {
    268   1.8  cegger 		vci->evtchn_upcall_pending = 0;
    269   1.2  bouyer 
    270  1.15  cherry 		evt_iterate_bits(ci, &vci->evtchn_pending_sel,
    271  1.15  cherry 		    s->evtchn_pending, s->evtchn_mask,
    272  1.15  cherry 		    evt_do_hypervisor_callback, regs);
    273   1.2  bouyer 	}
    274   1.2  bouyer 
    275   1.2  bouyer #ifdef DIAGNOSTIC
    276   1.2  bouyer 	if (level != ci->ci_ilevel)
    277   1.2  bouyer 		printf("hypervisor done %08x level %d/%d ipending %08x\n",
    278   1.8  cegger 		    (uint)vci->evtchn_pending_sel,
    279   1.2  bouyer 		    level, ci->ci_ilevel, ci->ci_ipending);
    280   1.2  bouyer #endif
    281   1.2  bouyer }
    282   1.2  bouyer 
    283   1.2  bouyer void
    284   1.2  bouyer hypervisor_unmask_event(unsigned int ev)
    285   1.2  bouyer {
    286   1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    287   1.8  cegger 	volatile struct vcpu_info *vci = curcpu()->ci_vcpu;
    288   1.8  cegger 
    289   1.2  bouyer #ifdef PORT_DEBUG
    290   1.2  bouyer 	if (ev == PORT_DEBUG)
    291   1.2  bouyer 		printf("hypervisor_unmask_event %d\n", ev);
    292   1.2  bouyer #endif
    293   1.2  bouyer 
    294   1.2  bouyer 	xen_atomic_clear_bit(&s->evtchn_mask[0], ev);
    295   1.2  bouyer 	/*
    296   1.2  bouyer 	 * The following is basically the equivalent of
    297   1.2  bouyer 	 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose the
    298   1.2  bouyer 	 * interrupt edge' if the channel is masked.
    299   1.2  bouyer 	 */
    300   1.2  bouyer 	if (xen_atomic_test_bit(&s->evtchn_pending[0], ev) &&
    301   1.8  cegger 	    !xen_atomic_test_and_set_bit(&vci->evtchn_pending_sel, ev>>LONG_SHIFT)) {
    302   1.8  cegger 		xen_atomic_set_bit(&vci->evtchn_upcall_pending, 0);
    303   1.8  cegger 		if (!vci->evtchn_upcall_mask)
    304   1.2  bouyer 			hypervisor_force_callback();
    305   1.2  bouyer 	}
    306   1.2  bouyer }
    307   1.2  bouyer 
    308   1.2  bouyer void
    309   1.2  bouyer hypervisor_mask_event(unsigned int ev)
    310   1.2  bouyer {
    311   1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    312   1.2  bouyer #ifdef PORT_DEBUG
    313   1.2  bouyer 	if (ev == PORT_DEBUG)
    314   1.2  bouyer 		printf("hypervisor_mask_event %d\n", ev);
    315   1.2  bouyer #endif
    316   1.2  bouyer 
    317   1.2  bouyer 	xen_atomic_set_bit(&s->evtchn_mask[0], ev);
    318   1.2  bouyer }
    319   1.2  bouyer 
    320   1.2  bouyer void
    321   1.2  bouyer hypervisor_clear_event(unsigned int ev)
    322   1.2  bouyer {
    323   1.2  bouyer 	volatile shared_info_t *s = HYPERVISOR_shared_info;
    324   1.2  bouyer #ifdef PORT_DEBUG
    325   1.2  bouyer 	if (ev == PORT_DEBUG)
    326   1.2  bouyer 		printf("hypervisor_clear_event %d\n", ev);
    327   1.2  bouyer #endif
    328   1.2  bouyer 
    329   1.2  bouyer 	xen_atomic_clear_bit(&s->evtchn_pending[0], ev);
    330   1.2  bouyer }
    331   1.2  bouyer 
    332  1.15  cherry static inline void
    333  1.15  cherry evt_enable_event(struct cpu_info *ci, unsigned int port,
    334  1.15  cherry 		 unsigned int l1i, unsigned int l2i, void *args)
    335  1.15  cherry {
    336  1.15  cherry 	KASSERT(ci != NULL);
    337  1.15  cherry 	KASSERT(args == NULL);
    338  1.15  cherry 	hypervisor_enable_event(port);
    339  1.15  cherry }
    340  1.15  cherry 
    341   1.2  bouyer void
    342   1.2  bouyer hypervisor_enable_ipl(unsigned int ipl)
    343   1.2  bouyer {
    344   1.2  bouyer 	struct cpu_info *ci = curcpu();
    345   1.2  bouyer 
    346   1.2  bouyer 	/*
    347   1.2  bouyer 	 * enable all events for ipl. As we only set an event in ipl_evt_mask
    348   1.2  bouyer 	 * for its lowest IPL, and pending IPLs are processed high to low,
    349   1.2  bouyer 	 * we know that all callback for this event have been processed.
    350   1.2  bouyer 	 */
    351   1.2  bouyer 
    352  1.15  cherry 	evt_iterate_bits(ci, &ci->ci_isources[ipl]->ipl_evt_mask1,
    353  1.15  cherry 	    ci->ci_isources[ipl]->ipl_evt_mask2, NULL,
    354  1.15  cherry 	    evt_enable_event, NULL);
    355   1.2  bouyer 
    356   1.2  bouyer }
    357   1.2  bouyer 
    358   1.2  bouyer void
    359  1.15  cherry hypervisor_set_ipending(struct cpu_info *ci, uint32_t iplmask, int l1, int l2)
    360   1.2  bouyer {
    361   1.2  bouyer 	int ipl;
    362   1.2  bouyer 
    363   1.2  bouyer 	/* set pending bit for the appropriate IPLs */
    364   1.2  bouyer 	ci->ci_ipending |= iplmask;
    365   1.2  bouyer 
    366   1.2  bouyer 	/*
    367   1.2  bouyer 	 * And set event pending bit for the lowest IPL. As IPL are handled
    368   1.2  bouyer 	 * from high to low, this ensure that all callbacks will have been
    369   1.2  bouyer 	 * called when we ack the event
    370   1.2  bouyer 	 */
    371   1.2  bouyer 	ipl = ffs(iplmask);
    372   1.2  bouyer 	KASSERT(ipl > 0);
    373   1.2  bouyer 	ipl--;
    374  1.15  cherry 	KASSERT(ipl < NIPL);
    375  1.15  cherry 	KASSERT(ci->ci_isources[ipl] != NULL);
    376   1.6  bouyer 	ci->ci_isources[ipl]->ipl_evt_mask1 |= 1UL << l1;
    377   1.6  bouyer 	ci->ci_isources[ipl]->ipl_evt_mask2[l1] |= 1UL << l2;
    378   1.2  bouyer }
    379  1.10  bouyer 
    380  1.10  bouyer void
    381  1.12  cegger hypervisor_machdep_attach(void)
    382  1.12  cegger {
    383  1.10  bouyer  	/* dom0 does not require the arch-dependent P2M translation table */
    384  1.16     jym 	if (!xendomain_is_dom0()) {
    385  1.10  bouyer 		build_p2m_frame_list_list();
    386  1.16     jym 		sysctl_xen_suspend_setup();
    387  1.10  bouyer 	}
    388  1.10  bouyer }
    389  1.10  bouyer 
    390  1.16     jym void
    391  1.16     jym hypervisor_machdep_resume(void)
    392  1.16     jym {
    393  1.16     jym 	/* dom0 does not require the arch-dependent P2M translation table */
    394  1.16     jym 	if (!xendomain_is_dom0())
    395  1.16     jym 		update_p2m_frame_list_list();
    396  1.16     jym }
    397  1.16     jym 
    398  1.10  bouyer /*
    399  1.10  bouyer  * Generate the p2m_frame_list_list table,
    400  1.10  bouyer  * needed for guest save/restore
    401  1.10  bouyer  */
    402  1.10  bouyer static void
    403  1.12  cegger build_p2m_frame_list_list(void)
    404  1.12  cegger {
    405  1.10  bouyer         int fpp; /* number of page (frame) pointer per page */
    406  1.10  bouyer         unsigned long max_pfn;
    407  1.10  bouyer         /*
    408  1.10  bouyer          * The p2m list is composed of three levels of indirection,
    409  1.10  bouyer          * each layer containing MFNs pointing to lower level pages
    410  1.10  bouyer          * The indirection is used to convert a given PFN to its MFN
    411  1.10  bouyer          * Each N level page can point to @fpp (N-1) level pages
    412  1.10  bouyer          * For example, for x86 32bit, we have:
    413  1.10  bouyer          * - PAGE_SIZE: 4096 bytes
    414  1.10  bouyer          * - fpp: 1024 (one L3 page can address 1024 L2 pages)
    415  1.10  bouyer          * A L1 page contains the list of MFN we are looking for
    416  1.10  bouyer          */
    417  1.10  bouyer         max_pfn = xen_start_info.nr_pages;
    418  1.14     jym         fpp = PAGE_SIZE / sizeof(xen_pfn_t);
    419  1.10  bouyer 
    420  1.10  bouyer         /* we only need one L3 page */
    421  1.14     jym         l3_p2m_page = (vaddr_t *)uvm_km_alloc(kernel_map, PAGE_SIZE,
    422  1.14     jym 	    PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_NOWAIT);
    423  1.10  bouyer         if (l3_p2m_page == NULL)
    424  1.10  bouyer                 panic("could not allocate memory for l3_p2m_page");
    425  1.10  bouyer 
    426  1.10  bouyer         /*
    427  1.10  bouyer          * Determine how many L2 pages we need for the mapping
    428  1.10  bouyer          * Each L2 can map a total of @fpp L1 pages
    429  1.10  bouyer          */
    430  1.10  bouyer         l2_p2m_page_size = howmany(max_pfn, fpp);
    431  1.10  bouyer 
    432  1.14     jym         l2_p2m_page = (vaddr_t *)uvm_km_alloc(kernel_map,
    433  1.14     jym 	    l2_p2m_page_size * PAGE_SIZE,
    434  1.14     jym 	    PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_NOWAIT);
    435  1.10  bouyer         if (l2_p2m_page == NULL)
    436  1.10  bouyer                 panic("could not allocate memory for l2_p2m_page");
    437  1.10  bouyer 
    438  1.10  bouyer         /* We now have L3 and L2 pages ready, update L1 mapping */
    439  1.10  bouyer         update_p2m_frame_list_list();
    440  1.10  bouyer 
    441  1.10  bouyer }
    442  1.10  bouyer 
    443  1.10  bouyer /*
    444  1.10  bouyer  * Update the L1 p2m_frame_list_list mapping (during guest boot or resume)
    445  1.10  bouyer  */
    446  1.10  bouyer static void
    447  1.12  cegger update_p2m_frame_list_list(void)
    448  1.12  cegger {
    449  1.10  bouyer         int i;
    450  1.10  bouyer         int fpp; /* number of page (frame) pointer per page */
    451  1.10  bouyer         unsigned long max_pfn;
    452  1.10  bouyer 
    453  1.10  bouyer         max_pfn = xen_start_info.nr_pages;
    454  1.14     jym         fpp = PAGE_SIZE / sizeof(xen_pfn_t);
    455  1.10  bouyer 
    456  1.10  bouyer         for (i = 0; i < l2_p2m_page_size; i++) {
    457  1.10  bouyer                 /*
    458  1.10  bouyer                  * Each time we start a new L2 page,
    459  1.10  bouyer                  * store its MFN in the L3 page
    460  1.10  bouyer                  */
    461  1.10  bouyer                 if ((i % fpp) == 0) {
    462  1.10  bouyer                         l3_p2m_page[i/fpp] = vtomfn(
    463  1.10  bouyer                                 (vaddr_t)&l2_p2m_page[i]);
    464  1.10  bouyer                 }
    465  1.10  bouyer                 /*
    466  1.10  bouyer                  * we use a shortcut
    467  1.10  bouyer                  * since @xpmap_phys_to_machine_mapping array
    468  1.10  bouyer                  * already contains PFN to MFN mapping, we just
    469  1.10  bouyer                  * set the l2_p2m_page MFN pointer to the MFN of the
    470  1.10  bouyer                  * according frame of @xpmap_phys_to_machine_mapping
    471  1.10  bouyer                  */
    472  1.10  bouyer                 l2_p2m_page[i] = vtomfn((vaddr_t)
    473  1.10  bouyer                         &xpmap_phys_to_machine_mapping[i*fpp]);
    474  1.10  bouyer         }
    475  1.10  bouyer 
    476  1.10  bouyer         HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list_list =
    477  1.10  bouyer                                         vtomfn((vaddr_t)l3_p2m_page);
    478  1.10  bouyer         HYPERVISOR_shared_info->arch.max_pfn = max_pfn;
    479  1.10  bouyer 
    480  1.10  bouyer }
    481