hypervisor_machdep.c revision 1.2.4.2
1 /* $NetBSD: hypervisor_machdep.c,v 1.2.4.2 2007/12/03 19:04:40 ad Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 2004 Christian Limpach. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Christian Limpach. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /****************************************************************************** 35 * hypervisor.c 36 * 37 * Communication to/from hypervisor. 38 * 39 * Copyright (c) 2002-2004, K A Fraser 40 * 41 * Permission is hereby granted, free of charge, to any person obtaining a copy 42 * of this software and associated documentation files (the "Software"), to 43 * deal in the Software without restriction, including without limitation the 44 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 45 * sell copies of the Software, and to permit persons to whom the Software is 46 * furnished to do so, subject to the following conditions: 47 * 48 * The above copyright notice and this permission notice shall be included in 49 * all copies or substantial portions of the Software. 50 * 51 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 52 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 53 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 54 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 55 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 56 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 57 * DEALINGS IN THE SOFTWARE. 58 */ 59 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: hypervisor_machdep.c,v 1.2.4.2 2007/12/03 19:04:40 ad Exp $"); 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 67 #include <xen/xen.h> 68 #include <xen/hypervisor.h> 69 #include <xen/evtchn.h> 70 #include <machine/atomic.h> 71 72 #include "opt_xen.h" 73 74 // #define PORT_DEBUG 4 75 // #define EARLY_DEBUG_EVENT 76 77 #ifdef EARLY_DEBUG_EVENT 78 extern int debug_port; 79 extern int xen_debug_handler(void *); 80 #endif 81 82 int stipending(void); 83 int 84 stipending() 85 { 86 uint32_t l1; 87 unsigned long l2; 88 unsigned int l1i, l2i, port; 89 volatile shared_info_t *s = HYPERVISOR_shared_info; 90 struct cpu_info *ci; 91 int ret; 92 93 ret = 0; 94 ci = curcpu(); 95 96 #if 0 97 if (HYPERVISOR_shared_info->events) 98 printf("stipending events %08lx mask %08lx ilevel %d\n", 99 HYPERVISOR_shared_info->events, 100 HYPERVISOR_shared_info->events_mask, ci->ci_ilevel); 101 #endif 102 103 #ifdef EARLY_DEBUG_EVENT 104 if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) { 105 xen_debug_handler(NULL); 106 xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port); 107 } 108 #endif 109 110 /* 111 * we're only called after STIC, so we know that we'll have to 112 * STI at the end 113 */ 114 while (s->vcpu_info[0].evtchn_upcall_pending) { 115 cli(); 116 s->vcpu_info[0].evtchn_upcall_pending = 0; 117 /* NB. No need for a barrier here -- XCHG is a barrier 118 * on x86. */ 119 #ifdef XEN3 120 l1 = xen_atomic_xchg(&s->vcpu_info[0].evtchn_pending_sel, 0); 121 #else 122 l1 = xen_atomic_xchg(&s->evtchn_pending_sel, 0); 123 #endif 124 while ((l1i = ffs(l1)) != 0) { 125 l1i--; 126 l1 &= ~(1 << l1i); 127 128 l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 129 /* 130 * mask and clear event. More efficient than calling 131 * hypervisor_mask/clear_event for each event. 132 */ 133 xen_atomic_setbits_l(&s->evtchn_mask[l1i], l2); 134 xen_atomic_clearbits_l(&s->evtchn_pending[l1i], l2); 135 while ((l2i = ffs(l2)) != 0) { 136 l2i--; 137 l2 &= ~(1 << l2i); 138 139 port = (l1i << 5) + l2i; 140 if (evtsource[port]) { 141 hypervisor_set_ipending( 142 evtsource[port]->ev_imask, 143 l1i, l2i); 144 evtsource[port]->ev_evcnt.ev_count++; 145 if (ret == 0 && ci->ci_ilevel < 146 evtsource[port]->ev_maxlevel) 147 ret = 1; 148 } 149 #ifdef DOM0OPS 150 else 151 xenevt_event(port); 152 #endif 153 } 154 } 155 sti(); 156 } 157 158 #if 0 159 if (ci->ci_ipending & 0x1) 160 printf("stipending events %08lx mask %08lx ilevel %d ipending %08x\n", 161 HYPERVISOR_shared_info->events, 162 HYPERVISOR_shared_info->events_mask, ci->ci_ilevel, 163 ci->ci_ipending); 164 #endif 165 166 return (ret); 167 } 168 169 void 170 do_hypervisor_callback(struct intrframe *regs) 171 { 172 uint32_t l1; 173 unsigned long l2; 174 unsigned int l1i, l2i, port; 175 volatile shared_info_t *s = HYPERVISOR_shared_info; 176 struct cpu_info *ci; 177 int level; 178 179 ci = curcpu(); 180 level = ci->ci_ilevel; 181 182 // DDD printf("do_hypervisor_callback\n"); 183 184 #ifdef EARLY_DEBUG_EVENT 185 if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) { 186 xen_debug_handler(NULL); 187 xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port); 188 } 189 #endif 190 191 while (s->vcpu_info[0].evtchn_upcall_pending) { 192 s->vcpu_info[0].evtchn_upcall_pending = 0; 193 /* NB. No need for a barrier here -- XCHG is a barrier 194 * on x86. */ 195 #ifdef XEN3 196 l1 = xen_atomic_xchg(&s->vcpu_info[0].evtchn_pending_sel, 0); 197 #else 198 l1 = xen_atomic_xchg(&s->evtchn_pending_sel, 0); 199 #endif 200 while ((l1i = ffs(l1)) != 0) { 201 l1i--; 202 l1 &= ~(1 << l1i); 203 204 l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 205 /* 206 * mask and clear the pending events. 207 * Doing it here for all event that will be processed 208 * avoids a race with stipending (which can be called 209 * though evtchn_do_event->splx) that could cause an event to 210 * be both processed and marked pending. 211 */ 212 xen_atomic_setbits_l(&s->evtchn_mask[l1i], l2); 213 xen_atomic_clearbits_l(&s->evtchn_pending[l1i], l2); 214 215 while ((l2i = ffs(l2)) != 0) { 216 l2i--; 217 l2 &= ~(1 << l2i); 218 219 port = (l1i << 5) + l2i; 220 #ifdef PORT_DEBUG 221 if (port == PORT_DEBUG) 222 printf("do_hypervisor_callback event %d\n", port); 223 #endif 224 if (evtsource[port]) 225 call_evtchn_do_event(port, regs); 226 #ifdef DOM0OPS 227 else 228 xenevt_event(port); 229 #endif 230 } 231 } 232 } 233 234 #ifdef DIAGNOSTIC 235 if (level != ci->ci_ilevel) 236 printf("hypervisor done %08x level %d/%d ipending %08x\n", 237 #ifdef XEN3 238 (uint)HYPERVISOR_shared_info->vcpu_info[0].evtchn_pending_sel, 239 #else 240 (uint)HYPERVISOR_shared_info->evtchn_pending_sel, 241 #endif 242 level, ci->ci_ilevel, ci->ci_ipending); 243 #endif 244 } 245 246 void 247 hypervisor_unmask_event(unsigned int ev) 248 { 249 volatile shared_info_t *s = HYPERVISOR_shared_info; 250 #ifdef PORT_DEBUG 251 if (ev == PORT_DEBUG) 252 printf("hypervisor_unmask_event %d\n", ev); 253 #endif 254 255 xen_atomic_clear_bit(&s->evtchn_mask[0], ev); 256 /* 257 * The following is basically the equivalent of 258 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose the 259 * interrupt edge' if the channel is masked. 260 */ 261 if (xen_atomic_test_bit(&s->evtchn_pending[0], ev) && 262 #ifdef XEN3 263 !xen_atomic_test_and_set_bit(&s->vcpu_info[0].evtchn_pending_sel, ev>>5)) { 264 #else 265 !xen_atomic_test_and_set_bit(&s->evtchn_pending_sel, ev>>5)) { 266 #endif 267 xen_atomic_set_bit(&s->vcpu_info[0].evtchn_upcall_pending, 0); 268 if (!s->vcpu_info[0].evtchn_upcall_mask) 269 hypervisor_force_callback(); 270 } 271 } 272 273 void 274 hypervisor_mask_event(unsigned int ev) 275 { 276 volatile shared_info_t *s = HYPERVISOR_shared_info; 277 #ifdef PORT_DEBUG 278 if (ev == PORT_DEBUG) 279 printf("hypervisor_mask_event %d\n", ev); 280 #endif 281 282 xen_atomic_set_bit(&s->evtchn_mask[0], ev); 283 } 284 285 void 286 hypervisor_clear_event(unsigned int ev) 287 { 288 volatile shared_info_t *s = HYPERVISOR_shared_info; 289 #ifdef PORT_DEBUG 290 if (ev == PORT_DEBUG) 291 printf("hypervisor_clear_event %d\n", ev); 292 #endif 293 294 xen_atomic_clear_bit(&s->evtchn_pending[0], ev); 295 } 296 297 void 298 hypervisor_enable_ipl(unsigned int ipl) 299 { 300 u_int32_t l1, l2; 301 int l1i, l2i; 302 struct cpu_info *ci = curcpu(); 303 304 /* 305 * enable all events for ipl. As we only set an event in ipl_evt_mask 306 * for its lowest IPL, and pending IPLs are processed high to low, 307 * we know that all callback for this event have been processed. 308 */ 309 310 l1 = ci->ci_isources[ipl]->ipl_evt_mask1; 311 ci->ci_isources[ipl]->ipl_evt_mask1 = 0; 312 while ((l1i = ffs(l1)) != 0) { 313 l1i--; 314 l1 &= ~(1 << l1i); 315 l2 = ci->ci_isources[ipl]->ipl_evt_mask2[l1i]; 316 ci->ci_isources[ipl]->ipl_evt_mask2[l1i] = 0; 317 while ((l2i = ffs(l2)) != 0) { 318 int evtch; 319 320 l2i--; 321 l2 &= ~(1 << l2i); 322 323 evtch = (l1i << 5) + l2i; 324 hypervisor_enable_event(evtch); 325 } 326 } 327 } 328 329 void 330 hypervisor_set_ipending(u_int32_t iplmask, int l1, int l2) 331 { 332 int ipl; 333 struct cpu_info *ci = curcpu(); 334 335 /* set pending bit for the appropriate IPLs */ 336 ci->ci_ipending |= iplmask; 337 338 /* 339 * And set event pending bit for the lowest IPL. As IPL are handled 340 * from high to low, this ensure that all callbacks will have been 341 * called when we ack the event 342 */ 343 ipl = ffs(iplmask); 344 KASSERT(ipl > 0); 345 ipl--; 346 ci->ci_isources[ipl]->ipl_evt_mask1 |= 1 << l1; 347 ci->ci_isources[ipl]->ipl_evt_mask2[l1] |= 1 << l2; 348 } 349 /* $NetBSD: hypervisor_machdep.c,v 1.2.4.2 2007/12/03 19:04:40 ad Exp $ */ 350 351 /* 352 * 353 * Copyright (c) 2004 Christian Limpach. 354 * All rights reserved. 355 * 356 * Redistribution and use in source and binary forms, with or without 357 * modification, are permitted provided that the following conditions 358 * are met: 359 * 1. Redistributions of source code must retain the above copyright 360 * notice, this list of conditions and the following disclaimer. 361 * 2. Redistributions in binary form must reproduce the above copyright 362 * notice, this list of conditions and the following disclaimer in the 363 * documentation and/or other materials provided with the distribution. 364 * 3. All advertising materials mentioning features or use of this software 365 * must display the following acknowledgement: 366 * This product includes software developed by Christian Limpach. 367 * 4. The name of the author may not be used to endorse or promote products 368 * derived from this software without specific prior written permission. 369 * 370 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 371 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 372 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 373 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 374 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 375 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 376 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 378 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 379 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 380 */ 381 382 /****************************************************************************** 383 * hypervisor.c 384 * 385 * Communication to/from hypervisor. 386 * 387 * Copyright (c) 2002-2004, K A Fraser 388 * 389 * Permission is hereby granted, free of charge, to any person obtaining a copy 390 * of this software and associated documentation files (the "Software"), to 391 * deal in the Software without restriction, including without limitation the 392 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 393 * sell copies of the Software, and to permit persons to whom the Software is 394 * furnished to do so, subject to the following conditions: 395 * 396 * The above copyright notice and this permission notice shall be included in 397 * all copies or substantial portions of the Software. 398 * 399 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 400 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 401 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 402 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 403 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 404 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 405 * DEALINGS IN THE SOFTWARE. 406 */ 407 408 409 #include <sys/cdefs.h> 410 __KERNEL_RCSID(0, "$NetBSD: hypervisor_machdep.c,v 1.2.4.2 2007/12/03 19:04:40 ad Exp $"); 411 412 #include <sys/param.h> 413 #include <sys/systm.h> 414 415 #include <xen/xen.h> 416 #include <xen/hypervisor.h> 417 #include <xen/evtchn.h> 418 #include <machine/atomic.h> 419 420 #include "opt_xen.h" 421 422 // #define PORT_DEBUG 4 423 // #define EARLY_DEBUG_EVENT 424 425 #ifdef EARLY_DEBUG_EVENT 426 extern int debug_port; 427 extern int xen_debug_handler(void *); 428 #endif 429 430 int stipending(void); 431 int 432 stipending() 433 { 434 uint32_t l1; 435 unsigned long l2; 436 unsigned int l1i, l2i, port; 437 volatile shared_info_t *s = HYPERVISOR_shared_info; 438 struct cpu_info *ci; 439 int ret; 440 441 ret = 0; 442 ci = curcpu(); 443 444 #if 0 445 if (HYPERVISOR_shared_info->events) 446 printf("stipending events %08lx mask %08lx ilevel %d\n", 447 HYPERVISOR_shared_info->events, 448 HYPERVISOR_shared_info->events_mask, ci->ci_ilevel); 449 #endif 450 451 #ifdef EARLY_DEBUG_EVENT 452 if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) { 453 xen_debug_handler(NULL); 454 xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port); 455 } 456 #endif 457 458 /* 459 * we're only called after STIC, so we know that we'll have to 460 * STI at the end 461 */ 462 while (s->vcpu_info[0].evtchn_upcall_pending) { 463 cli(); 464 s->vcpu_info[0].evtchn_upcall_pending = 0; 465 /* NB. No need for a barrier here -- XCHG is a barrier 466 * on x86. */ 467 #ifdef XEN3 468 l1 = xen_atomic_xchg(&s->vcpu_info[0].evtchn_pending_sel, 0); 469 #else 470 l1 = xen_atomic_xchg(&s->evtchn_pending_sel, 0); 471 #endif 472 while ((l1i = ffs(l1)) != 0) { 473 l1i--; 474 l1 &= ~(1 << l1i); 475 476 l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 477 /* 478 * mask and clear event. More efficient than calling 479 * hypervisor_mask/clear_event for each event. 480 */ 481 xen_atomic_setbits_l(&s->evtchn_mask[l1i], l2); 482 xen_atomic_clearbits_l(&s->evtchn_pending[l1i], l2); 483 while ((l2i = ffs(l2)) != 0) { 484 l2i--; 485 l2 &= ~(1 << l2i); 486 487 port = (l1i << 5) + l2i; 488 if (evtsource[port]) { 489 hypervisor_set_ipending( 490 evtsource[port]->ev_imask, 491 l1i, l2i); 492 evtsource[port]->ev_evcnt.ev_count++; 493 if (ret == 0 && ci->ci_ilevel < 494 evtsource[port]->ev_maxlevel) 495 ret = 1; 496 } 497 #ifdef DOM0OPS 498 else 499 xenevt_event(port); 500 #endif 501 } 502 } 503 sti(); 504 } 505 506 #if 0 507 if (ci->ci_ipending & 0x1) 508 printf("stipending events %08lx mask %08lx ilevel %d ipending %08x\n", 509 HYPERVISOR_shared_info->events, 510 HYPERVISOR_shared_info->events_mask, ci->ci_ilevel, 511 ci->ci_ipending); 512 #endif 513 514 return (ret); 515 } 516 517 void 518 do_hypervisor_callback(struct intrframe *regs) 519 { 520 uint32_t l1; 521 unsigned long l2; 522 unsigned int l1i, l2i, port; 523 volatile shared_info_t *s = HYPERVISOR_shared_info; 524 struct cpu_info *ci; 525 int level; 526 527 ci = curcpu(); 528 level = ci->ci_ilevel; 529 530 // DDD printf("do_hypervisor_callback\n"); 531 532 #ifdef EARLY_DEBUG_EVENT 533 if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) { 534 xen_debug_handler(NULL); 535 xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port); 536 } 537 #endif 538 539 while (s->vcpu_info[0].evtchn_upcall_pending) { 540 s->vcpu_info[0].evtchn_upcall_pending = 0; 541 /* NB. No need for a barrier here -- XCHG is a barrier 542 * on x86. */ 543 #ifdef XEN3 544 l1 = xen_atomic_xchg(&s->vcpu_info[0].evtchn_pending_sel, 0); 545 #else 546 l1 = xen_atomic_xchg(&s->evtchn_pending_sel, 0); 547 #endif 548 while ((l1i = ffs(l1)) != 0) { 549 l1i--; 550 l1 &= ~(1 << l1i); 551 552 l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 553 /* 554 * mask and clear the pending events. 555 * Doing it here for all event that will be processed 556 * avoids a race with stipending (which can be called 557 * though evtchn_do_event->splx) that could cause an event to 558 * be both processed and marked pending. 559 */ 560 xen_atomic_setbits_l(&s->evtchn_mask[l1i], l2); 561 xen_atomic_clearbits_l(&s->evtchn_pending[l1i], l2); 562 563 while ((l2i = ffs(l2)) != 0) { 564 l2i--; 565 l2 &= ~(1 << l2i); 566 567 port = (l1i << 5) + l2i; 568 #ifdef PORT_DEBUG 569 if (port == PORT_DEBUG) 570 printf("do_hypervisor_callback event %d\n", port); 571 #endif 572 if (evtsource[port]) 573 call_evtchn_do_event(port, regs); 574 #ifdef DOM0OPS 575 else 576 xenevt_event(port); 577 #endif 578 } 579 } 580 } 581 582 #ifdef DIAGNOSTIC 583 if (level != ci->ci_ilevel) 584 printf("hypervisor done %08x level %d/%d ipending %08x\n", 585 #ifdef XEN3 586 (uint)HYPERVISOR_shared_info->vcpu_info[0].evtchn_pending_sel, 587 #else 588 (uint)HYPERVISOR_shared_info->evtchn_pending_sel, 589 #endif 590 level, ci->ci_ilevel, ci->ci_ipending); 591 #endif 592 } 593 594 void 595 hypervisor_unmask_event(unsigned int ev) 596 { 597 volatile shared_info_t *s = HYPERVISOR_shared_info; 598 #ifdef PORT_DEBUG 599 if (ev == PORT_DEBUG) 600 printf("hypervisor_unmask_event %d\n", ev); 601 #endif 602 603 xen_atomic_clear_bit(&s->evtchn_mask[0], ev); 604 /* 605 * The following is basically the equivalent of 606 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose the 607 * interrupt edge' if the channel is masked. 608 */ 609 if (xen_atomic_test_bit(&s->evtchn_pending[0], ev) && 610 #ifdef XEN3 611 !xen_atomic_test_and_set_bit(&s->vcpu_info[0].evtchn_pending_sel, ev>>5)) { 612 #else 613 !xen_atomic_test_and_set_bit(&s->evtchn_pending_sel, ev>>5)) { 614 #endif 615 xen_atomic_set_bit(&s->vcpu_info[0].evtchn_upcall_pending, 0); 616 if (!s->vcpu_info[0].evtchn_upcall_mask) 617 hypervisor_force_callback(); 618 } 619 } 620 621 void 622 hypervisor_mask_event(unsigned int ev) 623 { 624 volatile shared_info_t *s = HYPERVISOR_shared_info; 625 #ifdef PORT_DEBUG 626 if (ev == PORT_DEBUG) 627 printf("hypervisor_mask_event %d\n", ev); 628 #endif 629 630 xen_atomic_set_bit(&s->evtchn_mask[0], ev); 631 } 632 633 void 634 hypervisor_clear_event(unsigned int ev) 635 { 636 volatile shared_info_t *s = HYPERVISOR_shared_info; 637 #ifdef PORT_DEBUG 638 if (ev == PORT_DEBUG) 639 printf("hypervisor_clear_event %d\n", ev); 640 #endif 641 642 xen_atomic_clear_bit(&s->evtchn_pending[0], ev); 643 } 644 645 void 646 hypervisor_enable_ipl(unsigned int ipl) 647 { 648 u_int32_t l1, l2; 649 int l1i, l2i; 650 struct cpu_info *ci = curcpu(); 651 652 /* 653 * enable all events for ipl. As we only set an event in ipl_evt_mask 654 * for its lowest IPL, and pending IPLs are processed high to low, 655 * we know that all callback for this event have been processed. 656 */ 657 658 l1 = ci->ci_isources[ipl]->ipl_evt_mask1; 659 ci->ci_isources[ipl]->ipl_evt_mask1 = 0; 660 while ((l1i = ffs(l1)) != 0) { 661 l1i--; 662 l1 &= ~(1 << l1i); 663 l2 = ci->ci_isources[ipl]->ipl_evt_mask2[l1i]; 664 ci->ci_isources[ipl]->ipl_evt_mask2[l1i] = 0; 665 while ((l2i = ffs(l2)) != 0) { 666 int evtch; 667 668 l2i--; 669 l2 &= ~(1 << l2i); 670 671 evtch = (l1i << 5) + l2i; 672 hypervisor_enable_event(evtch); 673 } 674 } 675 } 676 677 void 678 hypervisor_set_ipending(u_int32_t iplmask, int l1, int l2) 679 { 680 int ipl; 681 struct cpu_info *ci = curcpu(); 682 683 /* set pending bit for the appropriate IPLs */ 684 ci->ci_ipending |= iplmask; 685 686 /* 687 * And set event pending bit for the lowest IPL. As IPL are handled 688 * from high to low, this ensure that all callbacks will have been 689 * called when we ack the event 690 */ 691 ipl = ffs(iplmask); 692 KASSERT(ipl > 0); 693 ipl--; 694 ci->ci_isources[ipl]->ipl_evt_mask1 |= 1 << l1; 695 ci->ci_isources[ipl]->ipl_evt_mask2[l1] |= 1 << l2; 696 } 697
Indexes created Wed Oct 01 13:09:50 GMT 2025