x86_xpmap.c revision 1.1.2.4
1 /* $NetBSD: x86_xpmap.c,v 1.1.2.4 2007/11/19 19:50:40 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 3. All advertising materials mentioning features or use of this software 31 * must display the following acknowledgement: 32 * This product includes software developed by Manuel Bouyer. 33 * 4. The name of the author may not be used to endorse or promote products 34 * derived from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 38 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 39 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 41 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 45 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 * 47 */ 48 49 /* 50 * 51 * Copyright (c) 2004 Christian Limpach. 52 * All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Christian Limpach. 65 * 4. The name of the author may not be used to endorse or promote products 66 * derived from this software without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 69 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 70 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 71 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 72 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 73 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 74 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 75 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 76 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 77 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.1.2.4 2007/11/19 19:50:40 bouyer Exp $"); 83 84 #include "opt_xen.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 89 #include <uvm/uvm.h> 90 91 #include <machine/pmap.h> 92 #include <machine/gdt.h> 93 #include <xen/xenfunc.h> 94 95 #include <dev/isa/isareg.h> 96 #include <machine/isa_machdep.h> 97 98 #undef XENDEBUG 99 /* #define XENDEBUG_SYNC */ 100 /* #define XENDEBUG_LOW */ 101 102 #ifdef XENDEBUG 103 #define XENPRINTF(x) printf x 104 #define XENPRINTK(x) printk x 105 #define XENPRINTK2(x) /* printk x */ 106 107 static char XBUF[256]; 108 #else 109 #define XENPRINTF(x) 110 #define XENPRINTK(x) 111 #define XENPRINTK2(x) 112 #endif 113 #define PRINTF(x) printf x 114 #define PRINTK(x) printk x 115 116 volatile shared_info_t *HYPERVISOR_shared_info; 117 union start_info_union start_info_union; 118 119 void xen_failsafe_handler(void); 120 121 #ifdef XEN3 122 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 123 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 124 #else 125 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 126 HYPERVISOR_mmu_update((req), (count), (success_count)) 127 #endif 128 129 void 130 xen_failsafe_handler(void) 131 { 132 133 panic("xen_failsafe_handler called!\n"); 134 } 135 136 137 #ifndef __x86_64__ 138 void 139 xen_update_descriptor(union descriptor *table, union descriptor *entry) 140 { 141 paddr_t pa; 142 pt_entry_t *ptp; 143 144 ptp = kvtopte((vaddr_t)table); 145 pa = (*ptp & PG_FRAME) | ((vaddr_t)table & ~PG_FRAME); 146 if (HYPERVISOR_update_descriptor(pa, entry->raw[0], entry->raw[1])) 147 panic("HYPERVISOR_update_descriptor failed\n"); 148 } 149 #endif 150 151 void 152 xen_set_ldt(vaddr_t base, uint32_t entries) 153 { 154 vaddr_t va; 155 vaddr_t end; 156 pt_entry_t *ptp, *maptp; 157 int s; 158 159 #ifdef __x86_64__ 160 end = base + (entries << 3); 161 #else 162 end = base + entries * sizeof(union descriptor); 163 #endif 164 165 for (va = base; va < end; va += PAGE_SIZE) { 166 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 167 ptp = kvtopte(va); 168 maptp = (pt_entry_t *)vtomach((vaddr_t)ptp); 169 XENPRINTF(("xen_set_ldt %p %d %p %p\n", (void *)base, 170 entries, ptp, maptp)); 171 PTE_CLEARBITS(ptp, maptp, PG_RW); 172 } 173 s = splvm(); 174 PTE_UPDATES_FLUSH(); 175 176 xpq_queue_set_ldt(base, entries); 177 xpq_flush_queue(); 178 splx(s); 179 } 180 181 #ifdef XENDEBUG 182 void xpq_debug_dump(void); 183 #endif 184 185 #define XPQUEUE_SIZE 2048 186 static mmu_update_t xpq_queue[XPQUEUE_SIZE]; 187 static int xpq_idx = 0; 188 189 void 190 xpq_flush_queue() 191 { 192 int i, ok; 193 194 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 195 for (i = 0; i < xpq_idx; i++) 196 XENPRINTK2(("%d: %p %08x\n", i, (u_int)xpq_queue[i].ptr, 197 (u_int)xpq_queue[i].val)); 198 if (xpq_idx != 0 && 199 HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok) < 0) 200 panic("HYPERVISOR_mmu_update failed\n"); 201 xpq_idx = 0; 202 } 203 204 static inline void 205 xpq_increment_idx(void) 206 { 207 208 xpq_idx++; 209 if (__predict_false(xpq_idx == XPQUEUE_SIZE)) 210 xpq_flush_queue(); 211 } 212 213 void 214 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 215 { 216 XENPRINTK2(("xpq_queue_machphys_update ma=%p pa=%p\n", (void *)ma, (void *)pa)); 217 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 218 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 219 xpq_increment_idx(); 220 #ifdef XENDEBUG_SYNC 221 xpq_flush_queue(); 222 #endif 223 } 224 225 void 226 xpq_queue_pde_update(pd_entry_t *ptr, pd_entry_t val) 227 { 228 229 KASSERT(((paddr_t)ptr & 3) == 0); 230 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 231 xpq_queue[xpq_idx].val = val; 232 xpq_increment_idx(); 233 #ifdef XENDEBUG_SYNC 234 xpq_flush_queue(); 235 #endif 236 } 237 238 void 239 xpq_queue_pte_update(pt_entry_t *ptr, pt_entry_t val) 240 { 241 242 KASSERT(((paddr_t)ptr & 3) == 0); 243 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 244 xpq_queue[xpq_idx].val = val; 245 xpq_increment_idx(); 246 #ifdef XENDEBUG_SYNC 247 xpq_flush_queue(); 248 #endif 249 } 250 251 #ifdef XEN3 252 void 253 xpq_queue_pt_switch(paddr_t pa) 254 { 255 struct mmuext_op op; 256 xpq_flush_queue(); 257 258 XENPRINTK2(("xpq_queue_pt_switch: %p %p\n", (void *)pa, (void *)pa)); 259 op.cmd = MMUEXT_NEW_BASEPTR; 260 op.arg1.mfn = pa >> PAGE_SHIFT; 261 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 262 panic("xpq_queue_pt_switch"); 263 } 264 265 void 266 xpq_queue_pin_table(paddr_t pa) 267 { 268 struct mmuext_op op; 269 xpq_flush_queue(); 270 271 XENPRINTK2(("xpq_queue_pin_table: %p %p\n", (void *)pa, (void *)pa)); 272 op.arg1.mfn = pa >> PAGE_SHIFT; 273 274 #ifdef __x86_64__ 275 op.cmd = MMUEXT_PIN_L4_TABLE; 276 #else 277 op.cmd = MMUEXT_PIN_L2_TABLE; 278 #endif 279 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 280 panic("xpq_queue_pin_table"); 281 } 282 283 void 284 xpq_queue_unpin_table(paddr_t pa) 285 { 286 struct mmuext_op op; 287 xpq_flush_queue(); 288 289 XENPRINTK2(("xpq_queue_unpin_table: %p %p\n", (void *)pa, (void *)pa)); 290 op.arg1.mfn = pa >> PAGE_SHIFT; 291 op.cmd = MMUEXT_UNPIN_TABLE; 292 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 293 panic("xpq_queue_unpin_table"); 294 } 295 296 void 297 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 298 { 299 struct mmuext_op op; 300 xpq_flush_queue(); 301 302 XENPRINTK2(("xpq_queue_set_ldt\n")); 303 KASSERT(va == (va & ~PAGE_MASK)); 304 op.cmd = MMUEXT_SET_LDT; 305 op.arg1.linear_addr = va; 306 op.arg2.nr_ents = entries; 307 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 308 panic("xpq_queue_set_ldt"); 309 } 310 311 void 312 xpq_queue_tlb_flush() 313 { 314 struct mmuext_op op; 315 xpq_flush_queue(); 316 317 XENPRINTK2(("xpq_queue_tlb_flush\n")); 318 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 319 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 320 panic("xpq_queue_tlb_flush"); 321 } 322 323 void 324 xpq_flush_cache() 325 { 326 struct mmuext_op op; 327 int s = splvm(); 328 xpq_flush_queue(); 329 330 XENPRINTK2(("xpq_queue_flush_cache\n")); 331 op.cmd = MMUEXT_FLUSH_CACHE; 332 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 333 panic("xpq_flush_cache"); 334 splx(s); 335 } 336 337 void 338 xpq_queue_invlpg(vaddr_t va) 339 { 340 struct mmuext_op op; 341 xpq_flush_queue(); 342 343 XENPRINTK2(("xpq_queue_invlpg %p\n", (void *)va)); 344 op.cmd = MMUEXT_INVLPG_LOCAL; 345 op.arg1.linear_addr = (va & ~PAGE_MASK); 346 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 347 panic("xpq_queue_invlpg"); 348 } 349 350 int 351 xpq_update_foreign(pt_entry_t *ptr, pt_entry_t val, int dom) 352 { 353 mmu_update_t op; 354 int ok; 355 xpq_flush_queue(); 356 357 op.ptr = (paddr_t)ptr; 358 op.val = val; 359 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 360 return EFAULT; 361 return (0); 362 } 363 #else /* XEN3 */ 364 void 365 xpq_queue_pt_switch(paddr_t pa) 366 { 367 368 XENPRINTK2(("xpq_queue_pt_switch: %p %p\n", (void *)pa, (void *)pa)); 369 xpq_queue[xpq_idx].ptr = pa | MMU_EXTENDED_COMMAND; 370 xpq_queue[xpq_idx].val = MMUEXT_NEW_BASEPTR; 371 xpq_increment_idx(); 372 } 373 374 void 375 xpq_queue_pin_table(paddr_t pa) 376 { 377 378 XENPRINTK2(("xpq_queue_pin_table: %p %p\n", (void *)pa, (void *)pa)); 379 xpq_queue[xpq_idx].ptr = pa | MMU_EXTENDED_COMMAND; 380 xpq_queue[xpq_idx].val = MMUEXT_PIN_L2_TABLE; 381 xpq_increment_idx(); 382 } 383 384 void 385 xpq_queue_unpin_table(paddr_t pa) 386 { 387 388 XENPRINTK2(("xpq_queue_unpin_table: %p %p\n", (void *)pa, (void *)pa)); 389 xpq_queue[xpq_idx].ptr = pa | MMU_EXTENDED_COMMAND; 390 xpq_queue[xpq_idx].val = MMUEXT_UNPIN_TABLE; 391 xpq_increment_idx(); 392 } 393 394 void 395 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 396 { 397 398 XENPRINTK2(("xpq_queue_set_ldt\n")); 399 KASSERT(va == (va & ~PAGE_MASK)); 400 xpq_queue[xpq_idx].ptr = MMU_EXTENDED_COMMAND | va; 401 xpq_queue[xpq_idx].val = MMUEXT_SET_LDT | (entries << MMUEXT_CMD_SHIFT); 402 xpq_increment_idx(); 403 } 404 405 void 406 xpq_queue_tlb_flush() 407 { 408 409 XENPRINTK2(("xpq_queue_tlb_flush\n")); 410 xpq_queue[xpq_idx].ptr = MMU_EXTENDED_COMMAND; 411 xpq_queue[xpq_idx].val = MMUEXT_TLB_FLUSH; 412 xpq_increment_idx(); 413 } 414 415 void 416 xpq_flush_cache() 417 { 418 int s = splvm(); 419 420 XENPRINTK2(("xpq_queue_flush_cache\n")); 421 xpq_queue[xpq_idx].ptr = MMU_EXTENDED_COMMAND; 422 xpq_queue[xpq_idx].val = MMUEXT_FLUSH_CACHE; 423 xpq_increment_idx(); 424 xpq_flush_queue(); 425 splx(s); 426 } 427 428 void 429 xpq_queue_invlpg(vaddr_t va) 430 { 431 432 XENPRINTK2(("xpq_queue_invlpg %p\n", (void *)va)); 433 xpq_queue[xpq_idx].ptr = (va & ~PAGE_MASK) | MMU_EXTENDED_COMMAND; 434 xpq_queue[xpq_idx].val = MMUEXT_INVLPG; 435 xpq_increment_idx(); 436 } 437 438 int 439 xpq_update_foreign(pt_entry_t *ptr, pt_entry_t val, int dom) 440 { 441 mmu_update_t xpq_up[3]; 442 443 xpq_up[0].ptr = MMU_EXTENDED_COMMAND; 444 xpq_up[0].val = MMUEXT_SET_FOREIGNDOM | (dom << 16); 445 xpq_up[1].ptr = (paddr_t)ptr; 446 xpq_up[1].val = val; 447 if (HYPERVISOR_mmu_update_self(xpq_up, 2, NULL) < 0) 448 return EFAULT; 449 return (0); 450 } 451 #endif /* XEN3 */ 452 453 #ifdef XENDEBUG 454 void 455 xpq_debug_dump() 456 { 457 int i; 458 459 XENPRINTK2(("idx: %d\n", xpq_idx)); 460 for (i = 0; i < xpq_idx; i++) { 461 sprintf(XBUF, "%x %08x ", (u_int)xpq_queue[i].ptr, 462 (u_int)xpq_queue[i].val); 463 if (++i < xpq_idx) 464 sprintf(XBUF + strlen(XBUF), "%x %08x ", 465 (u_int)xpq_queue[i].ptr, (u_int)xpq_queue[i].val); 466 if (++i < xpq_idx) 467 sprintf(XBUF + strlen(XBUF), "%x %08x ", 468 (u_int)xpq_queue[i].ptr, (u_int)xpq_queue[i].val); 469 if (++i < xpq_idx) 470 sprintf(XBUF + strlen(XBUF), "%x %08x ", 471 (u_int)xpq_queue[i].ptr, (u_int)xpq_queue[i].val); 472 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 473 } 474 } 475 #endif 476 477 478 #ifdef __x86_64__ 479 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 480 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 481 482 static void xen_bt_set_readonly (vaddr_t); 483 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 484 485 /* How many PDEs ? */ 486 #if L2_SLOT_KERNBASE > 0 487 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 488 #else 489 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 490 #endif 491 492 /* 493 * Construct and switch to new pagetables 494 * first_avail is the first vaddr we can use after 495 * we get rid of Xen pagetables 496 */ 497 498 vaddr_t xen_pmap_bootstrap (void); 499 500 /* 501 * Function to get rid of Xen bootstrap tables 502 */ 503 504 vaddr_t 505 xen_pmap_bootstrap() 506 { 507 int count, iocount = 0; 508 vaddr_t bootstrap_tables, init_tables; 509 510 xpmap_phys_to_machine_mapping = (paddr_t *) xen_start_info.mfn_list; 511 init_tables = xen_start_info.pt_base; 512 printk("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables); 513 514 /* Space after Xen boostrap tables should be free */ 515 bootstrap_tables = xen_start_info.pt_base + 516 (xen_start_info.nr_pt_frames * PAGE_SIZE); 517 518 /* Calculate how many tables we need */ 519 count = TABLE_L2_ENTRIES; 520 521 #ifdef DOM0OPS 522 if (xen_start_info.flags & SIF_INITDOMAIN) { 523 /* space for ISA I/O mem */ 524 iocount = IOM_SIZE / PAGE_SIZE; 525 } 526 #endif 527 528 /* 529 * Xen space we'll reclaim may not be enough for our new page tables, 530 * move bootstrap tables if necessary 531 */ 532 533 if (bootstrap_tables < init_tables + ((count+3+iocount) * PAGE_SIZE)) 534 bootstrap_tables = init_tables + 535 ((count+3+iocount) * PAGE_SIZE); 536 537 /* Create temporary tables */ 538 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 539 xen_start_info.nr_pt_frames, count, 0); 540 541 /* get vaddr space for the shared info and the console pages */ 542 543 /* Create final tables */ 544 xen_bootstrap_tables(bootstrap_tables, init_tables, 545 count + 3, count, 1); 546 547 return (init_tables + ((count + 3) * PAGE_SIZE)); 548 } 549 550 551 /* 552 * Build a new table and switch to it 553 * old_count is # of old tables (including PGD, PDTPE and PDE) 554 * new_count is # of new tables (PTE only) 555 * we assume areas don't overlap 556 */ 557 558 559 static void 560 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 561 int old_count, int new_count, int final) 562 { 563 pd_entry_t *pdtpe, *pde, *pte; 564 pd_entry_t *cur_pgd, *bt_pgd; 565 paddr_t addr, page; 566 vaddr_t avail, text_end, map_end; 567 int i; 568 extern char __data_start; 569 570 printk("xen_bootstrap_tables(0x%lx, 0x%lx, %d, %d)\n", 571 old_pgd, new_pgd, old_count, new_count); 572 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 573 /* 574 * size of R/W area after kernel text: 575 * xencons_interface (if present) 576 * xenstore_interface (if present) 577 * table pages (new_count + 3 entries) 578 * UAREA 579 * dummy user PGD 580 * extra mappings (only when final is true): 581 * HYPERVISOR_shared_info 582 * ISA I/O mem (if needed) 583 */ 584 map_end = new_pgd + ((new_count + 3 + UPAGES + 1) * NBPG); 585 if (final) { 586 HYPERVISOR_shared_info = (struct shared_info *)map_end; 587 map_end += NBPG; 588 } 589 #ifdef DOM0OPS 590 if (final && (xen_start_info.flags & SIF_INITDOMAIN)) { 591 /* ISA I/O mem */ 592 atdevbase = map_end; 593 map_end += IOM_SIZE; 594 } 595 #endif /* DOM0OPS */ 596 597 printk("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", text_end, 598 map_end); 599 600 /* 601 * Create bootstrap page tables 602 * What we need: 603 * - a PGD (level 4) 604 * - a PDTPE (level 3) 605 * - a PDE (level2) 606 * - some PTEs (level 1) 607 */ 608 609 cur_pgd = (pd_entry_t *) old_pgd; 610 bt_pgd = (pd_entry_t *) new_pgd; 611 memset (bt_pgd, 0, PAGE_SIZE); 612 avail = new_pgd + PAGE_SIZE; 613 614 /* Install level 3 */ 615 pdtpe = (pd_entry_t *) avail; 616 memset (pdtpe, 0, PAGE_SIZE); 617 avail += PAGE_SIZE; 618 619 addr = ((paddr_t) pdtpe) - KERNBASE; 620 bt_pgd[pl4_pi(KERNTEXTOFF)] = 621 xpmap_ptom_masked(addr) | PG_u | PG_RW | PG_V; 622 623 printk("L3 va 0x%lx pa 0x%lx entry 0x%lx -> L4[0x%x]\n", pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF)); 624 625 /* Level 2 */ 626 pde = (pd_entry_t *) avail; 627 memset(pde, 0, PAGE_SIZE); 628 avail += PAGE_SIZE; 629 630 addr = ((paddr_t) pde) - KERNBASE; 631 pdtpe[pl3_pi(KERNTEXTOFF)] = 632 xpmap_ptom_masked(addr) | PG_u | PG_RW | PG_V; 633 printk("L2 va 0x%lx pa 0x%lx entry 0x%lx -> L3[0x%x]\n", pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF)); 634 635 /* Level 1 */ 636 page = KERNTEXTOFF; 637 for (i = 0; i < new_count; i ++) { 638 paddr_t cur_page = page; 639 640 pte = (pd_entry_t *) avail; 641 avail += PAGE_SIZE; 642 643 memset(pte, 0, PAGE_SIZE); 644 while (pl2_pi(page) == pl2_pi (cur_page)) { 645 if (page >= map_end) { 646 /* not mapped at all */ 647 pte[pl1_pi(page)] = 0; 648 page += PAGE_SIZE; 649 continue; 650 } 651 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 652 if (page == (vaddr_t)HYPERVISOR_shared_info) { 653 pte[pl1_pi(page)] = xen_start_info.shared_info; 654 printk("HYPERVISOR_shared_info va 0x%lx pte 0x%lx\n", HYPERVISOR_shared_info, pte[pl1_pi(page)]); 655 } 656 if (xpmap_ptom_masked(page - KERNBASE) == 657 (xen_start_info.console_mfn << PAGE_SHIFT)) { 658 xencons_interface = (void *)page; 659 pte[pl1_pi(page)] = 660 (xen_start_info.console_mfn << PAGE_SHIFT); 661 printk("xencons_interface va 0x%lx pte 0x%lx\n", xencons_interface, pte[pl1_pi(page)]); 662 } 663 if (xpmap_ptom_masked(page - KERNBASE) == 664 (xen_start_info.store_mfn << PAGE_SHIFT)) { 665 xenstore_interface = (void *)page; 666 pte[pl1_pi(page)] = 667 (xen_start_info.store_mfn << PAGE_SHIFT); 668 printk("xenstore_interface va 0x%lx pte 0x%lx\n", xenstore_interface, pte[pl1_pi(page)]); 669 } 670 #ifdef DOM0OPS 671 if (page >= (vaddr_t)atdevbase && 672 page < (vaddr_t)atdevbase + IOM_SIZE) { 673 pte[pl1_pi(page)] = 674 IOM_BEGIN + (page - (vaddr_t)atdevbase); 675 } 676 #endif 677 pte[pl1_pi(page)] |= PG_u | PG_V; 678 if (page < text_end) { 679 /* map kernel text RO */ 680 pte[pl1_pi(page)] |= 0; 681 } else if (page >= old_pgd 682 && page < old_pgd + (old_count * PAGE_SIZE)) { 683 /* map old page tables RO */ 684 pte[pl1_pi(page)] |= 0; 685 } else if (page >= new_pgd && 686 page < new_pgd + ((new_count + 3) * PAGE_SIZE)) { 687 /* map new page tables RO */ 688 pte[pl1_pi(page)] |= 0; 689 } else { 690 /* map page RW */ 691 pte[pl1_pi(page)] |= PG_RW; 692 } 693 if (page == old_pgd) 694 printk("va 0x%lx pa 0x%lx entry 0x%lx -> L1[0x%x]\n", page, page - KERNBASE, pte[pl1_pi(page)], pl1_pi(page)); 695 page += PAGE_SIZE; 696 } 697 698 addr = ((paddr_t) pte) - KERNBASE; 699 pde[pl2_pi(cur_page)] = 700 xpmap_ptom_masked(addr) | PG_u | PG_RW | PG_V; 701 printk("L1 va 0x%lx pa 0x%lx entry 0x%lx -> L2[0x%x]\n", pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page)); 702 /* Mark readonly */ 703 xen_bt_set_readonly((vaddr_t) pte); 704 } 705 706 /* Install recursive page tables mapping */ 707 bt_pgd[PDIR_SLOT_PTE] = 708 xpmap_ptom_masked(new_pgd - KERNBASE) | PG_u | PG_V; 709 printk("bt_pgd[PDIR_SLOT_PTE] va 0x%lx pa 0x%lx entry 0x%lx\n", new_pgd, new_pgd - KERNBASE, bt_pgd[PDIR_SLOT_PTE]); 710 711 /* Mark tables RO */ 712 xen_bt_set_readonly((vaddr_t) pde); 713 xen_bt_set_readonly((vaddr_t) pdtpe); 714 xen_bt_set_readonly(new_pgd); 715 /* Pin the PGD */ 716 printk("pin PDG\n"); 717 xpq_queue_pin_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 718 /* Switch to new tables */ 719 printk("switch to PDG\n"); 720 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 721 printk("bt_pgd[PDIR_SLOT_PTE] now entry 0x%lx\n",bt_pgd[PDIR_SLOT_PTE]); 722 printk("L4_BASE va 0x%lx\n", (long)L4_BASE); 723 printk("value 0x%lx\n", *L4_BASE); 724 printk("[PDIR_SLOT_PTE] 0x%lx\n", L4_BASE[PDIR_SLOT_PTE]); 725 726 /* Now we can safely reclaim space taken by old tables */ 727 728 printk("unpin old PDG\n"); 729 /* Unpin old PGD */ 730 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 731 /* Mark old tables RW */ 732 page = old_pgd; 733 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 734 addr = xpmap_mtop(addr); 735 pte = (pd_entry_t *) (addr + KERNBASE); 736 pte += pl1_pi(page); 737 printk("*pde 0x%lx addr 0x%lx pte 0x%lx\n", pde[pl2_pi(page)], addr, pte); 738 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 739 addr = xpmap_ptom(((paddr_t) pte) - KERNBASE); 740 xpq_queue_pte_update((pt_entry_t *) addr, *pte | PG_RW); 741 page += PAGE_SIZE; 742 /* 743 * Our ptes are contiguous 744 * so it's safe to just "++" here 745 */ 746 pte++; 747 } 748 xpq_flush_queue(); 749 } 750 751 752 void 753 xen_set_user_pgd(paddr_t page) 754 { 755 struct mmuext_op op; 756 int s = splvm(); 757 758 xpq_flush_queue(); 759 op.cmd = MMUEXT_NEW_USER_BASEPTR; 760 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 761 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 762 panic("xen_set_user_pgd: failed to install new user page" 763 " directory %lx", page); 764 splx(s); 765 } 766 767 /* 768 * Bootstrap helper functions 769 */ 770 771 /* 772 * Mark a page readonly 773 * XXX: assuming vaddr = paddr + KERNBASE 774 */ 775 776 static void 777 xen_bt_set_readonly (vaddr_t page) 778 { 779 pt_entry_t entry; 780 781 entry = xpmap_ptom_masked(page - KERNBASE); 782 entry |= PG_u | PG_V; 783 784 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 785 } 786 #endif /* x86_64 */ 787
Indexes created Tue Oct 28 12:10:06 GMT 2025