x86_xpmap.c revision 1.12.4.10
1 /* $NetBSD: x86_xpmap.c,v 1.12.4.10 2011/03/28 23:04:56 jym Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.12.4.10 2011/03/28 23:04:56 jym Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 81 #include <uvm/uvm.h> 82 83 #include <machine/pmap.h> 84 #include <machine/gdt.h> 85 #include <xen/xenfunc.h> 86 87 #include <dev/isa/isareg.h> 88 #include <machine/isa_machdep.h> 89 90 #define XENDEBUG 91 /* #define XENDEBUG_SYNC */ 92 /* #define XENDEBUG_LOW */ 93 94 #ifdef XENDEBUG 95 #define XENPRINTF(x) printf x 96 #define XENPRINTK(x) printk x 97 #define XENPRINTK2(x) /* printk x */ 98 99 static char XBUF[256]; 100 #else 101 #define XENPRINTF(x) 102 #define XENPRINTK(x) 103 #define XENPRINTK2(x) 104 #endif 105 #define PRINTF(x) printf x 106 #define PRINTK(x) printk x 107 108 /* on x86_64 kernel runs in ring 3 */ 109 #ifdef __x86_64__ 110 #define PG_k PG_u 111 #else 112 #define PG_k 0 113 #endif 114 115 volatile shared_info_t *HYPERVISOR_shared_info; 116 /* Xen requires the start_info struct to be page aligned */ 117 union start_info_union start_info_union __aligned(PAGE_SIZE); 118 unsigned long *xpmap_phys_to_machine_mapping; 119 120 void xen_failsafe_handler(void); 121 122 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 123 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 124 125 void 126 xen_failsafe_handler(void) 127 { 128 129 panic("xen_failsafe_handler called!\n"); 130 } 131 132 133 void 134 xen_set_ldt(vaddr_t base, uint32_t entries) 135 { 136 vaddr_t va; 137 vaddr_t end; 138 pt_entry_t *ptp; 139 int s; 140 141 #ifdef __x86_64__ 142 end = base + (entries << 3); 143 #else 144 end = base + entries * sizeof(union descriptor); 145 #endif 146 147 for (va = base; va < end; va += PAGE_SIZE) { 148 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 149 ptp = kvtopte(va); 150 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 151 base, entries, ptp)); 152 pmap_pte_clearbits(ptp, PG_RW); 153 } 154 s = splvm(); 155 xpq_queue_set_ldt(base, entries); 156 splx(s); 157 } 158 159 #ifdef XENDEBUG 160 void xpq_debug_dump(void); 161 #endif 162 163 #define XPQUEUE_SIZE 2048 164 static mmu_update_t xpq_queue[XPQUEUE_SIZE]; 165 static int xpq_idx = 0; 166 167 void 168 xpq_flush_queue(void) 169 { 170 int i, ok, ret; 171 172 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 173 for (i = 0; i < xpq_idx; i++) 174 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 175 xpq_queue[i].ptr, xpq_queue[i].val)); 176 177 ret = HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok); 178 179 if (xpq_idx != 0 && ret < 0) { 180 printf("xpq_flush_queue: %d entries (%d successful)\n", 181 xpq_idx, ok); 182 for (i = 0; i < xpq_idx; i++) 183 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 184 xpq_queue[i].ptr, xpq_queue[i].val); 185 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 186 } 187 xpq_idx = 0; 188 } 189 190 static inline void 191 xpq_increment_idx(void) 192 { 193 194 xpq_idx++; 195 if (__predict_false(xpq_idx == XPQUEUE_SIZE)) 196 xpq_flush_queue(); 197 } 198 199 void 200 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 201 { 202 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 203 "\n", (int64_t)ma, (int64_t)pa)); 204 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 205 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 206 xpq_increment_idx(); 207 #ifdef XENDEBUG_SYNC 208 xpq_flush_queue(); 209 #endif 210 } 211 212 void 213 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 214 { 215 216 KASSERT((ptr & 3) == 0); 217 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 218 xpq_queue[xpq_idx].val = val; 219 xpq_increment_idx(); 220 #ifdef XENDEBUG_SYNC 221 xpq_flush_queue(); 222 #endif 223 } 224 225 void 226 xpq_queue_pt_switch(paddr_t pa) 227 { 228 struct mmuext_op op; 229 xpq_flush_queue(); 230 231 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 232 (int64_t)pa, (int64_t)pa)); 233 op.cmd = MMUEXT_NEW_BASEPTR; 234 op.arg1.mfn = pa >> PAGE_SHIFT; 235 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 236 panic("xpq_queue_pt_switch"); 237 } 238 239 void 240 xpq_queue_pin_table(paddr_t pa, int lvl) 241 { 242 struct mmuext_op op; 243 xpq_flush_queue(); 244 245 XENPRINTK2(("xpq_queue_pin_l%d_table: %#" PRIxPADDR "\n", 246 lvl + 1, pa)); 247 248 op.arg1.mfn = pa >> PAGE_SHIFT; 249 op.cmd = lvl; 250 251 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 252 panic("xpq_queue_pin_table: level %u %#"PRIx64"\n", 253 level, (int64_t)pa); 254 } 255 256 void 257 xpq_queue_unpin_table(paddr_t pa) 258 { 259 struct mmuext_op op; 260 xpq_flush_queue(); 261 262 XENPRINTK2(("xpq_queue_unpin_table: %#" PRIxPADDR "\n", pa)); 263 op.arg1.mfn = pa >> PAGE_SHIFT; 264 op.cmd = MMUEXT_UNPIN_TABLE; 265 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 266 panic("xpq_queue_unpin_table"); 267 } 268 269 void 270 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 271 { 272 struct mmuext_op op; 273 xpq_flush_queue(); 274 275 XENPRINTK2(("xpq_queue_set_ldt\n")); 276 KASSERT(va == (va & ~PAGE_MASK)); 277 op.cmd = MMUEXT_SET_LDT; 278 op.arg1.linear_addr = va; 279 op.arg2.nr_ents = entries; 280 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 281 panic("xpq_queue_set_ldt"); 282 } 283 284 void 285 xpq_queue_tlb_flush(void) 286 { 287 struct mmuext_op op; 288 xpq_flush_queue(); 289 290 XENPRINTK2(("xpq_queue_tlb_flush\n")); 291 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 292 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 293 panic("xpq_queue_tlb_flush"); 294 } 295 296 void 297 xpq_flush_cache(void) 298 { 299 struct mmuext_op op; 300 int s = splvm(); 301 xpq_flush_queue(); 302 303 XENPRINTK2(("xpq_queue_flush_cache\n")); 304 op.cmd = MMUEXT_FLUSH_CACHE; 305 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 306 panic("xpq_flush_cache"); 307 splx(s); 308 } 309 310 void 311 xpq_queue_invlpg(vaddr_t va) 312 { 313 struct mmuext_op op; 314 xpq_flush_queue(); 315 316 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 317 op.cmd = MMUEXT_INVLPG_LOCAL; 318 op.arg1.linear_addr = (va & ~PAGE_MASK); 319 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 320 panic("xpq_queue_invlpg"); 321 } 322 323 int 324 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 325 { 326 mmu_update_t op; 327 int ok; 328 xpq_flush_queue(); 329 330 op.ptr = ptr; 331 op.val = val; 332 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 333 return EFAULT; 334 return (0); 335 } 336 337 #ifdef XENDEBUG 338 void 339 xpq_debug_dump(void) 340 { 341 int i; 342 343 XENPRINTK2(("idx: %d\n", xpq_idx)); 344 for (i = 0; i < xpq_idx; i++) { 345 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 346 xpq_queue[i].ptr, xpq_queue[i].val); 347 if (++i < xpq_idx) 348 snprintf(XBUF + strlen(XBUF), 349 sizeof(XBUF) - strlen(XBUF), 350 "%" PRIx64 " %08" PRIx64, 351 xpq_queue[i].ptr, xpq_queue[i].val); 352 if (++i < xpq_idx) 353 snprintf(XBUF + strlen(XBUF), 354 sizeof(XBUF) - strlen(XBUF), 355 "%" PRIx64 " %08" PRIx64, 356 xpq_queue[i].ptr, xpq_queue[i].val); 357 if (++i < xpq_idx) 358 snprintf(XBUF + strlen(XBUF), 359 sizeof(XBUF) - strlen(XBUF), 360 "%" PRIx64 " %08" PRIx64, 361 xpq_queue[i].ptr, xpq_queue[i].val); 362 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 363 } 364 } 365 #endif 366 367 368 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 369 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 370 371 static void xen_bt_set_readonly (vaddr_t); 372 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 373 374 /* How many PDEs ? */ 375 #if L2_SLOT_KERNBASE > 0 376 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 377 #else 378 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 379 #endif 380 381 /* 382 * Construct and switch to new pagetables 383 * first_avail is the first vaddr we can use after 384 * we get rid of Xen pagetables 385 */ 386 387 vaddr_t xen_pmap_bootstrap (void); 388 389 /* 390 * Function to get rid of Xen bootstrap tables 391 */ 392 393 /* How many PDP do we need: */ 394 #ifdef PAE 395 /* 396 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 397 * all of them mapped by the L3 page. We also need a shadow page 398 * for L3[3]. 399 */ 400 static const int l2_4_count = 6; 401 #else 402 static const int l2_4_count = PTP_LEVELS - 1; 403 #endif 404 405 vaddr_t 406 xen_pmap_bootstrap(void) 407 { 408 int count, oldcount; 409 long mapsize; 410 vaddr_t bootstrap_tables, init_tables; 411 412 xpmap_phys_to_machine_mapping = 413 (unsigned long *)xen_start_info.mfn_list; 414 init_tables = xen_start_info.pt_base; 415 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 416 417 /* Space after Xen boostrap tables should be free */ 418 bootstrap_tables = xen_start_info.pt_base + 419 (xen_start_info.nr_pt_frames * PAGE_SIZE); 420 421 /* 422 * Calculate how many space we need 423 * first everything mapped before the Xen bootstrap tables 424 */ 425 mapsize = init_tables - KERNTEXTOFF; 426 /* after the tables we'll have: 427 * - UAREA 428 * - dummy user PGD (x86_64) 429 * - HYPERVISOR_shared_info 430 * - ISA I/O mem (if needed) 431 */ 432 mapsize += UPAGES * NBPG; 433 #ifdef __x86_64__ 434 mapsize += NBPG; 435 #endif 436 mapsize += NBPG; 437 438 #ifdef DOM0OPS 439 if (xendomain_is_dom0()) { 440 /* space for ISA I/O mem */ 441 mapsize += IOM_SIZE; 442 } 443 #endif 444 /* at this point mapsize doens't include the table size */ 445 446 #ifdef __x86_64__ 447 count = TABLE_L2_ENTRIES; 448 #else 449 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 450 #endif /* __x86_64__ */ 451 452 /* now compute how many L2 pages we need exactly */ 453 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 454 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 455 ((long)count << L2_SHIFT) + KERNBASE) { 456 count++; 457 } 458 #ifndef __x86_64__ 459 /* 460 * one more L2 page: we'll alocate several pages after kva_start 461 * in pmap_bootstrap() before pmap_growkernel(), which have not been 462 * counted here. It's not a big issue to allocate one more L2 as 463 * pmap_growkernel() will be called anyway. 464 */ 465 count++; 466 nkptp[1] = count; 467 #endif 468 469 /* 470 * install bootstrap pages. We may need more L2 pages than will 471 * have the final table here, as it's installed after the final table 472 */ 473 oldcount = count; 474 475 bootstrap_again: 476 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 477 /* 478 * Xen space we'll reclaim may not be enough for our new page tables, 479 * move bootstrap tables if necessary 480 */ 481 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 482 bootstrap_tables = init_tables + 483 ((count + l2_4_count) * PAGE_SIZE); 484 /* make sure we have enough to map the bootstrap_tables */ 485 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 486 ((long)oldcount << L2_SHIFT) + KERNBASE) { 487 oldcount++; 488 goto bootstrap_again; 489 } 490 491 /* Create temporary tables */ 492 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 493 xen_start_info.nr_pt_frames, oldcount, 0); 494 495 /* Create final tables */ 496 xen_bootstrap_tables(bootstrap_tables, init_tables, 497 oldcount + l2_4_count, count, 1); 498 499 /* zero out free space after tables */ 500 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 501 (UPAGES + 1) * NBPG); 502 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 503 } 504 505 506 /* 507 * Build a new table and switch to it 508 * old_count is # of old tables (including PGD, PDTPE and PDE) 509 * new_count is # of new tables (PTE only) 510 * we assume areas don't overlap 511 */ 512 513 514 static void 515 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 516 int old_count, int new_count, int final) 517 { 518 pd_entry_t *pdtpe, *pde, *pte; 519 pd_entry_t *cur_pgd, *bt_pgd; 520 paddr_t addr; 521 vaddr_t page, avail, text_end, map_end; 522 int i; 523 extern char __data_start; 524 525 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 526 " %d, %d)\n", 527 old_pgd, new_pgd, old_count, new_count)); 528 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 529 /* 530 * size of R/W area after kernel text: 531 * xencons_interface (if present) 532 * xenstore_interface (if present) 533 * table pages (new_count + l2_4_count entries) 534 * extra mappings (only when final is true): 535 * UAREA 536 * dummy user PGD (x86_64 only)/gdt page (i386 only) 537 * HYPERVISOR_shared_info 538 * ISA I/O mem (if needed) 539 */ 540 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 541 if (final) { 542 map_end += (UPAGES + 1) * NBPG; 543 HYPERVISOR_shared_info = (shared_info_t *)map_end; 544 map_end += NBPG; 545 } 546 /* 547 * we always set atdevbase, as it's used by init386 to find the first 548 * available VA. map_end is updated only if we are dom0, so 549 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 550 * this case. 551 */ 552 if (final) 553 atdevbase = map_end; 554 #ifdef DOM0OPS 555 if (final && xendomain_is_dom0()) { 556 /* ISA I/O mem */ 557 map_end += IOM_SIZE; 558 } 559 #endif /* DOM0OPS */ 560 561 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 562 text_end, map_end)); 563 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 564 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 565 566 /* 567 * Create bootstrap page tables 568 * What we need: 569 * - a PGD (level 4) 570 * - a PDTPE (level 3) 571 * - a PDE (level2) 572 * - some PTEs (level 1) 573 */ 574 575 cur_pgd = (pd_entry_t *) old_pgd; 576 bt_pgd = (pd_entry_t *) new_pgd; 577 memset (bt_pgd, 0, PAGE_SIZE); 578 avail = new_pgd + PAGE_SIZE; 579 #if PTP_LEVELS > 3 580 /* Install level 3 */ 581 pdtpe = (pd_entry_t *) avail; 582 memset (pdtpe, 0, PAGE_SIZE); 583 avail += PAGE_SIZE; 584 585 addr = ((u_long) pdtpe) - KERNBASE; 586 bt_pgd[pl4_pi(KERNTEXTOFF)] = 587 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 588 589 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 590 " -> L4[%#x]\n", 591 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 592 #else 593 pdtpe = bt_pgd; 594 #endif /* PTP_LEVELS > 3 */ 595 596 #if PTP_LEVELS > 2 597 /* Level 2 */ 598 pde = (pd_entry_t *) avail; 599 memset(pde, 0, PAGE_SIZE); 600 avail += PAGE_SIZE; 601 602 addr = ((u_long) pde) - KERNBASE; 603 pdtpe[pl3_pi(KERNTEXTOFF)] = 604 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 605 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 606 " -> L3[%#x]\n", 607 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 608 #elif defined(PAE) 609 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 610 pde = (pd_entry_t *) avail; 611 memset(pde, 0, PAGE_SIZE * 5); 612 avail += PAGE_SIZE * 5; 613 addr = ((u_long) pde) - KERNBASE; 614 /* 615 * enter L2 pages in the L3. 616 * The real L2 kernel PD will be the last one (so that 617 * pde[L2_SLOT_KERN] always point to the shadow). 618 */ 619 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 620 /* 621 * Xen doesn't want R/W mappings in L3 entries, it'll add it 622 * itself. 623 */ 624 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 625 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 626 " -> L3[%#x]\n", 627 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 628 } 629 addr += PAGE_SIZE; 630 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 631 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 632 " -> L3[%#x]\n", 633 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 634 635 #else /* PAE */ 636 pde = bt_pgd; 637 #endif /* PTP_LEVELS > 2 */ 638 639 /* Level 1 */ 640 page = KERNTEXTOFF; 641 for (i = 0; i < new_count; i ++) { 642 vaddr_t cur_page = page; 643 644 pte = (pd_entry_t *) avail; 645 avail += PAGE_SIZE; 646 647 memset(pte, 0, PAGE_SIZE); 648 while (pl2_pi(page) == pl2_pi (cur_page)) { 649 if (page >= map_end) { 650 /* not mapped at all */ 651 pte[pl1_pi(page)] = 0; 652 page += PAGE_SIZE; 653 continue; 654 } 655 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 656 if (page == (vaddr_t)HYPERVISOR_shared_info) { 657 pte[pl1_pi(page)] = xen_start_info.shared_info; 658 __PRINTK(("HYPERVISOR_shared_info " 659 "va %#lx pte %#" PRIxPADDR "\n", 660 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 661 } 662 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 663 == xen_start_info.console.domU.mfn) { 664 xencons_interface = (void *)page; 665 pte[pl1_pi(page)] = xen_start_info.console_mfn; 666 pte[pl1_pi(page)] <<= PAGE_SHIFT; 667 __PRINTK(("xencons_interface " 668 "va %#lx pte %#" PRIxPADDR "\n", 669 xencons_interface, pte[pl1_pi(page)])); 670 } 671 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 672 == xen_start_info.store_mfn) { 673 xenstore_interface = (void *)page; 674 pte[pl1_pi(page)] = xen_start_info.store_mfn; 675 pte[pl1_pi(page)] <<= PAGE_SHIFT; 676 __PRINTK(("xenstore_interface " 677 "va %#lx pte %#" PRIxPADDR "\n", 678 xenstore_interface, pte[pl1_pi(page)])); 679 } 680 #ifdef DOM0OPS 681 if (page >= (vaddr_t)atdevbase && 682 page < (vaddr_t)atdevbase + IOM_SIZE) { 683 pte[pl1_pi(page)] = 684 IOM_BEGIN + (page - (vaddr_t)atdevbase); 685 } 686 #endif 687 pte[pl1_pi(page)] |= PG_k | PG_V; 688 if (page < text_end) { 689 /* map kernel text RO */ 690 pte[pl1_pi(page)] |= 0; 691 } else if (page >= old_pgd 692 && page < old_pgd + (old_count * PAGE_SIZE)) { 693 /* map old page tables RO */ 694 pte[pl1_pi(page)] |= 0; 695 } else if (page >= new_pgd && 696 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 697 /* map new page tables RO */ 698 pte[pl1_pi(page)] |= 0; 699 } else { 700 /* map page RW */ 701 pte[pl1_pi(page)] |= PG_RW; 702 } 703 704 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 705 || page >= new_pgd) { 706 __PRINTK(("va %#lx pa %#lx " 707 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 708 page, page - KERNBASE, 709 pte[pl1_pi(page)], pl1_pi(page))); 710 } 711 page += PAGE_SIZE; 712 } 713 714 addr = ((u_long) pte) - KERNBASE; 715 pde[pl2_pi(cur_page)] = 716 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 717 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 718 " -> L2[%#x]\n", 719 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 720 /* Mark readonly */ 721 xen_bt_set_readonly((vaddr_t) pte); 722 } 723 724 /* Install recursive page tables mapping */ 725 #ifdef PAE 726 /* 727 * we need a shadow page for the kernel's L2 page 728 * The real L2 kernel PD will be the last one (so that 729 * pde[L2_SLOT_KERN] always point to the shadow. 730 */ 731 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 732 pmap_kl2pd = &pde[L2_SLOT_KERN + NPDPG]; 733 pmap_kl2paddr = (u_long)pmap_kl2pd - KERNBASE; 734 735 /* 736 * We don't enter a recursive entry from the L3 PD. Instead, 737 * we enter the first 4 L2 pages, which includes the kernel's L2 738 * shadow. But we have to entrer the shadow after switching 739 * %cr3, or Xen will refcount some PTE with the wrong type. 740 */ 741 addr = (u_long)pde - KERNBASE; 742 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 743 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 744 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 745 " entry %#" PRIxPADDR "\n", 746 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 747 addr, pde[PDIR_SLOT_PTE + i])); 748 } 749 #if 0 750 addr += PAGE_SIZE; /* point to shadow L2 */ 751 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 752 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 753 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 754 (int64_t)pde[PDIR_SLOT_PTE + 3])); 755 #endif 756 /* Mark tables RO, and pin the kernel's shadow as L2 */ 757 addr = (u_long)pde - KERNBASE; 758 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 759 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 760 if (i == 2 || i == 3) 761 continue; 762 #if 0 763 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 764 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 765 #endif 766 } 767 if (final) { 768 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 769 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 770 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 771 } 772 #if 0 773 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 774 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 775 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 776 #endif 777 #else /* PAE */ 778 /* recursive entry in higher-level PD */ 779 bt_pgd[PDIR_SLOT_PTE] = 780 xpmap_ptom_masked(new_pgd - KERNBASE) | PG_k | PG_V; 781 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 782 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 783 bt_pgd[PDIR_SLOT_PTE])); 784 /* Mark tables RO */ 785 xen_bt_set_readonly((vaddr_t) pde); 786 #endif 787 #if PTP_LEVELS > 2 || defined(PAE) 788 xen_bt_set_readonly((vaddr_t) pdtpe); 789 #endif 790 #if PTP_LEVELS > 3 791 xen_bt_set_readonly(new_pgd); 792 #endif 793 /* Pin the PGD */ 794 __PRINTK(("pin PGD\n")); 795 #ifdef __x86_64__ 796 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 797 #elif PAE 798 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 799 #elif defined(__x86_64__) 800 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 801 #else 802 xpq_queue_pin_l2_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 803 #endif 804 805 /* Save phys. addr of PDP, for libkvm. */ 806 #ifdef PAE 807 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 808 #else 809 PDPpaddr = (u_long)new_pgd - KERNBASE; 810 #endif 811 812 /* Switch to new tables */ 813 __PRINTK(("switch to PGD\n")); 814 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 815 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 816 bt_pgd[PDIR_SLOT_PTE])); 817 818 #ifdef PAE 819 if (final) { 820 /* save the address of the L3 page */ 821 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 822 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 823 824 /* now enter kernel's PTE mappings */ 825 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 826 xpq_queue_pte_update( 827 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 828 xpmap_ptom_masked(addr) | PG_k | PG_V); 829 xpq_flush_queue(); 830 } 831 #endif 832 833 /* Now we can safely reclaim space taken by old tables */ 834 835 __PRINTK(("unpin old PGD\n")); 836 /* Unpin old PGD */ 837 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 838 /* Mark old tables RW */ 839 page = old_pgd; 840 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 841 addr = xpmap_mtop(addr); 842 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 843 pte += pl1_pi(page); 844 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 845 pde[pl2_pi(page)], addr, (long)pte)); 846 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 847 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 848 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 849 "*pte %#" PRIxPADDR "\n", 850 addr, (long)pte, *pte)); 851 xpq_queue_pte_update(addr, *pte | PG_RW); 852 page += PAGE_SIZE; 853 /* 854 * Our ptes are contiguous 855 * so it's safe to just "++" here 856 */ 857 pte++; 858 } 859 xpq_flush_queue(); 860 } 861 862 863 /* 864 * Bootstrap helper functions 865 */ 866 867 /* 868 * Mark a page readonly 869 * XXX: assuming vaddr = paddr + KERNBASE 870 */ 871 872 static void 873 xen_bt_set_readonly (vaddr_t page) 874 { 875 pt_entry_t entry; 876 877 entry = xpmap_ptom_masked(page - KERNBASE); 878 entry |= PG_k | PG_V; 879 880 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 881 } 882 883 #ifdef __x86_64__ 884 void 885 xen_set_user_pgd(paddr_t page) 886 { 887 struct mmuext_op op; 888 int s = splvm(); 889 890 xpq_flush_queue(); 891 op.cmd = MMUEXT_NEW_USER_BASEPTR; 892 op.arg1.mfn = pfn_to_mfn(page >> PAGE_SHIFT); 893 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 894 panic("xen_set_user_pgd: failed to install new user page" 895 " directory %#" PRIxPADDR, page); 896 splx(s); 897 } 898 #endif /* __x86_64__ */ 899
Indexes created Wed Oct 22 06:10:02 GMT 2025