x86_xpmap.c revision 1.18
1 /* $NetBSD: x86_xpmap.c,v 1.18 2010/02/12 01:55:45 jym Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.18 2010/02/12 01:55:45 jym Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 81 #include <uvm/uvm.h> 82 83 #include <machine/pmap.h> 84 #include <machine/gdt.h> 85 #include <xen/xenfunc.h> 86 87 #include <dev/isa/isareg.h> 88 #include <machine/isa_machdep.h> 89 90 #undef XENDEBUG 91 /* #define XENDEBUG_SYNC */ 92 /* #define XENDEBUG_LOW */ 93 94 #ifdef XENDEBUG 95 #define XENPRINTF(x) printf x 96 #define XENPRINTK(x) printk x 97 #define XENPRINTK2(x) /* printk x */ 98 99 static char XBUF[256]; 100 #else 101 #define XENPRINTF(x) 102 #define XENPRINTK(x) 103 #define XENPRINTK2(x) 104 #endif 105 #define PRINTF(x) printf x 106 #define PRINTK(x) printk x 107 108 /* on x86_64 kernel runs in ring 3 */ 109 #ifdef __x86_64__ 110 #define PG_k PG_u 111 #else 112 #define PG_k 0 113 #endif 114 115 volatile shared_info_t *HYPERVISOR_shared_info; 116 /* Xen requires the start_info struct to be page aligned */ 117 union start_info_union start_info_union __aligned(PAGE_SIZE); 118 unsigned long *xpmap_phys_to_machine_mapping; 119 120 void xen_failsafe_handler(void); 121 122 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 123 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 124 125 void 126 xen_failsafe_handler(void) 127 { 128 129 panic("xen_failsafe_handler called!\n"); 130 } 131 132 133 void 134 xen_set_ldt(vaddr_t base, uint32_t entries) 135 { 136 vaddr_t va; 137 vaddr_t end; 138 pt_entry_t *ptp; 139 int s; 140 141 #ifdef __x86_64__ 142 end = base + (entries << 3); 143 #else 144 end = base + entries * sizeof(union descriptor); 145 #endif 146 147 for (va = base; va < end; va += PAGE_SIZE) { 148 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 149 ptp = kvtopte(va); 150 XENPRINTF(("xen_set_ldt %p %d %p\n", (void *)base, 151 entries, ptp)); 152 pmap_pte_clearbits(ptp, PG_RW); 153 } 154 s = splvm(); 155 xpq_queue_set_ldt(base, entries); 156 splx(s); 157 } 158 159 #ifdef XENDEBUG 160 void xpq_debug_dump(void); 161 #endif 162 163 #define XPQUEUE_SIZE 2048 164 static mmu_update_t xpq_queue[XPQUEUE_SIZE]; 165 static int xpq_idx = 0; 166 167 void 168 xpq_flush_queue(void) 169 { 170 int i, ok; 171 172 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 173 for (i = 0; i < xpq_idx; i++) 174 XENPRINTK2(("%d: %p %08" PRIx64 "\n", i, 175 (uint64_t)xpq_queue[i].ptr, (uint64_t)xpq_queue[i].val)); 176 if (xpq_idx != 0 && 177 HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok) < 0) { 178 printf("xpq_flush_queue: %d entries \n", xpq_idx); 179 for (i = 0; i < xpq_idx; i++) 180 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 181 (uint64_t)xpq_queue[i].ptr, 182 (uint64_t)xpq_queue[i].val); 183 panic("HYPERVISOR_mmu_update failed\n"); 184 } 185 xpq_idx = 0; 186 } 187 188 static inline void 189 xpq_increment_idx(void) 190 { 191 192 xpq_idx++; 193 if (__predict_false(xpq_idx == XPQUEUE_SIZE)) 194 xpq_flush_queue(); 195 } 196 197 void 198 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 199 { 200 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 201 "\n", (int64_t)ma, (int64_t)pa)); 202 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 203 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 204 xpq_increment_idx(); 205 #ifdef XENDEBUG_SYNC 206 xpq_flush_queue(); 207 #endif 208 } 209 210 void 211 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 212 { 213 214 KASSERT((ptr & 3) == 0); 215 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 216 xpq_queue[xpq_idx].val = val; 217 xpq_increment_idx(); 218 #ifdef XENDEBUG_SYNC 219 xpq_flush_queue(); 220 #endif 221 } 222 223 void 224 xpq_queue_pt_switch(paddr_t pa) 225 { 226 struct mmuext_op op; 227 xpq_flush_queue(); 228 229 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 230 (int64_t)pa, (int64_t)pa)); 231 op.cmd = MMUEXT_NEW_BASEPTR; 232 op.arg1.mfn = pa >> PAGE_SHIFT; 233 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 234 panic("xpq_queue_pt_switch"); 235 } 236 237 void 238 xpq_queue_pin_table(paddr_t pa) 239 { 240 struct mmuext_op op; 241 xpq_flush_queue(); 242 243 XENPRINTK2(("xpq_queue_pin_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 244 (int64_t)pa, (int64_t)pa)); 245 op.arg1.mfn = pa >> PAGE_SHIFT; 246 247 #if defined(__x86_64__) 248 op.cmd = MMUEXT_PIN_L4_TABLE; 249 #else 250 op.cmd = MMUEXT_PIN_L2_TABLE; 251 #endif 252 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 253 panic("xpq_queue_pin_table"); 254 } 255 256 #ifdef PAE 257 static void 258 xpq_queue_pin_l3_table(paddr_t pa) 259 { 260 struct mmuext_op op; 261 xpq_flush_queue(); 262 263 XENPRINTK2(("xpq_queue_pin_l2_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 264 (int64_t)pa, (int64_t)pa)); 265 op.arg1.mfn = pa >> PAGE_SHIFT; 266 267 op.cmd = MMUEXT_PIN_L3_TABLE; 268 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 269 panic("xpq_queue_pin_table"); 270 } 271 #endif 272 273 void 274 xpq_queue_unpin_table(paddr_t pa) 275 { 276 struct mmuext_op op; 277 xpq_flush_queue(); 278 279 XENPRINTK2(("xpq_queue_unpin_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 280 (int64_t)pa, (int64_t)pa)); 281 op.arg1.mfn = pa >> PAGE_SHIFT; 282 op.cmd = MMUEXT_UNPIN_TABLE; 283 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 284 panic("xpq_queue_unpin_table"); 285 } 286 287 void 288 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 289 { 290 struct mmuext_op op; 291 xpq_flush_queue(); 292 293 XENPRINTK2(("xpq_queue_set_ldt\n")); 294 KASSERT(va == (va & ~PAGE_MASK)); 295 op.cmd = MMUEXT_SET_LDT; 296 op.arg1.linear_addr = va; 297 op.arg2.nr_ents = entries; 298 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 299 panic("xpq_queue_set_ldt"); 300 } 301 302 void 303 xpq_queue_tlb_flush(void) 304 { 305 struct mmuext_op op; 306 xpq_flush_queue(); 307 308 XENPRINTK2(("xpq_queue_tlb_flush\n")); 309 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 310 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 311 panic("xpq_queue_tlb_flush"); 312 } 313 314 void 315 xpq_flush_cache(void) 316 { 317 struct mmuext_op op; 318 int s = splvm(); 319 xpq_flush_queue(); 320 321 XENPRINTK2(("xpq_queue_flush_cache\n")); 322 op.cmd = MMUEXT_FLUSH_CACHE; 323 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 324 panic("xpq_flush_cache"); 325 splx(s); 326 } 327 328 void 329 xpq_queue_invlpg(vaddr_t va) 330 { 331 struct mmuext_op op; 332 xpq_flush_queue(); 333 334 XENPRINTK2(("xpq_queue_invlpg %p\n", (void *)va)); 335 op.cmd = MMUEXT_INVLPG_LOCAL; 336 op.arg1.linear_addr = (va & ~PAGE_MASK); 337 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 338 panic("xpq_queue_invlpg"); 339 } 340 341 int 342 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 343 { 344 mmu_update_t op; 345 int ok; 346 xpq_flush_queue(); 347 348 op.ptr = ptr; 349 op.val = val; 350 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 351 return EFAULT; 352 return (0); 353 } 354 355 #ifdef XENDEBUG 356 void 357 xpq_debug_dump(void) 358 { 359 int i; 360 361 XENPRINTK2(("idx: %d\n", xpq_idx)); 362 for (i = 0; i < xpq_idx; i++) { 363 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 364 (uint64_t)xpq_queue[i].ptr, (uint64_t)xpq_queue[i].val); 365 if (++i < xpq_idx) 366 snprintf(XBUF + strlen(XBUF), 367 sizeof(XBUF) - strlen(XBUF), 368 "%" PRIx64 " %08" PRIx64, 369 (uint64_t)xpq_queue[i].ptr, 370 (uint64_t)xpq_queue[i].val); 371 if (++i < xpq_idx) 372 snprintf(XBUF + strlen(XBUF), 373 sizeof(XBUF) - strlen(XBUF), 374 "%" PRIx64 " %08" PRIx64, 375 (uint64_t)xpq_queue[i].ptr, 376 (uint64_t)xpq_queue[i].val); 377 if (++i < xpq_idx) 378 snprintf(XBUF + strlen(XBUF), 379 sizeof(XBUF) - strlen(XBUF), 380 "%" PRIx64 " %08" PRIx64, 381 (uint64_t)xpq_queue[i].ptr, 382 (uint64_t)xpq_queue[i].val); 383 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 384 } 385 } 386 #endif 387 388 389 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 390 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 391 392 static void xen_bt_set_readonly (vaddr_t); 393 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 394 395 /* How many PDEs ? */ 396 #if L2_SLOT_KERNBASE > 0 397 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 398 #else 399 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 400 #endif 401 402 /* 403 * Construct and switch to new pagetables 404 * first_avail is the first vaddr we can use after 405 * we get rid of Xen pagetables 406 */ 407 408 vaddr_t xen_pmap_bootstrap (void); 409 410 /* 411 * Function to get rid of Xen bootstrap tables 412 */ 413 414 /* How many PDP do we need: */ 415 #ifdef PAE 416 /* 417 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 418 * all of them mapped by the L3 page. We also need a shadow page 419 * for L3[3]. 420 */ 421 static const int l2_4_count = 6; 422 #else 423 static const int l2_4_count = PTP_LEVELS - 1; 424 #endif 425 426 vaddr_t 427 xen_pmap_bootstrap(void) 428 { 429 int count, oldcount; 430 long mapsize; 431 vaddr_t bootstrap_tables, init_tables; 432 433 xpmap_phys_to_machine_mapping = 434 (unsigned long *)xen_start_info.mfn_list; 435 init_tables = xen_start_info.pt_base; 436 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 437 438 /* Space after Xen boostrap tables should be free */ 439 bootstrap_tables = xen_start_info.pt_base + 440 (xen_start_info.nr_pt_frames * PAGE_SIZE); 441 442 /* 443 * Calculate how many space we need 444 * first everything mapped before the Xen bootstrap tables 445 */ 446 mapsize = init_tables - KERNTEXTOFF; 447 /* after the tables we'll have: 448 * - UAREA 449 * - dummy user PGD (x86_64) 450 * - HYPERVISOR_shared_info 451 * - ISA I/O mem (if needed) 452 */ 453 mapsize += UPAGES * NBPG; 454 #ifdef __x86_64__ 455 mapsize += NBPG; 456 #endif 457 mapsize += NBPG; 458 459 #ifdef DOM0OPS 460 if (xendomain_is_dom0()) { 461 /* space for ISA I/O mem */ 462 mapsize += IOM_SIZE; 463 } 464 #endif 465 /* at this point mapsize doens't include the table size */ 466 467 #ifdef __x86_64__ 468 count = TABLE_L2_ENTRIES; 469 #else 470 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 471 #endif /* __x86_64__ */ 472 473 /* now compute how many L2 pages we need exactly */ 474 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 475 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 476 ((long)count << L2_SHIFT) + KERNBASE) { 477 count++; 478 } 479 #ifndef __x86_64__ 480 /* 481 * one more L2 page: we'll alocate several pages after kva_start 482 * in pmap_bootstrap() before pmap_growkernel(), which have not been 483 * counted here. It's not a big issue to allocate one more L2 as 484 * pmap_growkernel() will be called anyway. 485 */ 486 count++; 487 nkptp[1] = count; 488 #endif 489 490 /* 491 * install bootstrap pages. We may need more L2 pages than will 492 * have the final table here, as it's installed after the final table 493 */ 494 oldcount = count; 495 496 bootstrap_again: 497 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 498 /* 499 * Xen space we'll reclaim may not be enough for our new page tables, 500 * move bootstrap tables if necessary 501 */ 502 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 503 bootstrap_tables = init_tables + 504 ((count + l2_4_count) * PAGE_SIZE); 505 /* make sure we have enough to map the bootstrap_tables */ 506 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 507 ((long)oldcount << L2_SHIFT) + KERNBASE) { 508 oldcount++; 509 goto bootstrap_again; 510 } 511 512 /* Create temporary tables */ 513 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 514 xen_start_info.nr_pt_frames, oldcount, 0); 515 516 /* Create final tables */ 517 xen_bootstrap_tables(bootstrap_tables, init_tables, 518 oldcount + l2_4_count, count, 1); 519 520 /* zero out free space after tables */ 521 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 522 (UPAGES + 1) * NBPG); 523 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 524 } 525 526 527 /* 528 * Build a new table and switch to it 529 * old_count is # of old tables (including PGD, PDTPE and PDE) 530 * new_count is # of new tables (PTE only) 531 * we assume areas don't overlap 532 */ 533 534 535 static void 536 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 537 int old_count, int new_count, int final) 538 { 539 pd_entry_t *pdtpe, *pde, *pte; 540 pd_entry_t *cur_pgd, *bt_pgd; 541 paddr_t addr; 542 vaddr_t page, avail, text_end, map_end; 543 int i; 544 extern char __data_start; 545 546 __PRINTK(("xen_bootstrap_tables(0x%lx, 0x%lx, %d, %d)\n", 547 old_pgd, new_pgd, old_count, new_count)); 548 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 549 /* 550 * size of R/W area after kernel text: 551 * xencons_interface (if present) 552 * xenstore_interface (if present) 553 * table pages (new_count + l2_4_count entries) 554 * extra mappings (only when final is true): 555 * UAREA 556 * dummy user PGD (x86_64 only)/gdt page (i386 only) 557 * HYPERVISOR_shared_info 558 * ISA I/O mem (if needed) 559 */ 560 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 561 if (final) { 562 map_end += (UPAGES + 1) * NBPG; 563 HYPERVISOR_shared_info = (shared_info_t *)map_end; 564 map_end += NBPG; 565 } 566 /* 567 * we always set atdevbase, as it's used by init386 to find the first 568 * available VA. map_end is updated only if we are dom0, so 569 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 570 * this case. 571 */ 572 if (final) 573 atdevbase = map_end; 574 #ifdef DOM0OPS 575 if (final && xendomain_is_dom0()) { 576 /* ISA I/O mem */ 577 map_end += IOM_SIZE; 578 } 579 #endif /* DOM0OPS */ 580 581 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 582 text_end, map_end)); 583 __PRINTK(("console 0x%lx ", xen_start_info.console.domU.mfn)); 584 __PRINTK(("xenstore 0x%lx\n", xen_start_info.store_mfn)); 585 586 /* 587 * Create bootstrap page tables 588 * What we need: 589 * - a PGD (level 4) 590 * - a PDTPE (level 3) 591 * - a PDE (level2) 592 * - some PTEs (level 1) 593 */ 594 595 cur_pgd = (pd_entry_t *) old_pgd; 596 bt_pgd = (pd_entry_t *) new_pgd; 597 memset (bt_pgd, 0, PAGE_SIZE); 598 avail = new_pgd + PAGE_SIZE; 599 #if PTP_LEVELS > 3 600 /* Install level 3 */ 601 pdtpe = (pd_entry_t *) avail; 602 memset (pdtpe, 0, PAGE_SIZE); 603 avail += PAGE_SIZE; 604 605 addr = ((u_long) pdtpe) - KERNBASE; 606 bt_pgd[pl4_pi(KERNTEXTOFF)] = 607 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 608 609 __PRINTK(("L3 va 0x%lx pa 0x%" PRIx64 " entry 0x%" PRIx64 " -> L4[0x%x]\n", 610 pdtpe, (uint64_t)addr, (uint64_t)bt_pgd[pl4_pi(KERNTEXTOFF)], 611 pl4_pi(KERNTEXTOFF))); 612 #else 613 pdtpe = bt_pgd; 614 #endif /* PTP_LEVELS > 3 */ 615 616 #if PTP_LEVELS > 2 617 /* Level 2 */ 618 pde = (pd_entry_t *) avail; 619 memset(pde, 0, PAGE_SIZE); 620 avail += PAGE_SIZE; 621 622 addr = ((u_long) pde) - KERNBASE; 623 pdtpe[pl3_pi(KERNTEXTOFF)] = 624 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 625 __PRINTK(("L2 va 0x%lx pa 0x%" PRIx64 " entry 0x%" PRIx64 " -> L3[0x%x]\n", 626 pde, (int64_t)addr, (int64_t)pdtpe[pl3_pi(KERNTEXTOFF)], 627 pl3_pi(KERNTEXTOFF))); 628 #elif defined(PAE) 629 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 630 pde = (pd_entry_t *) avail; 631 memset(pde, 0, PAGE_SIZE * 5); 632 avail += PAGE_SIZE * 5; 633 addr = ((u_long) pde) - KERNBASE; 634 /* 635 * enter L2 pages in the L3. 636 * The real L2 kernel PD will be the last one (so that 637 * pde[L2_SLOT_KERN] always point to the shadow). 638 */ 639 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 640 /* 641 * Xen doens't want R/W mappings in L3 entries, it'll add it 642 * itself. 643 */ 644 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 645 __PRINTK(("L2 va 0x%lx pa 0x%" PRIx64 " entry 0x%" PRIx64 646 " -> L3[0x%x]\n", (vaddr_t)pde + PAGE_SIZE * i, 647 (int64_t)addr, (int64_t)pdtpe[i], i)); 648 } 649 addr += PAGE_SIZE; 650 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 651 __PRINTK(("L2 va 0x%lx pa 0x%" PRIx64 " entry 0x%" PRIx64 652 " -> L3[0x%x]\n", (vaddr_t)pde + PAGE_SIZE * 4, 653 (int64_t)addr, (int64_t)pdtpe[3], 3)); 654 655 #else /* PAE */ 656 pde = bt_pgd; 657 #endif /* PTP_LEVELS > 2 */ 658 659 /* Level 1 */ 660 page = KERNTEXTOFF; 661 for (i = 0; i < new_count; i ++) { 662 vaddr_t cur_page = page; 663 664 pte = (pd_entry_t *) avail; 665 avail += PAGE_SIZE; 666 667 memset(pte, 0, PAGE_SIZE); 668 while (pl2_pi(page) == pl2_pi (cur_page)) { 669 if (page >= map_end) { 670 /* not mapped at all */ 671 pte[pl1_pi(page)] = 0; 672 page += PAGE_SIZE; 673 continue; 674 } 675 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 676 if (page == (vaddr_t)HYPERVISOR_shared_info) { 677 pte[pl1_pi(page)] = xen_start_info.shared_info; 678 __PRINTK(("HYPERVISOR_shared_info " 679 "va 0x%lx pte 0x%" PRIx64 "\n", 680 HYPERVISOR_shared_info, (int64_t)pte[pl1_pi(page)])); 681 } 682 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 683 == xen_start_info.console.domU.mfn) { 684 xencons_interface = (void *)page; 685 pte[pl1_pi(page)] = xen_start_info.console.domU.mfn; 686 pte[pl1_pi(page)] <<= PAGE_SHIFT; 687 __PRINTK(("xencons_interface " 688 "va 0x%lx pte 0x%" PRIx64 "\n", 689 xencons_interface, (int64_t)pte[pl1_pi(page)])); 690 } 691 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 692 == xen_start_info.store_mfn) { 693 xenstore_interface = (void *)page; 694 pte[pl1_pi(page)] = xen_start_info.store_mfn; 695 pte[pl1_pi(page)] <<= PAGE_SHIFT; 696 __PRINTK(("xenstore_interface " 697 "va 0x%lx pte 0x%" PRIx64 "\n", 698 xenstore_interface, (int64_t)pte[pl1_pi(page)])); 699 } 700 #ifdef DOM0OPS 701 if (page >= (vaddr_t)atdevbase && 702 page < (vaddr_t)atdevbase + IOM_SIZE) { 703 pte[pl1_pi(page)] = 704 IOM_BEGIN + (page - (vaddr_t)atdevbase); 705 } 706 #endif 707 pte[pl1_pi(page)] |= PG_k | PG_V; 708 if (page < text_end) { 709 /* map kernel text RO */ 710 pte[pl1_pi(page)] |= 0; 711 } else if (page >= old_pgd 712 && page < old_pgd + (old_count * PAGE_SIZE)) { 713 /* map old page tables RO */ 714 pte[pl1_pi(page)] |= 0; 715 } else if (page >= new_pgd && 716 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 717 /* map new page tables RO */ 718 pte[pl1_pi(page)] |= 0; 719 } else { 720 /* map page RW */ 721 pte[pl1_pi(page)] |= PG_RW; 722 } 723 724 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 725 || page >= new_pgd) { 726 __PRINTK(("va 0x%lx pa 0x%lx " 727 "entry 0x%" PRIx64 " -> L1[0x%x]\n", 728 page, page - KERNBASE, 729 (int64_t)pte[pl1_pi(page)], pl1_pi(page))); 730 } 731 page += PAGE_SIZE; 732 } 733 734 addr = ((u_long) pte) - KERNBASE; 735 pde[pl2_pi(cur_page)] = 736 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 737 __PRINTK(("L1 va 0x%lx pa 0x%" PRIx64 " entry 0x%" PRIx64 738 " -> L2[0x%x]\n", pte, (int64_t)addr, 739 (int64_t)pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 740 /* Mark readonly */ 741 xen_bt_set_readonly((vaddr_t) pte); 742 } 743 744 /* Install recursive page tables mapping */ 745 #ifdef PAE 746 /* 747 * we need a shadow page for the kernel's L2 page 748 * The real L2 kernel PD will be the last one (so that 749 * pde[L2_SLOT_KERN] always point to the shadow. 750 */ 751 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 752 pmap_kl2pd = &pde[L2_SLOT_KERN + NPDPG]; 753 pmap_kl2paddr = (u_long)pmap_kl2pd - KERNBASE; 754 755 /* 756 * We don't enter a recursive entry from the L3 PD. Instead, 757 * we enter the first 4 L2 pages, which includes the kernel's L2 758 * shadow. But we have to entrer the shadow after switching 759 * %cr3, or Xen will refcount some PTE with the wrong type. 760 */ 761 addr = (u_long)pde - KERNBASE; 762 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 763 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 764 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 765 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, (long)addr, 766 (int64_t)pde[PDIR_SLOT_PTE + i])); 767 } 768 #if 0 769 addr += PAGE_SIZE; /* point to shadow L2 */ 770 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 771 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 772 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 773 (int64_t)pde[PDIR_SLOT_PTE + 3])); 774 #endif 775 /* Mark tables RO, and pin the kernel's shadow as L2 */ 776 addr = (u_long)pde - KERNBASE; 777 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 778 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 779 if (i == 2 || i == 3) 780 continue; 781 #if 0 782 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 783 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 784 #endif 785 } 786 if (final) { 787 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 788 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 789 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 790 } 791 #if 0 792 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 793 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 794 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 795 #endif 796 #else /* PAE */ 797 /* recursive entry in higher-level PD */ 798 bt_pgd[PDIR_SLOT_PTE] = 799 xpmap_ptom_masked(new_pgd - KERNBASE) | PG_k | PG_V; 800 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] va 0x%lx pa 0x%" PRIx64 801 " entry 0x%" PRIx64 "\n", new_pgd, (int64_t)new_pgd - KERNBASE, 802 (int64_t)bt_pgd[PDIR_SLOT_PTE])); 803 /* Mark tables RO */ 804 xen_bt_set_readonly((vaddr_t) pde); 805 #endif 806 #if PTP_LEVELS > 2 || defined(PAE) 807 xen_bt_set_readonly((vaddr_t) pdtpe); 808 #endif 809 #if PTP_LEVELS > 3 810 xen_bt_set_readonly(new_pgd); 811 #endif 812 /* Pin the PGD */ 813 __PRINTK(("pin PGD\n")); 814 #ifdef PAE 815 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 816 #else 817 xpq_queue_pin_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 818 #endif 819 #ifdef __i386__ 820 /* Save phys. addr of PDP, for libkvm. */ 821 PDPpaddr = (long)pde; 822 #ifdef PAE 823 /* also save the address of the L3 page */ 824 pmap_l3pd = pdtpe; 825 pmap_l3paddr = (new_pgd - KERNBASE); 826 #endif /* PAE */ 827 #endif /* i386 */ 828 /* Switch to new tables */ 829 __PRINTK(("switch to PGD\n")); 830 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 831 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry 0x%" PRIx64 "\n", 832 (int64_t)bt_pgd[PDIR_SLOT_PTE])); 833 #ifdef PAE 834 if (final) { 835 /* now enter kernel's PTE mappings */ 836 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 837 xpq_queue_pte_update( 838 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 839 xpmap_ptom_masked(addr) | PG_k | PG_V); 840 xpq_flush_queue(); 841 } 842 #endif 843 844 845 846 /* Now we can safely reclaim space taken by old tables */ 847 848 __PRINTK(("unpin old PGD\n")); 849 /* Unpin old PGD */ 850 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 851 /* Mark old tables RW */ 852 page = old_pgd; 853 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 854 addr = xpmap_mtop(addr); 855 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 856 pte += pl1_pi(page); 857 __PRINTK(("*pde 0x%" PRIx64 " addr 0x%" PRIx64 " pte 0x%lx\n", 858 (int64_t)pde[pl2_pi(page)], (int64_t)addr, (long)pte)); 859 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 860 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 861 XENPRINTK(("addr 0x%" PRIx64 " pte 0x%lx *pte 0x%" PRIx64 "\n", 862 (int64_t)addr, (long)pte, (int64_t)*pte)); 863 xpq_queue_pte_update(addr, *pte | PG_RW); 864 page += PAGE_SIZE; 865 /* 866 * Our ptes are contiguous 867 * so it's safe to just "++" here 868 */ 869 pte++; 870 } 871 xpq_flush_queue(); 872 } 873 874 875 /* 876 * Bootstrap helper functions 877 */ 878 879 /* 880 * Mark a page readonly 881 * XXX: assuming vaddr = paddr + KERNBASE 882 */ 883 884 static void 885 xen_bt_set_readonly (vaddr_t page) 886 { 887 pt_entry_t entry; 888 889 entry = xpmap_ptom_masked(page - KERNBASE); 890 entry |= PG_k | PG_V; 891 892 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 893 } 894 895 #ifdef __x86_64__ 896 void 897 xen_set_user_pgd(paddr_t page) 898 { 899 struct mmuext_op op; 900 int s = splvm(); 901 902 xpq_flush_queue(); 903 op.cmd = MMUEXT_NEW_USER_BASEPTR; 904 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 905 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 906 panic("xen_set_user_pgd: failed to install new user page" 907 " directory %lx", page); 908 splx(s); 909 } 910 #endif /* __x86_64__ */ 911
Indexes created Tue Oct 21 08:09:48 GMT 2025