x86_xpmap.c revision 1.22
1 /* $NetBSD: x86_xpmap.c,v 1.22 2010/12/19 23:23:35 jym Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.22 2010/12/19 23:23:35 jym Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 81 #include <uvm/uvm.h> 82 83 #include <machine/pmap.h> 84 #include <machine/gdt.h> 85 #include <xen/xenfunc.h> 86 87 #include <dev/isa/isareg.h> 88 #include <machine/isa_machdep.h> 89 90 #undef XENDEBUG 91 /* #define XENDEBUG_SYNC */ 92 /* #define XENDEBUG_LOW */ 93 94 #ifdef XENDEBUG 95 #define XENPRINTF(x) printf x 96 #define XENPRINTK(x) printk x 97 #define XENPRINTK2(x) /* printk x */ 98 99 static char XBUF[256]; 100 #else 101 #define XENPRINTF(x) 102 #define XENPRINTK(x) 103 #define XENPRINTK2(x) 104 #endif 105 #define PRINTF(x) printf x 106 #define PRINTK(x) printk x 107 108 /* on x86_64 kernel runs in ring 3 */ 109 #ifdef __x86_64__ 110 #define PG_k PG_u 111 #else 112 #define PG_k 0 113 #endif 114 115 volatile shared_info_t *HYPERVISOR_shared_info; 116 /* Xen requires the start_info struct to be page aligned */ 117 union start_info_union start_info_union __aligned(PAGE_SIZE); 118 unsigned long *xpmap_phys_to_machine_mapping; 119 120 void xen_failsafe_handler(void); 121 122 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 123 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 124 125 void 126 xen_failsafe_handler(void) 127 { 128 129 panic("xen_failsafe_handler called!\n"); 130 } 131 132 133 void 134 xen_set_ldt(vaddr_t base, uint32_t entries) 135 { 136 vaddr_t va; 137 vaddr_t end; 138 pt_entry_t *ptp; 139 int s; 140 141 #ifdef __x86_64__ 142 end = base + (entries << 3); 143 #else 144 end = base + entries * sizeof(union descriptor); 145 #endif 146 147 for (va = base; va < end; va += PAGE_SIZE) { 148 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 149 ptp = kvtopte(va); 150 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 151 base, entries, ptp)); 152 pmap_pte_clearbits(ptp, PG_RW); 153 } 154 s = splvm(); 155 xpq_queue_set_ldt(base, entries); 156 splx(s); 157 } 158 159 #ifdef XENDEBUG 160 void xpq_debug_dump(void); 161 #endif 162 163 #define XPQUEUE_SIZE 2048 164 static mmu_update_t xpq_queue[XPQUEUE_SIZE]; 165 static int xpq_idx = 0; 166 167 void 168 xpq_flush_queue(void) 169 { 170 int i, ok; 171 172 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 173 for (i = 0; i < xpq_idx; i++) 174 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 175 xpq_queue[i].ptr, xpq_queue[i].val)); 176 if (xpq_idx != 0 && 177 HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok) < 0) { 178 printf("xpq_flush_queue: %d entries (%d successful)\n", 179 xpq_idx, ok); 180 for (i = 0; i < xpq_idx; i++) 181 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 182 xpq_queue[i].ptr, xpq_queue[i].val); 183 panic("HYPERVISOR_mmu_update failed\n"); 184 } 185 xpq_idx = 0; 186 } 187 188 static inline void 189 xpq_increment_idx(void) 190 { 191 192 xpq_idx++; 193 if (__predict_false(xpq_idx == XPQUEUE_SIZE)) 194 xpq_flush_queue(); 195 } 196 197 void 198 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 199 { 200 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 201 "\n", (int64_t)ma, (int64_t)pa)); 202 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 203 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 204 xpq_increment_idx(); 205 #ifdef XENDEBUG_SYNC 206 xpq_flush_queue(); 207 #endif 208 } 209 210 void 211 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 212 { 213 214 KASSERT((ptr & 3) == 0); 215 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 216 xpq_queue[xpq_idx].val = val; 217 xpq_increment_idx(); 218 #ifdef XENDEBUG_SYNC 219 xpq_flush_queue(); 220 #endif 221 } 222 223 void 224 xpq_queue_pt_switch(paddr_t pa) 225 { 226 struct mmuext_op op; 227 xpq_flush_queue(); 228 229 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 230 (int64_t)pa, (int64_t)pa)); 231 op.cmd = MMUEXT_NEW_BASEPTR; 232 op.arg1.mfn = pa >> PAGE_SHIFT; 233 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 234 panic("xpq_queue_pt_switch"); 235 } 236 237 void 238 xpq_queue_pin_table(paddr_t pa) 239 { 240 struct mmuext_op op; 241 xpq_flush_queue(); 242 243 XENPRINTK2(("xpq_queue_pin_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 244 (int64_t)pa, (int64_t)pa)); 245 op.arg1.mfn = pa >> PAGE_SHIFT; 246 247 #if defined(__x86_64__) 248 op.cmd = MMUEXT_PIN_L4_TABLE; 249 #else 250 op.cmd = MMUEXT_PIN_L2_TABLE; 251 #endif 252 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 253 panic("xpq_queue_pin_table"); 254 } 255 256 #ifdef PAE 257 static void 258 xpq_queue_pin_l3_table(paddr_t pa) 259 { 260 struct mmuext_op op; 261 xpq_flush_queue(); 262 263 XENPRINTK2(("xpq_queue_pin_l2_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 264 (int64_t)pa, (int64_t)pa)); 265 op.arg1.mfn = pa >> PAGE_SHIFT; 266 267 op.cmd = MMUEXT_PIN_L3_TABLE; 268 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 269 panic("xpq_queue_pin_table"); 270 } 271 #endif 272 273 void 274 xpq_queue_unpin_table(paddr_t pa) 275 { 276 struct mmuext_op op; 277 xpq_flush_queue(); 278 279 XENPRINTK2(("xpq_queue_unpin_table: 0x%" PRIx64 " 0x%" PRIx64 "\n", 280 (int64_t)pa, (int64_t)pa)); 281 op.arg1.mfn = pa >> PAGE_SHIFT; 282 op.cmd = MMUEXT_UNPIN_TABLE; 283 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 284 panic("xpq_queue_unpin_table"); 285 } 286 287 void 288 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 289 { 290 struct mmuext_op op; 291 xpq_flush_queue(); 292 293 XENPRINTK2(("xpq_queue_set_ldt\n")); 294 KASSERT(va == (va & ~PAGE_MASK)); 295 op.cmd = MMUEXT_SET_LDT; 296 op.arg1.linear_addr = va; 297 op.arg2.nr_ents = entries; 298 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 299 panic("xpq_queue_set_ldt"); 300 } 301 302 void 303 xpq_queue_tlb_flush(void) 304 { 305 struct mmuext_op op; 306 xpq_flush_queue(); 307 308 XENPRINTK2(("xpq_queue_tlb_flush\n")); 309 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 310 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 311 panic("xpq_queue_tlb_flush"); 312 } 313 314 void 315 xpq_flush_cache(void) 316 { 317 struct mmuext_op op; 318 int s = splvm(); 319 xpq_flush_queue(); 320 321 XENPRINTK2(("xpq_queue_flush_cache\n")); 322 op.cmd = MMUEXT_FLUSH_CACHE; 323 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 324 panic("xpq_flush_cache"); 325 splx(s); 326 } 327 328 void 329 xpq_queue_invlpg(vaddr_t va) 330 { 331 struct mmuext_op op; 332 xpq_flush_queue(); 333 334 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 335 op.cmd = MMUEXT_INVLPG_LOCAL; 336 op.arg1.linear_addr = (va & ~PAGE_MASK); 337 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 338 panic("xpq_queue_invlpg"); 339 } 340 341 int 342 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 343 { 344 mmu_update_t op; 345 int ok; 346 xpq_flush_queue(); 347 348 op.ptr = ptr; 349 op.val = val; 350 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 351 return EFAULT; 352 return (0); 353 } 354 355 #ifdef XENDEBUG 356 void 357 xpq_debug_dump(void) 358 { 359 int i; 360 361 XENPRINTK2(("idx: %d\n", xpq_idx)); 362 for (i = 0; i < xpq_idx; i++) { 363 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 364 xpq_queue[i].ptr, xpq_queue[i].val); 365 if (++i < xpq_idx) 366 snprintf(XBUF + strlen(XBUF), 367 sizeof(XBUF) - strlen(XBUF), 368 "%" PRIx64 " %08" PRIx64, 369 xpq_queue[i].ptr, xpq_queue[i].val); 370 if (++i < xpq_idx) 371 snprintf(XBUF + strlen(XBUF), 372 sizeof(XBUF) - strlen(XBUF), 373 "%" PRIx64 " %08" PRIx64, 374 xpq_queue[i].ptr, xpq_queue[i].val); 375 if (++i < xpq_idx) 376 snprintf(XBUF + strlen(XBUF), 377 sizeof(XBUF) - strlen(XBUF), 378 "%" PRIx64 " %08" PRIx64, 379 xpq_queue[i].ptr, xpq_queue[i].val); 380 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 381 } 382 } 383 #endif 384 385 386 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 387 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 388 389 static void xen_bt_set_readonly (vaddr_t); 390 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 391 392 /* How many PDEs ? */ 393 #if L2_SLOT_KERNBASE > 0 394 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 395 #else 396 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 397 #endif 398 399 /* 400 * Construct and switch to new pagetables 401 * first_avail is the first vaddr we can use after 402 * we get rid of Xen pagetables 403 */ 404 405 vaddr_t xen_pmap_bootstrap (void); 406 407 /* 408 * Function to get rid of Xen bootstrap tables 409 */ 410 411 /* How many PDP do we need: */ 412 #ifdef PAE 413 /* 414 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 415 * all of them mapped by the L3 page. We also need a shadow page 416 * for L3[3]. 417 */ 418 static const int l2_4_count = 6; 419 #else 420 static const int l2_4_count = PTP_LEVELS - 1; 421 #endif 422 423 vaddr_t 424 xen_pmap_bootstrap(void) 425 { 426 int count, oldcount; 427 long mapsize; 428 vaddr_t bootstrap_tables, init_tables; 429 430 xpmap_phys_to_machine_mapping = 431 (unsigned long *)xen_start_info.mfn_list; 432 init_tables = xen_start_info.pt_base; 433 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 434 435 /* Space after Xen boostrap tables should be free */ 436 bootstrap_tables = xen_start_info.pt_base + 437 (xen_start_info.nr_pt_frames * PAGE_SIZE); 438 439 /* 440 * Calculate how many space we need 441 * first everything mapped before the Xen bootstrap tables 442 */ 443 mapsize = init_tables - KERNTEXTOFF; 444 /* after the tables we'll have: 445 * - UAREA 446 * - dummy user PGD (x86_64) 447 * - HYPERVISOR_shared_info 448 * - ISA I/O mem (if needed) 449 */ 450 mapsize += UPAGES * NBPG; 451 #ifdef __x86_64__ 452 mapsize += NBPG; 453 #endif 454 mapsize += NBPG; 455 456 #ifdef DOM0OPS 457 if (xendomain_is_dom0()) { 458 /* space for ISA I/O mem */ 459 mapsize += IOM_SIZE; 460 } 461 #endif 462 /* at this point mapsize doens't include the table size */ 463 464 #ifdef __x86_64__ 465 count = TABLE_L2_ENTRIES; 466 #else 467 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 468 #endif /* __x86_64__ */ 469 470 /* now compute how many L2 pages we need exactly */ 471 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 472 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 473 ((long)count << L2_SHIFT) + KERNBASE) { 474 count++; 475 } 476 #ifndef __x86_64__ 477 /* 478 * one more L2 page: we'll alocate several pages after kva_start 479 * in pmap_bootstrap() before pmap_growkernel(), which have not been 480 * counted here. It's not a big issue to allocate one more L2 as 481 * pmap_growkernel() will be called anyway. 482 */ 483 count++; 484 nkptp[1] = count; 485 #endif 486 487 /* 488 * install bootstrap pages. We may need more L2 pages than will 489 * have the final table here, as it's installed after the final table 490 */ 491 oldcount = count; 492 493 bootstrap_again: 494 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 495 /* 496 * Xen space we'll reclaim may not be enough for our new page tables, 497 * move bootstrap tables if necessary 498 */ 499 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 500 bootstrap_tables = init_tables + 501 ((count + l2_4_count) * PAGE_SIZE); 502 /* make sure we have enough to map the bootstrap_tables */ 503 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 504 ((long)oldcount << L2_SHIFT) + KERNBASE) { 505 oldcount++; 506 goto bootstrap_again; 507 } 508 509 /* Create temporary tables */ 510 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 511 xen_start_info.nr_pt_frames, oldcount, 0); 512 513 /* Create final tables */ 514 xen_bootstrap_tables(bootstrap_tables, init_tables, 515 oldcount + l2_4_count, count, 1); 516 517 /* zero out free space after tables */ 518 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 519 (UPAGES + 1) * NBPG); 520 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 521 } 522 523 524 /* 525 * Build a new table and switch to it 526 * old_count is # of old tables (including PGD, PDTPE and PDE) 527 * new_count is # of new tables (PTE only) 528 * we assume areas don't overlap 529 */ 530 531 532 static void 533 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 534 int old_count, int new_count, int final) 535 { 536 pd_entry_t *pdtpe, *pde, *pte; 537 pd_entry_t *cur_pgd, *bt_pgd; 538 paddr_t addr; 539 vaddr_t page, avail, text_end, map_end; 540 int i; 541 extern char __data_start; 542 543 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 544 " %d, %d)\n", 545 old_pgd, new_pgd, old_count, new_count)); 546 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 547 /* 548 * size of R/W area after kernel text: 549 * xencons_interface (if present) 550 * xenstore_interface (if present) 551 * table pages (new_count + l2_4_count entries) 552 * extra mappings (only when final is true): 553 * UAREA 554 * dummy user PGD (x86_64 only)/gdt page (i386 only) 555 * HYPERVISOR_shared_info 556 * ISA I/O mem (if needed) 557 */ 558 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 559 if (final) { 560 map_end += (UPAGES + 1) * NBPG; 561 HYPERVISOR_shared_info = (shared_info_t *)map_end; 562 map_end += NBPG; 563 } 564 /* 565 * we always set atdevbase, as it's used by init386 to find the first 566 * available VA. map_end is updated only if we are dom0, so 567 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 568 * this case. 569 */ 570 if (final) 571 atdevbase = map_end; 572 #ifdef DOM0OPS 573 if (final && xendomain_is_dom0()) { 574 /* ISA I/O mem */ 575 map_end += IOM_SIZE; 576 } 577 #endif /* DOM0OPS */ 578 579 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 580 text_end, map_end)); 581 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 582 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 583 584 /* 585 * Create bootstrap page tables 586 * What we need: 587 * - a PGD (level 4) 588 * - a PDTPE (level 3) 589 * - a PDE (level2) 590 * - some PTEs (level 1) 591 */ 592 593 cur_pgd = (pd_entry_t *) old_pgd; 594 bt_pgd = (pd_entry_t *) new_pgd; 595 memset (bt_pgd, 0, PAGE_SIZE); 596 avail = new_pgd + PAGE_SIZE; 597 #if PTP_LEVELS > 3 598 /* Install level 3 */ 599 pdtpe = (pd_entry_t *) avail; 600 memset (pdtpe, 0, PAGE_SIZE); 601 avail += PAGE_SIZE; 602 603 addr = ((u_long) pdtpe) - KERNBASE; 604 bt_pgd[pl4_pi(KERNTEXTOFF)] = 605 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 606 607 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 608 " -> L4[%#x]\n", 609 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 610 #else 611 pdtpe = bt_pgd; 612 #endif /* PTP_LEVELS > 3 */ 613 614 #if PTP_LEVELS > 2 615 /* Level 2 */ 616 pde = (pd_entry_t *) avail; 617 memset(pde, 0, PAGE_SIZE); 618 avail += PAGE_SIZE; 619 620 addr = ((u_long) pde) - KERNBASE; 621 pdtpe[pl3_pi(KERNTEXTOFF)] = 622 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 623 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 624 " -> L3[%#x]\n", 625 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 626 #elif defined(PAE) 627 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 628 pde = (pd_entry_t *) avail; 629 memset(pde, 0, PAGE_SIZE * 5); 630 avail += PAGE_SIZE * 5; 631 addr = ((u_long) pde) - KERNBASE; 632 /* 633 * enter L2 pages in the L3. 634 * The real L2 kernel PD will be the last one (so that 635 * pde[L2_SLOT_KERN] always point to the shadow). 636 */ 637 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 638 /* 639 * Xen doens't want R/W mappings in L3 entries, it'll add it 640 * itself. 641 */ 642 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 643 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 644 " -> L3[%#x]\n", 645 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 646 } 647 addr += PAGE_SIZE; 648 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 649 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 650 " -> L3[%#x]\n", 651 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 652 653 #else /* PAE */ 654 pde = bt_pgd; 655 #endif /* PTP_LEVELS > 2 */ 656 657 /* Level 1 */ 658 page = KERNTEXTOFF; 659 for (i = 0; i < new_count; i ++) { 660 vaddr_t cur_page = page; 661 662 pte = (pd_entry_t *) avail; 663 avail += PAGE_SIZE; 664 665 memset(pte, 0, PAGE_SIZE); 666 while (pl2_pi(page) == pl2_pi (cur_page)) { 667 if (page >= map_end) { 668 /* not mapped at all */ 669 pte[pl1_pi(page)] = 0; 670 page += PAGE_SIZE; 671 continue; 672 } 673 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 674 if (page == (vaddr_t)HYPERVISOR_shared_info) { 675 pte[pl1_pi(page)] = xen_start_info.shared_info; 676 __PRINTK(("HYPERVISOR_shared_info " 677 "va %#lx pte %#" PRIxPADDR "\n", 678 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 679 } 680 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 681 == xen_start_info.console.domU.mfn) { 682 xencons_interface = (void *)page; 683 pte[pl1_pi(page)] = xen_start_info.console_mfn; 684 pte[pl1_pi(page)] <<= PAGE_SHIFT; 685 __PRINTK(("xencons_interface " 686 "va %#lx pte %#" PRIxPADDR "\n", 687 xencons_interface, pte[pl1_pi(page)])); 688 } 689 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 690 == xen_start_info.store_mfn) { 691 xenstore_interface = (void *)page; 692 pte[pl1_pi(page)] = xen_start_info.store_mfn; 693 pte[pl1_pi(page)] <<= PAGE_SHIFT; 694 __PRINTK(("xenstore_interface " 695 "va %#lx pte %#" PRIxPADDR "\n", 696 xenstore_interface, pte[pl1_pi(page)])); 697 } 698 #ifdef DOM0OPS 699 if (page >= (vaddr_t)atdevbase && 700 page < (vaddr_t)atdevbase + IOM_SIZE) { 701 pte[pl1_pi(page)] = 702 IOM_BEGIN + (page - (vaddr_t)atdevbase); 703 } 704 #endif 705 pte[pl1_pi(page)] |= PG_k | PG_V; 706 if (page < text_end) { 707 /* map kernel text RO */ 708 pte[pl1_pi(page)] |= 0; 709 } else if (page >= old_pgd 710 && page < old_pgd + (old_count * PAGE_SIZE)) { 711 /* map old page tables RO */ 712 pte[pl1_pi(page)] |= 0; 713 } else if (page >= new_pgd && 714 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 715 /* map new page tables RO */ 716 pte[pl1_pi(page)] |= 0; 717 } else { 718 /* map page RW */ 719 pte[pl1_pi(page)] |= PG_RW; 720 } 721 722 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 723 || page >= new_pgd) { 724 __PRINTK(("va %#lx pa %#lx " 725 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 726 page, page - KERNBASE, 727 pte[pl1_pi(page)], pl1_pi(page))); 728 } 729 page += PAGE_SIZE; 730 } 731 732 addr = ((u_long) pte) - KERNBASE; 733 pde[pl2_pi(cur_page)] = 734 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 735 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 736 " -> L2[%#x]\n", 737 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 738 /* Mark readonly */ 739 xen_bt_set_readonly((vaddr_t) pte); 740 } 741 742 /* Install recursive page tables mapping */ 743 #ifdef PAE 744 /* 745 * we need a shadow page for the kernel's L2 page 746 * The real L2 kernel PD will be the last one (so that 747 * pde[L2_SLOT_KERN] always point to the shadow. 748 */ 749 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 750 pmap_kl2pd = &pde[L2_SLOT_KERN + NPDPG]; 751 pmap_kl2paddr = (u_long)pmap_kl2pd - KERNBASE; 752 753 /* 754 * We don't enter a recursive entry from the L3 PD. Instead, 755 * we enter the first 4 L2 pages, which includes the kernel's L2 756 * shadow. But we have to entrer the shadow after switching 757 * %cr3, or Xen will refcount some PTE with the wrong type. 758 */ 759 addr = (u_long)pde - KERNBASE; 760 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 761 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 762 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 763 " entry %#" PRIxPADDR "\n", 764 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 765 addr, pde[PDIR_SLOT_PTE + i])); 766 } 767 #if 0 768 addr += PAGE_SIZE; /* point to shadow L2 */ 769 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 770 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 771 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 772 (int64_t)pde[PDIR_SLOT_PTE + 3])); 773 #endif 774 /* Mark tables RO, and pin the kernel's shadow as L2 */ 775 addr = (u_long)pde - KERNBASE; 776 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 777 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 778 if (i == 2 || i == 3) 779 continue; 780 #if 0 781 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 782 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 783 #endif 784 } 785 if (final) { 786 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 787 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 788 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 789 } 790 #if 0 791 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 792 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 793 xpq_queue_pin_table(xpmap_ptom_masked(addr)); 794 #endif 795 #else /* PAE */ 796 /* recursive entry in higher-level PD */ 797 bt_pgd[PDIR_SLOT_PTE] = 798 xpmap_ptom_masked(new_pgd - KERNBASE) | PG_k | PG_V; 799 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 800 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 801 bt_pgd[PDIR_SLOT_PTE])); 802 /* Mark tables RO */ 803 xen_bt_set_readonly((vaddr_t) pde); 804 #endif 805 #if PTP_LEVELS > 2 || defined(PAE) 806 xen_bt_set_readonly((vaddr_t) pdtpe); 807 #endif 808 #if PTP_LEVELS > 3 809 xen_bt_set_readonly(new_pgd); 810 #endif 811 /* Pin the PGD */ 812 __PRINTK(("pin PGD\n")); 813 #ifdef PAE 814 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 815 #else 816 xpq_queue_pin_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 817 #endif 818 819 /* Save phys. addr of PDP, for libkvm. */ 820 #ifdef PAE 821 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 822 #else 823 PDPpaddr = (u_long)new_pgd - KERNBASE; 824 #endif 825 826 /* Switch to new tables */ 827 __PRINTK(("switch to PGD\n")); 828 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 829 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 830 bt_pgd[PDIR_SLOT_PTE])); 831 832 #ifdef PAE 833 if (final) { 834 /* save the address of the L3 page */ 835 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 836 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 837 838 /* now enter kernel's PTE mappings */ 839 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 840 xpq_queue_pte_update( 841 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 842 xpmap_ptom_masked(addr) | PG_k | PG_V); 843 xpq_flush_queue(); 844 } 845 #endif 846 847 /* Now we can safely reclaim space taken by old tables */ 848 849 __PRINTK(("unpin old PGD\n")); 850 /* Unpin old PGD */ 851 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 852 /* Mark old tables RW */ 853 page = old_pgd; 854 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 855 addr = xpmap_mtop(addr); 856 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 857 pte += pl1_pi(page); 858 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 859 pde[pl2_pi(page)], addr, (long)pte)); 860 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 861 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 862 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 863 "*pte %#" PRIxPADDR "\n", 864 addr, (long)pte, *pte)); 865 xpq_queue_pte_update(addr, *pte | PG_RW); 866 page += PAGE_SIZE; 867 /* 868 * Our ptes are contiguous 869 * so it's safe to just "++" here 870 */ 871 pte++; 872 } 873 xpq_flush_queue(); 874 } 875 876 877 /* 878 * Bootstrap helper functions 879 */ 880 881 /* 882 * Mark a page readonly 883 * XXX: assuming vaddr = paddr + KERNBASE 884 */ 885 886 static void 887 xen_bt_set_readonly (vaddr_t page) 888 { 889 pt_entry_t entry; 890 891 entry = xpmap_ptom_masked(page - KERNBASE); 892 entry |= PG_k | PG_V; 893 894 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 895 } 896 897 #ifdef __x86_64__ 898 void 899 xen_set_user_pgd(paddr_t page) 900 { 901 struct mmuext_op op; 902 int s = splvm(); 903 904 xpq_flush_queue(); 905 op.cmd = MMUEXT_NEW_USER_BASEPTR; 906 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 907 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 908 panic("xen_set_user_pgd: failed to install new user page" 909 " directory %#" PRIxPADDR, page); 910 splx(s); 911 } 912 #endif /* __x86_64__ */ 913
Indexes created Tue Sep 30 11:09:46 GMT 2025