x86_xpmap.c revision 1.26.2.10
1 /* $NetBSD: x86_xpmap.c,v 1.26.2.10 2011/09/18 16:48:23 cherry Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.26.2.10 2011/09/18 16:48:23 cherry Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/simplelock.h> 81 82 #include <uvm/uvm.h> 83 84 #include <machine/pmap.h> 85 #include <machine/gdt.h> 86 #include <xen/xenfunc.h> 87 88 #include <dev/isa/isareg.h> 89 #include <machine/isa_machdep.h> 90 91 #undef XENDEBUG 92 /* #define XENDEBUG_SYNC */ 93 /* #define XENDEBUG_LOW */ 94 95 #ifdef XENDEBUG 96 #define XENPRINTF(x) printf x 97 #define XENPRINTK(x) printk x 98 #define XENPRINTK2(x) /* printk x */ 99 100 static char XBUF[256]; 101 #else 102 #define XENPRINTF(x) 103 #define XENPRINTK(x) 104 #define XENPRINTK2(x) 105 #endif 106 #define PRINTF(x) printf x 107 #define PRINTK(x) printk x 108 109 /* on x86_64 kernel runs in ring 3 */ 110 #ifdef __x86_64__ 111 #define PG_k PG_u 112 #else 113 #define PG_k 0 114 #endif 115 116 volatile shared_info_t *HYPERVISOR_shared_info; 117 /* Xen requires the start_info struct to be page aligned */ 118 union start_info_union start_info_union __aligned(PAGE_SIZE); 119 unsigned long *xpmap_phys_to_machine_mapping; 120 121 void xen_failsafe_handler(void); 122 123 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 124 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 125 126 void 127 xen_failsafe_handler(void) 128 { 129 130 panic("xen_failsafe_handler called!\n"); 131 } 132 133 134 void 135 xen_set_ldt(vaddr_t base, uint32_t entries) 136 { 137 vaddr_t va; 138 vaddr_t end; 139 pt_entry_t *ptp; 140 int s; 141 142 #ifdef __x86_64__ 143 end = base + (entries << 3); 144 #else 145 end = base + entries * sizeof(union descriptor); 146 #endif 147 148 for (va = base; va < end; va += PAGE_SIZE) { 149 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 150 ptp = kvtopte(va); 151 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 152 base, entries, ptp)); 153 pmap_pte_clearbits(ptp, PG_RW); 154 } 155 s = splvm(); 156 xpq_queue_lock(); 157 xpq_queue_set_ldt(base, entries); 158 xpq_queue_unlock(); 159 splx(s); 160 } 161 162 #ifdef XENDEBUG 163 void xpq_debug_dump(void); 164 #endif 165 166 #define XPQUEUE_SIZE 2048 167 static mmu_update_t xpq_queue_array[MAXCPUS][XPQUEUE_SIZE]; 168 static int xpq_idx_array[MAXCPUS]; 169 170 #ifdef MULTIPROCESSOR 171 static struct simplelock xpq_lock[MAXCPUS]; 172 173 extern struct cpu_info * (*xpq_cpu)(void); 174 175 void 176 xpq_queue_lock(void) 177 { 178 simple_lock(&xpq_lock[xpq_cpu()->ci_cpuid]); 179 } 180 181 void 182 xpq_queue_unlock(void) 183 { 184 simple_unlock(&xpq_lock[xpq_cpu()->ci_cpuid]); 185 } 186 187 bool 188 xpq_queue_locked(void) 189 { 190 return simple_lock_held(&xpq_lock[xpq_cpu()->ci_cpuid]); 191 } 192 #endif /* MULTIPROCESSOR */ 193 194 /* Must be called with xpq_lock held */ 195 void 196 xpq_flush_queue(void) 197 { 198 int i, ok, ret; 199 200 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 201 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 202 203 KASSERT(xpq_queue_locked()); 204 205 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 206 for (i = 0; i < xpq_idx; i++) 207 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 208 xpq_queue[i].ptr, xpq_queue[i].val)); 209 210 ret = HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok); 211 212 if (xpq_idx != 0 && ret < 0) { 213 printf("xpq_flush_queue: %d entries (%d successful)\n", 214 xpq_idx, ok); 215 for (i = 0; i < xpq_idx; i++) 216 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 217 xpq_queue[i].ptr, xpq_queue[i].val); 218 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 219 } 220 xpq_idx_array[xpq_cpu()->ci_cpuid] = 0; 221 } 222 223 /* Must be called with xpq_lock held */ 224 static inline void 225 xpq_increment_idx(void) 226 { 227 228 KASSERT(xpq_queue_locked()); 229 230 if (__predict_false(++xpq_idx_array[xpq_cpu()->ci_cpuid] == XPQUEUE_SIZE)) 231 xpq_flush_queue(); 232 } 233 234 void 235 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 236 { 237 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 238 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 239 240 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 241 "\n", (int64_t)ma, (int64_t)pa)); 242 KASSERT(xpq_queue_locked()); 243 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 244 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 245 xpq_increment_idx(); 246 #ifdef XENDEBUG_SYNC 247 xpq_flush_queue(); 248 #endif 249 } 250 251 void 252 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 253 { 254 255 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 256 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 257 258 KASSERT((ptr & 3) == 0); 259 KASSERT(xpq_queue_locked()); 260 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 261 xpq_queue[xpq_idx].val = val; 262 xpq_increment_idx(); 263 #ifdef XENDEBUG_SYNC 264 xpq_flush_queue(); 265 #endif 266 } 267 268 void 269 xpq_queue_pt_switch(paddr_t pa) 270 { 271 struct mmuext_op op; 272 KASSERT(xpq_queue_locked()); 273 xpq_flush_queue(); 274 275 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 276 (int64_t)pa, (int64_t)pa)); 277 op.cmd = MMUEXT_NEW_BASEPTR; 278 op.arg1.mfn = pa >> PAGE_SHIFT; 279 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 280 panic("xpq_queue_pt_switch"); 281 } 282 283 void 284 xpq_queue_pin_table(paddr_t pa, int lvl) 285 { 286 struct mmuext_op op; 287 288 KASSERT(xpq_queue_locked()); 289 xpq_flush_queue(); 290 291 XENPRINTK2(("xpq_queue_pin_l%d_table: %#" PRIxPADDR "\n", 292 lvl + 1, pa)); 293 294 op.arg1.mfn = pa >> PAGE_SHIFT; 295 op.cmd = lvl; 296 297 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 298 panic("xpq_queue_pin_table"); 299 } 300 301 void 302 xpq_queue_unpin_table(paddr_t pa) 303 { 304 struct mmuext_op op; 305 306 KASSERT(xpq_queue_locked()); 307 xpq_flush_queue(); 308 309 XENPRINTK2(("xpq_queue_unpin_table: %#" PRIxPADDR "\n", pa)); 310 op.arg1.mfn = pa >> PAGE_SHIFT; 311 op.cmd = MMUEXT_UNPIN_TABLE; 312 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 313 panic("xpq_queue_unpin_table"); 314 } 315 316 void 317 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 318 { 319 struct mmuext_op op; 320 321 KASSERT(xpq_queue_locked()); 322 xpq_flush_queue(); 323 324 XENPRINTK2(("xpq_queue_set_ldt\n")); 325 KASSERT(va == (va & ~PAGE_MASK)); 326 op.cmd = MMUEXT_SET_LDT; 327 op.arg1.linear_addr = va; 328 op.arg2.nr_ents = entries; 329 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 330 panic("xpq_queue_set_ldt"); 331 } 332 333 void 334 xpq_queue_tlb_flush(void) 335 { 336 struct mmuext_op op; 337 338 KASSERT(xpq_queue_locked()); 339 xpq_flush_queue(); 340 341 XENPRINTK2(("xpq_queue_tlb_flush\n")); 342 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 343 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 344 panic("xpq_queue_tlb_flush"); 345 } 346 347 void 348 xpq_flush_cache(void) 349 { 350 struct mmuext_op op; 351 int s = splvm(), err; 352 353 xpq_queue_lock(); 354 xpq_flush_queue(); 355 356 XENPRINTK2(("xpq_queue_flush_cache\n")); 357 op.cmd = MMUEXT_FLUSH_CACHE; 358 if ((err = HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF)) < 0) 359 printf("errno == %d\n", err); 360 panic("xpq_flush_cache"); 361 xpq_queue_unlock(); 362 splx(s); /* XXX: removeme */ 363 } 364 365 void 366 xpq_queue_invlpg(vaddr_t va) 367 { 368 struct mmuext_op op; 369 KASSERT(xpq_queue_locked()); 370 xpq_flush_queue(); 371 372 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 373 op.cmd = MMUEXT_INVLPG_LOCAL; 374 op.arg1.linear_addr = (va & ~PAGE_MASK); 375 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 376 panic("xpq_queue_invlpg"); 377 } 378 379 void 380 xen_mcast_invlpg(vaddr_t va, uint32_t cpumask) 381 { 382 mmuext_op_t op; 383 384 KASSERT(xpq_queue_locked()); 385 386 /* Flush pending page updates */ 387 xpq_flush_queue(); 388 389 op.cmd = MMUEXT_INVLPG_MULTI; 390 op.arg1.linear_addr = va; 391 op.arg2.vcpumask = &cpumask; 392 393 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 394 panic("xpq_queue_invlpg_all"); 395 } 396 397 return; 398 } 399 400 void 401 xen_bcast_invlpg(vaddr_t va) 402 { 403 mmuext_op_t op; 404 405 /* Flush pending page updates */ 406 KASSERT(xpq_queue_locked()); 407 xpq_flush_queue(); 408 409 op.cmd = MMUEXT_INVLPG_ALL; 410 op.arg1.linear_addr = va; 411 412 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 413 panic("xpq_queue_invlpg_all"); 414 } 415 416 return; 417 } 418 419 /* This is a synchronous call. */ 420 void 421 xen_mcast_tlbflush(uint32_t cpumask) 422 { 423 mmuext_op_t op; 424 425 /* Flush pending page updates */ 426 KASSERT(xpq_queue_locked()); 427 xpq_flush_queue(); 428 429 op.cmd = MMUEXT_TLB_FLUSH_MULTI; 430 op.arg2.vcpumask = &cpumask; 431 432 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 433 panic("xpq_queue_invlpg_all"); 434 } 435 436 return; 437 } 438 439 /* This is a synchronous call. */ 440 void 441 xen_bcast_tlbflush(void) 442 { 443 mmuext_op_t op; 444 445 /* Flush pending page updates */ 446 KASSERT(xpq_queue_locked()); 447 xpq_flush_queue(); 448 449 op.cmd = MMUEXT_TLB_FLUSH_ALL; 450 451 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 452 panic("xpq_queue_invlpg_all"); 453 } 454 455 return; 456 } 457 458 /* This is a synchronous call. */ 459 void 460 xen_vcpu_mcast_invlpg(vaddr_t sva, vaddr_t eva, uint32_t cpumask) 461 { 462 KASSERT(eva > sva); 463 464 /* Flush pending page updates */ 465 KASSERT(xpq_queue_locked()); 466 xpq_flush_queue(); 467 468 /* Align to nearest page boundary */ 469 sva &= ~PAGE_MASK; 470 eva &= ~PAGE_MASK; 471 472 for ( ; sva <= eva; sva += PAGE_SIZE) { 473 xen_mcast_invlpg(sva, cpumask); 474 } 475 476 return; 477 } 478 479 /* This is a synchronous call. */ 480 void 481 xen_vcpu_bcast_invlpg(vaddr_t sva, vaddr_t eva) 482 { 483 KASSERT(eva > sva); 484 485 /* Flush pending page updates */ 486 KASSERT(xpq_queue_locked()); 487 xpq_flush_queue(); 488 489 /* Align to nearest page boundary */ 490 sva &= ~PAGE_MASK; 491 eva &= ~PAGE_MASK; 492 493 for ( ; sva <= eva; sva += PAGE_SIZE) { 494 xen_bcast_invlpg(sva); 495 } 496 497 return; 498 } 499 500 int 501 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 502 { 503 mmu_update_t op; 504 int ok; 505 506 KASSERT(xpq_queue_locked()); 507 xpq_flush_queue(); 508 509 op.ptr = ptr; 510 op.val = val; 511 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 512 return EFAULT; 513 return (0); 514 } 515 516 #ifdef XENDEBUG 517 void 518 xpq_debug_dump(void) 519 { 520 int i; 521 522 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 523 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 524 525 XENPRINTK2(("idx: %d\n", xpq_idx)); 526 for (i = 0; i < xpq_idx; i++) { 527 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 528 xpq_queue[i].ptr, xpq_queue[i].val); 529 if (++i < xpq_idx) 530 snprintf(XBUF + strlen(XBUF), 531 sizeof(XBUF) - strlen(XBUF), 532 "%" PRIx64 " %08" PRIx64, 533 xpq_queue[i].ptr, xpq_queue[i].val); 534 if (++i < xpq_idx) 535 snprintf(XBUF + strlen(XBUF), 536 sizeof(XBUF) - strlen(XBUF), 537 "%" PRIx64 " %08" PRIx64, 538 xpq_queue[i].ptr, xpq_queue[i].val); 539 if (++i < xpq_idx) 540 snprintf(XBUF + strlen(XBUF), 541 sizeof(XBUF) - strlen(XBUF), 542 "%" PRIx64 " %08" PRIx64, 543 xpq_queue[i].ptr, xpq_queue[i].val); 544 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 545 } 546 } 547 #endif 548 549 550 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 551 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 552 553 static void xen_bt_set_readonly (vaddr_t); 554 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 555 556 /* How many PDEs ? */ 557 #if L2_SLOT_KERNBASE > 0 558 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 559 #else 560 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 561 #endif 562 563 /* 564 * Construct and switch to new pagetables 565 * first_avail is the first vaddr we can use after 566 * we get rid of Xen pagetables 567 */ 568 569 vaddr_t xen_pmap_bootstrap (void); 570 571 /* 572 * Function to get rid of Xen bootstrap tables 573 */ 574 575 /* How many PDP do we need: */ 576 #ifdef PAE 577 /* 578 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 579 * all of them mapped by the L3 page. We also need a shadow page 580 * for L3[3]. 581 */ 582 static const int l2_4_count = 6; 583 #elif defined(__x86_64__) 584 static const int l2_4_count = PTP_LEVELS; 585 #else 586 static const int l2_4_count = PTP_LEVELS - 1; 587 #endif 588 589 vaddr_t 590 xen_pmap_bootstrap(void) 591 { 592 int count, oldcount, i; 593 long mapsize; 594 vaddr_t bootstrap_tables, init_tables; 595 596 memset(xpq_idx_array, 0, sizeof xpq_idx_array); 597 for (i = 0; i < MAXCPUS;i++) { 598 simple_lock_init(&xpq_lock[i]); 599 } 600 601 xpmap_phys_to_machine_mapping = 602 (unsigned long *)xen_start_info.mfn_list; 603 init_tables = xen_start_info.pt_base; 604 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 605 606 /* Space after Xen boostrap tables should be free */ 607 bootstrap_tables = xen_start_info.pt_base + 608 (xen_start_info.nr_pt_frames * PAGE_SIZE); 609 610 /* 611 * Calculate how many space we need 612 * first everything mapped before the Xen bootstrap tables 613 */ 614 mapsize = init_tables - KERNTEXTOFF; 615 /* after the tables we'll have: 616 * - UAREA 617 * - dummy user PGD (x86_64) 618 * - HYPERVISOR_shared_info 619 * - ISA I/O mem (if needed) 620 */ 621 mapsize += UPAGES * NBPG; 622 #ifdef __x86_64__ 623 mapsize += NBPG; 624 #endif 625 mapsize += NBPG; 626 627 #ifdef DOM0OPS 628 if (xendomain_is_dom0()) { 629 /* space for ISA I/O mem */ 630 mapsize += IOM_SIZE; 631 } 632 #endif 633 /* at this point mapsize doens't include the table size */ 634 635 #ifdef __x86_64__ 636 count = TABLE_L2_ENTRIES; 637 #else 638 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 639 #endif /* __x86_64__ */ 640 641 /* now compute how many L2 pages we need exactly */ 642 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 643 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 644 ((long)count << L2_SHIFT) + KERNBASE) { 645 count++; 646 } 647 #ifndef __x86_64__ 648 /* 649 * one more L2 page: we'll alocate several pages after kva_start 650 * in pmap_bootstrap() before pmap_growkernel(), which have not been 651 * counted here. It's not a big issue to allocate one more L2 as 652 * pmap_growkernel() will be called anyway. 653 */ 654 count++; 655 nkptp[1] = count; 656 #endif 657 658 /* 659 * install bootstrap pages. We may need more L2 pages than will 660 * have the final table here, as it's installed after the final table 661 */ 662 oldcount = count; 663 664 bootstrap_again: 665 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 666 /* 667 * Xen space we'll reclaim may not be enough for our new page tables, 668 * move bootstrap tables if necessary 669 */ 670 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 671 bootstrap_tables = init_tables + 672 ((count + l2_4_count) * PAGE_SIZE); 673 /* make sure we have enough to map the bootstrap_tables */ 674 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 675 ((long)oldcount << L2_SHIFT) + KERNBASE) { 676 oldcount++; 677 goto bootstrap_again; 678 } 679 680 /* Create temporary tables */ 681 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 682 xen_start_info.nr_pt_frames, oldcount, 0); 683 684 /* Create final tables */ 685 xen_bootstrap_tables(bootstrap_tables, init_tables, 686 oldcount + l2_4_count, count, 1); 687 688 /* zero out free space after tables */ 689 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 690 (UPAGES + 1) * NBPG); 691 692 /* Finally, flush TLB. */ 693 xpq_queue_lock(); 694 xpq_queue_tlb_flush(); 695 xpq_queue_unlock(); 696 697 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 698 } 699 700 /* 701 * Build a new table and switch to it 702 * old_count is # of old tables (including PGD, PDTPE and PDE) 703 * new_count is # of new tables (PTE only) 704 * we assume areas don't overlap 705 */ 706 static void 707 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 708 int old_count, int new_count, int final) 709 { 710 pd_entry_t *pdtpe, *pde, *pte; 711 pd_entry_t *cur_pgd, *bt_pgd; 712 paddr_t addr; 713 vaddr_t page, avail, text_end, map_end; 714 int i; 715 extern char __data_start; 716 717 xpq_queue_lock(); 718 719 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 720 " %d, %d)\n", 721 old_pgd, new_pgd, old_count, new_count)); 722 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 723 /* 724 * size of R/W area after kernel text: 725 * xencons_interface (if present) 726 * xenstore_interface (if present) 727 * table pages (new_count + l2_4_count entries) 728 * extra mappings (only when final is true): 729 * UAREA 730 * dummy user PGD (x86_64 only)/gdt page (i386 only) 731 * HYPERVISOR_shared_info 732 * ISA I/O mem (if needed) 733 */ 734 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 735 if (final) { 736 map_end += (UPAGES + 1) * NBPG; 737 HYPERVISOR_shared_info = (shared_info_t *)map_end; 738 map_end += NBPG; 739 } 740 /* 741 * we always set atdevbase, as it's used by init386 to find the first 742 * available VA. map_end is updated only if we are dom0, so 743 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 744 * this case. 745 */ 746 if (final) 747 atdevbase = map_end; 748 #ifdef DOM0OPS 749 if (final && xendomain_is_dom0()) { 750 /* ISA I/O mem */ 751 map_end += IOM_SIZE; 752 } 753 #endif /* DOM0OPS */ 754 755 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 756 text_end, map_end)); 757 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 758 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 759 760 /* 761 * Create bootstrap page tables 762 * What we need: 763 * - a PGD (level 4) 764 * - a PDTPE (level 3) 765 * - a PDE (level2) 766 * - some PTEs (level 1) 767 */ 768 769 cur_pgd = (pd_entry_t *) old_pgd; 770 bt_pgd = (pd_entry_t *) new_pgd; 771 memset (bt_pgd, 0, PAGE_SIZE); 772 avail = new_pgd + PAGE_SIZE; 773 #if PTP_LEVELS > 3 774 /* per-cpu L4 PD */ 775 pd_entry_t *bt_cpu_pgd = bt_pgd; 776 /* pmap_kernel() "shadow" L4 PD */ 777 bt_pgd = (pd_entry_t *) avail; 778 memset(bt_pgd, 0, PAGE_SIZE); 779 avail += PAGE_SIZE; 780 781 /* Install level 3 */ 782 pdtpe = (pd_entry_t *) avail; 783 memset (pdtpe, 0, PAGE_SIZE); 784 avail += PAGE_SIZE; 785 786 addr = ((u_long) pdtpe) - KERNBASE; 787 bt_pgd[pl4_pi(KERNTEXTOFF)] = bt_cpu_pgd[pl4_pi(KERNTEXTOFF)] = 788 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 789 790 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 791 " -> L4[%#x]\n", 792 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 793 #else 794 pdtpe = bt_pgd; 795 #endif /* PTP_LEVELS > 3 */ 796 797 #if PTP_LEVELS > 2 798 /* Level 2 */ 799 pde = (pd_entry_t *) avail; 800 memset(pde, 0, PAGE_SIZE); 801 avail += PAGE_SIZE; 802 803 addr = ((u_long) pde) - KERNBASE; 804 pdtpe[pl3_pi(KERNTEXTOFF)] = 805 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 806 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 807 " -> L3[%#x]\n", 808 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 809 #elif defined(PAE) 810 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 811 pde = (pd_entry_t *) avail; 812 memset(pde, 0, PAGE_SIZE * 5); 813 avail += PAGE_SIZE * 5; 814 addr = ((u_long) pde) - KERNBASE; 815 /* 816 * enter L2 pages in the L3. 817 * The real L2 kernel PD will be the last one (so that 818 * pde[L2_SLOT_KERN] always point to the shadow). 819 */ 820 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 821 /* 822 * Xen doesn't want R/W mappings in L3 entries, it'll add it 823 * itself. 824 */ 825 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 826 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 827 " -> L3[%#x]\n", 828 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 829 } 830 addr += PAGE_SIZE; 831 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 832 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 833 " -> L3[%#x]\n", 834 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 835 836 #else /* PAE */ 837 pde = bt_pgd; 838 #endif /* PTP_LEVELS > 2 */ 839 840 /* Level 1 */ 841 page = KERNTEXTOFF; 842 for (i = 0; i < new_count; i ++) { 843 vaddr_t cur_page = page; 844 845 pte = (pd_entry_t *) avail; 846 avail += PAGE_SIZE; 847 848 memset(pte, 0, PAGE_SIZE); 849 while (pl2_pi(page) == pl2_pi (cur_page)) { 850 if (page >= map_end) { 851 /* not mapped at all */ 852 pte[pl1_pi(page)] = 0; 853 page += PAGE_SIZE; 854 continue; 855 } 856 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 857 if (page == (vaddr_t)HYPERVISOR_shared_info) { 858 pte[pl1_pi(page)] = xen_start_info.shared_info; 859 __PRINTK(("HYPERVISOR_shared_info " 860 "va %#lx pte %#" PRIxPADDR "\n", 861 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 862 } 863 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 864 == xen_start_info.console.domU.mfn) { 865 xencons_interface = (void *)page; 866 pte[pl1_pi(page)] = xen_start_info.console_mfn; 867 pte[pl1_pi(page)] <<= PAGE_SHIFT; 868 __PRINTK(("xencons_interface " 869 "va %#lx pte %#" PRIxPADDR "\n", 870 xencons_interface, pte[pl1_pi(page)])); 871 } 872 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 873 == xen_start_info.store_mfn) { 874 xenstore_interface = (void *)page; 875 pte[pl1_pi(page)] = xen_start_info.store_mfn; 876 pte[pl1_pi(page)] <<= PAGE_SHIFT; 877 __PRINTK(("xenstore_interface " 878 "va %#lx pte %#" PRIxPADDR "\n", 879 xenstore_interface, pte[pl1_pi(page)])); 880 } 881 #ifdef DOM0OPS 882 if (page >= (vaddr_t)atdevbase && 883 page < (vaddr_t)atdevbase + IOM_SIZE) { 884 pte[pl1_pi(page)] = 885 IOM_BEGIN + (page - (vaddr_t)atdevbase); 886 } 887 #endif 888 pte[pl1_pi(page)] |= PG_k | PG_V; 889 if (page < text_end) { 890 /* map kernel text RO */ 891 pte[pl1_pi(page)] |= 0; 892 } else if (page >= old_pgd 893 && page < old_pgd + (old_count * PAGE_SIZE)) { 894 /* map old page tables RO */ 895 pte[pl1_pi(page)] |= 0; 896 } else if (page >= new_pgd && 897 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 898 /* map new page tables RO */ 899 pte[pl1_pi(page)] |= 0; 900 } else { 901 /* map page RW */ 902 pte[pl1_pi(page)] |= PG_RW; 903 } 904 905 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 906 || page >= new_pgd) { 907 __PRINTK(("va %#lx pa %#lx " 908 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 909 page, page - KERNBASE, 910 pte[pl1_pi(page)], pl1_pi(page))); 911 } 912 page += PAGE_SIZE; 913 } 914 915 addr = ((u_long) pte) - KERNBASE; 916 pde[pl2_pi(cur_page)] = 917 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 918 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 919 " -> L2[%#x]\n", 920 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 921 /* Mark readonly */ 922 xen_bt_set_readonly((vaddr_t) pte); 923 } 924 925 /* Install recursive page tables mapping */ 926 #ifdef PAE 927 /* 928 * we need a shadow page for the kernel's L2 page 929 * The real L2 kernel PD will be the last one (so that 930 * pde[L2_SLOT_KERN] always point to the shadow. 931 */ 932 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 933 cpu_info_primary.ci_kpm_pdir = &pde[L2_SLOT_KERN + NPDPG]; 934 cpu_info_primary.ci_kpm_pdirpa = 935 (vaddr_t) cpu_info_primary.ci_kpm_pdir - KERNBASE; 936 937 /* 938 * We don't enter a recursive entry from the L3 PD. Instead, 939 * we enter the first 4 L2 pages, which includes the kernel's L2 940 * shadow. But we have to entrer the shadow after switching 941 * %cr3, or Xen will refcount some PTE with the wrong type. 942 */ 943 addr = (u_long)pde - KERNBASE; 944 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 945 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 946 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 947 " entry %#" PRIxPADDR "\n", 948 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 949 addr, pde[PDIR_SLOT_PTE + i])); 950 } 951 #if 0 952 addr += PAGE_SIZE; /* point to shadow L2 */ 953 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 954 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 955 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 956 (int64_t)pde[PDIR_SLOT_PTE + 3])); 957 #endif 958 /* Mark tables RO, and pin the kernel's shadow as L2 */ 959 addr = (u_long)pde - KERNBASE; 960 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 961 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 962 if (i == 2 || i == 3) 963 continue; 964 #if 0 965 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 966 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 967 #endif 968 } 969 if (final) { 970 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 971 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 972 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 973 } 974 #if 0 975 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 976 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 977 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 978 #endif 979 #else /* PAE */ 980 /* recursive entry in higher-level per-cpu PD and pmap_kernel() */ 981 bt_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_pgd - KERNBASE) | PG_k | PG_V; 982 #ifdef __x86_64__ 983 bt_cpu_pgd[PDIR_SLOT_PTE] = 984 xpmap_ptom_masked((paddr_t)bt_cpu_pgd - KERNBASE) | PG_k | PG_V; 985 #endif /* __x86_64__ */ 986 __PRINTK(("bt_cpu_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 987 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 988 bt_pgd[PDIR_SLOT_PTE])); 989 990 991 /* Mark tables RO */ 992 xen_bt_set_readonly((vaddr_t) pde); 993 #endif 994 #if PTP_LEVELS > 2 || defined(PAE) 995 xen_bt_set_readonly((vaddr_t) pdtpe); 996 #endif 997 #if PTP_LEVELS > 3 998 xen_bt_set_readonly(new_pgd); 999 #endif 1000 /* Pin the PGD */ 1001 __PRINTK(("pin PGD: %"PRIxVADDR"\n", new_pgd - KERNBASE)); 1002 #ifdef __x86_64__ 1003 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1004 #elif PAE 1005 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1006 #else 1007 xpq_queue_pin_l2_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1008 #endif 1009 /* Save phys. addr of PDP, for libkvm. */ 1010 #ifdef PAE 1011 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 1012 #else 1013 PDPpaddr = (u_long)bt_pgd - KERNBASE; 1014 #endif 1015 1016 /* Switch to new tables */ 1017 __PRINTK(("switch to PGD\n")); 1018 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 1019 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 1020 bt_pgd[PDIR_SLOT_PTE])); 1021 1022 #ifdef PAE 1023 if (final) { 1024 /* save the address of the L3 page */ 1025 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 1026 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 1027 1028 /* now enter kernel's PTE mappings */ 1029 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 1030 xpq_queue_pte_update( 1031 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 1032 xpmap_ptom_masked(addr) | PG_k | PG_V); 1033 xpq_flush_queue(); 1034 } 1035 #elif defined(__x86_64__) 1036 if (final) { 1037 /* save the address of the real per-cpu L4 pgd page */ 1038 cpu_info_primary.ci_kpm_pdir = bt_cpu_pgd; 1039 cpu_info_primary.ci_kpm_pdirpa = ((paddr_t) bt_cpu_pgd - KERNBASE); 1040 } 1041 #endif 1042 1043 /* Now we can safely reclaim space taken by old tables */ 1044 1045 __PRINTK(("unpin old PGD\n")); 1046 /* Unpin old PGD */ 1047 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 1048 /* Mark old tables RW */ 1049 page = old_pgd; 1050 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 1051 addr = xpmap_mtop(addr); 1052 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 1053 pte += pl1_pi(page); 1054 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 1055 pde[pl2_pi(page)], addr, (long)pte)); 1056 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 1057 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 1058 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 1059 "*pte %#" PRIxPADDR "\n", 1060 addr, (long)pte, *pte)); 1061 xpq_queue_pte_update(addr, *pte | PG_RW); 1062 page += PAGE_SIZE; 1063 /* 1064 * Our ptes are contiguous 1065 * so it's safe to just "++" here 1066 */ 1067 pte++; 1068 } 1069 xpq_flush_queue(); 1070 xpq_queue_unlock(); 1071 } 1072 1073 1074 /* 1075 * Bootstrap helper functions 1076 */ 1077 1078 /* 1079 * Mark a page readonly 1080 * XXX: assuming vaddr = paddr + KERNBASE 1081 */ 1082 1083 static void 1084 xen_bt_set_readonly (vaddr_t page) 1085 { 1086 pt_entry_t entry; 1087 1088 entry = xpmap_ptom_masked(page - KERNBASE); 1089 entry |= PG_k | PG_V; 1090 1091 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 1092 } 1093 1094 #ifdef __x86_64__ 1095 void 1096 xen_set_user_pgd(paddr_t page) 1097 { 1098 struct mmuext_op op; 1099 int s = splvm(); 1100 1101 KASSERT(xpq_queue_locked()); 1102 xpq_flush_queue(); 1103 op.cmd = MMUEXT_NEW_USER_BASEPTR; 1104 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 1105 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 1106 panic("xen_set_user_pgd: failed to install new user page" 1107 " directory %#" PRIxPADDR, page); 1108 splx(s); 1109 } 1110 #endif /* __x86_64__ */ 1111
Indexes created Tue Oct 21 08:09:48 GMT 2025