x86_xpmap.c revision 1.26.2.12
1 /* $NetBSD: x86_xpmap.c,v 1.26.2.12 2011/10/21 18:08:44 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.26.2.12 2011/10/21 18:08:44 bouyer Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/simplelock.h> 81 82 #include <uvm/uvm.h> 83 84 #include <machine/pmap.h> 85 #include <machine/gdt.h> 86 #include <xen/xenfunc.h> 87 88 #include <dev/isa/isareg.h> 89 #include <machine/isa_machdep.h> 90 91 #undef XENDEBUG 92 /* #define XENDEBUG_SYNC */ 93 /* #define XENDEBUG_LOW */ 94 95 #ifdef XENDEBUG 96 #define XENPRINTF(x) printf x 97 #define XENPRINTK(x) printk x 98 #define XENPRINTK2(x) /* printk x */ 99 100 static char XBUF[256]; 101 #else 102 #define XENPRINTF(x) 103 #define XENPRINTK(x) 104 #define XENPRINTK2(x) 105 #endif 106 #define PRINTF(x) printf x 107 #define PRINTK(x) printk x 108 109 /* on x86_64 kernel runs in ring 3 */ 110 #ifdef __x86_64__ 111 #define PG_k PG_u 112 #else 113 #define PG_k 0 114 #endif 115 116 volatile shared_info_t *HYPERVISOR_shared_info; 117 /* Xen requires the start_info struct to be page aligned */ 118 union start_info_union start_info_union __aligned(PAGE_SIZE); 119 unsigned long *xpmap_phys_to_machine_mapping; 120 121 void xen_failsafe_handler(void); 122 123 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 124 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 125 126 void 127 xen_failsafe_handler(void) 128 { 129 130 panic("xen_failsafe_handler called!\n"); 131 } 132 133 134 void 135 xen_set_ldt(vaddr_t base, uint32_t entries) 136 { 137 vaddr_t va; 138 vaddr_t end; 139 pt_entry_t *ptp; 140 int s; 141 142 #ifdef __x86_64__ 143 end = base + (entries << 3); 144 #else 145 end = base + entries * sizeof(union descriptor); 146 #endif 147 148 for (va = base; va < end; va += PAGE_SIZE) { 149 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 150 ptp = kvtopte(va); 151 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 152 base, entries, ptp)); 153 pmap_pte_clearbits(ptp, PG_RW); 154 } 155 s = splvm(); 156 xpq_queue_set_ldt(base, entries); 157 splx(s); 158 } 159 160 #ifdef XENDEBUG 161 void xpq_debug_dump(void); 162 #endif 163 164 #define XPQUEUE_SIZE 2048 165 static mmu_update_t xpq_queue_array[MAXCPUS][XPQUEUE_SIZE]; 166 static int xpq_idx_array[MAXCPUS]; 167 168 extern struct cpu_info * (*xpq_cpu)(void); 169 170 void 171 xpq_flush_queue(void) 172 { 173 int i, ok = 0, ret; 174 175 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 176 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 177 178 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 179 for (i = 0; i < xpq_idx; i++) 180 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 181 xpq_queue[i].ptr, xpq_queue[i].val)); 182 retry: 183 ret = HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok); 184 185 if (xpq_idx != 0 && ret < 0) { 186 printf("xpq_flush_queue: %d entries (%d successful)\n", 187 xpq_idx, ok); 188 if (ok != 0) { 189 xpq_queue += ok; 190 xpq_idx -= ok; 191 ok = 0; 192 goto retry; 193 } 194 195 for (i = 0; i < xpq_idx; i++) 196 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 197 xpq_queue[i].ptr, xpq_queue[i].val); 198 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 199 } 200 xpq_idx_array[xpq_cpu()->ci_cpuid] = 0; 201 } 202 203 static inline void 204 xpq_increment_idx(void) 205 { 206 207 if (__predict_false(++xpq_idx_array[xpq_cpu()->ci_cpuid] == XPQUEUE_SIZE)) 208 xpq_flush_queue(); 209 } 210 211 void 212 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 213 { 214 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 215 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 216 217 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 218 "\n", (int64_t)ma, (int64_t)pa)); 219 220 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 221 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 222 xpq_increment_idx(); 223 #ifdef XENDEBUG_SYNC 224 xpq_flush_queue(); 225 #endif 226 } 227 228 void 229 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 230 { 231 232 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 233 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 234 235 KASSERT((ptr & 3) == 0); 236 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 237 xpq_queue[xpq_idx].val = val; 238 xpq_increment_idx(); 239 #ifdef XENDEBUG_SYNC 240 xpq_flush_queue(); 241 #endif 242 } 243 244 void 245 xpq_queue_pt_switch(paddr_t pa) 246 { 247 struct mmuext_op op; 248 xpq_flush_queue(); 249 250 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 251 (int64_t)pa, (int64_t)pa)); 252 op.cmd = MMUEXT_NEW_BASEPTR; 253 op.arg1.mfn = pa >> PAGE_SHIFT; 254 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 255 panic("xpq_queue_pt_switch"); 256 } 257 258 void 259 xpq_queue_pin_table(paddr_t pa, int lvl) 260 { 261 struct mmuext_op op; 262 263 xpq_flush_queue(); 264 265 XENPRINTK2(("xpq_queue_pin_l%d_table: %#" PRIxPADDR "\n", 266 lvl + 1, pa)); 267 268 op.arg1.mfn = pa >> PAGE_SHIFT; 269 op.cmd = lvl; 270 271 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 272 panic("xpq_queue_pin_table"); 273 } 274 275 void 276 xpq_queue_unpin_table(paddr_t pa) 277 { 278 struct mmuext_op op; 279 280 xpq_flush_queue(); 281 282 XENPRINTK2(("xpq_queue_unpin_table: %#" PRIxPADDR "\n", pa)); 283 op.arg1.mfn = pa >> PAGE_SHIFT; 284 op.cmd = MMUEXT_UNPIN_TABLE; 285 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 286 panic("xpq_queue_unpin_table"); 287 } 288 289 void 290 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 291 { 292 struct mmuext_op op; 293 294 xpq_flush_queue(); 295 296 XENPRINTK2(("xpq_queue_set_ldt\n")); 297 KASSERT(va == (va & ~PAGE_MASK)); 298 op.cmd = MMUEXT_SET_LDT; 299 op.arg1.linear_addr = va; 300 op.arg2.nr_ents = entries; 301 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 302 panic("xpq_queue_set_ldt"); 303 } 304 305 void 306 xpq_queue_tlb_flush(void) 307 { 308 struct mmuext_op op; 309 310 xpq_flush_queue(); 311 312 XENPRINTK2(("xpq_queue_tlb_flush\n")); 313 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 314 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 315 panic("xpq_queue_tlb_flush"); 316 } 317 318 void 319 xpq_flush_cache(void) 320 { 321 struct mmuext_op op; 322 int s = splvm(), err; 323 324 xpq_flush_queue(); 325 XENPRINTK2(("xpq_queue_flush_cache\n")); 326 op.cmd = MMUEXT_FLUSH_CACHE; 327 if ((err = HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF)) < 0) 328 printf("errno == %d\n", err); 329 panic("xpq_flush_cache"); 330 splx(s); /* XXX: removeme */ 331 } 332 333 void 334 xpq_queue_invlpg(vaddr_t va) 335 { 336 struct mmuext_op op; 337 338 xpq_flush_queue(); 339 340 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 341 op.cmd = MMUEXT_INVLPG_LOCAL; 342 op.arg1.linear_addr = (va & ~PAGE_MASK); 343 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 344 panic("xpq_queue_invlpg"); 345 } 346 347 void 348 xen_mcast_invlpg(vaddr_t va, uint32_t cpumask) 349 { 350 mmuext_op_t op; 351 352 /* Flush pending page updates */ 353 xpq_flush_queue(); 354 355 op.cmd = MMUEXT_INVLPG_MULTI; 356 op.arg1.linear_addr = va; 357 op.arg2.vcpumask = &cpumask; 358 359 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 360 panic("xpq_queue_invlpg_all"); 361 } 362 363 return; 364 } 365 366 void 367 xen_bcast_invlpg(vaddr_t va) 368 { 369 mmuext_op_t op; 370 371 /* Flush pending page updates */ 372 xpq_flush_queue(); 373 374 op.cmd = MMUEXT_INVLPG_ALL; 375 op.arg1.linear_addr = va; 376 377 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 378 panic("xpq_queue_invlpg_all"); 379 } 380 381 return; 382 } 383 384 /* This is a synchronous call. */ 385 void 386 xen_mcast_tlbflush(uint32_t cpumask) 387 { 388 mmuext_op_t op; 389 390 /* Flush pending page updates */ 391 xpq_flush_queue(); 392 393 op.cmd = MMUEXT_TLB_FLUSH_MULTI; 394 op.arg2.vcpumask = &cpumask; 395 396 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 397 panic("xpq_queue_invlpg_all"); 398 } 399 400 return; 401 } 402 403 /* This is a synchronous call. */ 404 void 405 xen_bcast_tlbflush(void) 406 { 407 mmuext_op_t op; 408 409 /* Flush pending page updates */ 410 xpq_flush_queue(); 411 412 op.cmd = MMUEXT_TLB_FLUSH_ALL; 413 414 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 415 panic("xpq_queue_invlpg_all"); 416 } 417 418 return; 419 } 420 421 /* This is a synchronous call. */ 422 void 423 xen_vcpu_mcast_invlpg(vaddr_t sva, vaddr_t eva, uint32_t cpumask) 424 { 425 KASSERT(eva > sva); 426 427 /* Flush pending page updates */ 428 xpq_flush_queue(); 429 430 /* Align to nearest page boundary */ 431 sva &= ~PAGE_MASK; 432 eva &= ~PAGE_MASK; 433 434 for ( ; sva <= eva; sva += PAGE_SIZE) { 435 xen_mcast_invlpg(sva, cpumask); 436 } 437 438 return; 439 } 440 441 /* This is a synchronous call. */ 442 void 443 xen_vcpu_bcast_invlpg(vaddr_t sva, vaddr_t eva) 444 { 445 KASSERT(eva > sva); 446 447 /* Flush pending page updates */ 448 xpq_flush_queue(); 449 450 /* Align to nearest page boundary */ 451 sva &= ~PAGE_MASK; 452 eva &= ~PAGE_MASK; 453 454 for ( ; sva <= eva; sva += PAGE_SIZE) { 455 xen_bcast_invlpg(sva); 456 } 457 458 return; 459 } 460 461 int 462 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 463 { 464 mmu_update_t op; 465 int ok; 466 467 xpq_flush_queue(); 468 469 op.ptr = ptr; 470 op.val = val; 471 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 472 return EFAULT; 473 return (0); 474 } 475 476 #ifdef XENDEBUG 477 void 478 xpq_debug_dump(void) 479 { 480 int i; 481 482 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 483 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 484 485 XENPRINTK2(("idx: %d\n", xpq_idx)); 486 for (i = 0; i < xpq_idx; i++) { 487 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 488 xpq_queue[i].ptr, xpq_queue[i].val); 489 if (++i < xpq_idx) 490 snprintf(XBUF + strlen(XBUF), 491 sizeof(XBUF) - strlen(XBUF), 492 "%" PRIx64 " %08" PRIx64, 493 xpq_queue[i].ptr, xpq_queue[i].val); 494 if (++i < xpq_idx) 495 snprintf(XBUF + strlen(XBUF), 496 sizeof(XBUF) - strlen(XBUF), 497 "%" PRIx64 " %08" PRIx64, 498 xpq_queue[i].ptr, xpq_queue[i].val); 499 if (++i < xpq_idx) 500 snprintf(XBUF + strlen(XBUF), 501 sizeof(XBUF) - strlen(XBUF), 502 "%" PRIx64 " %08" PRIx64, 503 xpq_queue[i].ptr, xpq_queue[i].val); 504 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 505 } 506 } 507 #endif 508 509 510 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 511 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 512 513 static void xen_bt_set_readonly (vaddr_t); 514 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 515 516 /* How many PDEs ? */ 517 #if L2_SLOT_KERNBASE > 0 518 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 519 #else 520 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 521 #endif 522 523 /* 524 * Construct and switch to new pagetables 525 * first_avail is the first vaddr we can use after 526 * we get rid of Xen pagetables 527 */ 528 529 vaddr_t xen_pmap_bootstrap (void); 530 531 /* 532 * Function to get rid of Xen bootstrap tables 533 */ 534 535 /* How many PDP do we need: */ 536 #ifdef PAE 537 /* 538 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 539 * all of them mapped by the L3 page. We also need a shadow page 540 * for L3[3]. 541 */ 542 static const int l2_4_count = 6; 543 #elif defined(__x86_64__) 544 static const int l2_4_count = PTP_LEVELS; 545 #else 546 static const int l2_4_count = PTP_LEVELS - 1; 547 #endif 548 549 vaddr_t 550 xen_pmap_bootstrap(void) 551 { 552 int count, oldcount; 553 long mapsize; 554 vaddr_t bootstrap_tables, init_tables; 555 556 memset(xpq_idx_array, 0, sizeof xpq_idx_array); 557 558 xpmap_phys_to_machine_mapping = 559 (unsigned long *)xen_start_info.mfn_list; 560 init_tables = xen_start_info.pt_base; 561 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 562 563 /* Space after Xen boostrap tables should be free */ 564 bootstrap_tables = xen_start_info.pt_base + 565 (xen_start_info.nr_pt_frames * PAGE_SIZE); 566 567 /* 568 * Calculate how many space we need 569 * first everything mapped before the Xen bootstrap tables 570 */ 571 mapsize = init_tables - KERNTEXTOFF; 572 /* after the tables we'll have: 573 * - UAREA 574 * - dummy user PGD (x86_64) 575 * - HYPERVISOR_shared_info 576 * - ISA I/O mem (if needed) 577 */ 578 mapsize += UPAGES * NBPG; 579 #ifdef __x86_64__ 580 mapsize += NBPG; 581 #endif 582 mapsize += NBPG; 583 584 #ifdef DOM0OPS 585 if (xendomain_is_dom0()) { 586 /* space for ISA I/O mem */ 587 mapsize += IOM_SIZE; 588 } 589 #endif 590 /* at this point mapsize doens't include the table size */ 591 592 #ifdef __x86_64__ 593 count = TABLE_L2_ENTRIES; 594 #else 595 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 596 #endif /* __x86_64__ */ 597 598 /* now compute how many L2 pages we need exactly */ 599 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 600 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 601 ((long)count << L2_SHIFT) + KERNBASE) { 602 count++; 603 } 604 #ifndef __x86_64__ 605 /* 606 * one more L2 page: we'll alocate several pages after kva_start 607 * in pmap_bootstrap() before pmap_growkernel(), which have not been 608 * counted here. It's not a big issue to allocate one more L2 as 609 * pmap_growkernel() will be called anyway. 610 */ 611 count++; 612 nkptp[1] = count; 613 #endif 614 615 /* 616 * install bootstrap pages. We may need more L2 pages than will 617 * have the final table here, as it's installed after the final table 618 */ 619 oldcount = count; 620 621 bootstrap_again: 622 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 623 /* 624 * Xen space we'll reclaim may not be enough for our new page tables, 625 * move bootstrap tables if necessary 626 */ 627 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 628 bootstrap_tables = init_tables + 629 ((count + l2_4_count) * PAGE_SIZE); 630 /* make sure we have enough to map the bootstrap_tables */ 631 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 632 ((long)oldcount << L2_SHIFT) + KERNBASE) { 633 oldcount++; 634 goto bootstrap_again; 635 } 636 637 /* Create temporary tables */ 638 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 639 xen_start_info.nr_pt_frames, oldcount, 0); 640 641 /* Create final tables */ 642 xen_bootstrap_tables(bootstrap_tables, init_tables, 643 oldcount + l2_4_count, count, 1); 644 645 /* zero out free space after tables */ 646 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 647 (UPAGES + 1) * NBPG); 648 649 /* Finally, flush TLB. */ 650 xpq_queue_tlb_flush(); 651 652 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 653 } 654 655 /* 656 * Build a new table and switch to it 657 * old_count is # of old tables (including PGD, PDTPE and PDE) 658 * new_count is # of new tables (PTE only) 659 * we assume areas don't overlap 660 */ 661 static void 662 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 663 int old_count, int new_count, int final) 664 { 665 pd_entry_t *pdtpe, *pde, *pte; 666 pd_entry_t *cur_pgd, *bt_pgd; 667 paddr_t addr; 668 vaddr_t page, avail, text_end, map_end; 669 int i; 670 extern char __data_start; 671 672 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 673 " %d, %d)\n", 674 old_pgd, new_pgd, old_count, new_count)); 675 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 676 /* 677 * size of R/W area after kernel text: 678 * xencons_interface (if present) 679 * xenstore_interface (if present) 680 * table pages (new_count + l2_4_count entries) 681 * extra mappings (only when final is true): 682 * UAREA 683 * dummy user PGD (x86_64 only)/gdt page (i386 only) 684 * HYPERVISOR_shared_info 685 * ISA I/O mem (if needed) 686 */ 687 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 688 if (final) { 689 map_end += (UPAGES + 1) * NBPG; 690 HYPERVISOR_shared_info = (shared_info_t *)map_end; 691 map_end += NBPG; 692 } 693 /* 694 * we always set atdevbase, as it's used by init386 to find the first 695 * available VA. map_end is updated only if we are dom0, so 696 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 697 * this case. 698 */ 699 if (final) 700 atdevbase = map_end; 701 #ifdef DOM0OPS 702 if (final && xendomain_is_dom0()) { 703 /* ISA I/O mem */ 704 map_end += IOM_SIZE; 705 } 706 #endif /* DOM0OPS */ 707 708 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 709 text_end, map_end)); 710 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 711 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 712 713 /* 714 * Create bootstrap page tables 715 * What we need: 716 * - a PGD (level 4) 717 * - a PDTPE (level 3) 718 * - a PDE (level2) 719 * - some PTEs (level 1) 720 */ 721 722 cur_pgd = (pd_entry_t *) old_pgd; 723 bt_pgd = (pd_entry_t *) new_pgd; 724 memset (bt_pgd, 0, PAGE_SIZE); 725 avail = new_pgd + PAGE_SIZE; 726 #if PTP_LEVELS > 3 727 /* per-cpu L4 PD */ 728 pd_entry_t *bt_cpu_pgd = bt_pgd; 729 /* pmap_kernel() "shadow" L4 PD */ 730 bt_pgd = (pd_entry_t *) avail; 731 memset(bt_pgd, 0, PAGE_SIZE); 732 avail += PAGE_SIZE; 733 734 /* Install level 3 */ 735 pdtpe = (pd_entry_t *) avail; 736 memset (pdtpe, 0, PAGE_SIZE); 737 avail += PAGE_SIZE; 738 739 addr = ((u_long) pdtpe) - KERNBASE; 740 bt_pgd[pl4_pi(KERNTEXTOFF)] = bt_cpu_pgd[pl4_pi(KERNTEXTOFF)] = 741 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 742 743 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 744 " -> L4[%#x]\n", 745 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 746 #else 747 pdtpe = bt_pgd; 748 #endif /* PTP_LEVELS > 3 */ 749 750 #if PTP_LEVELS > 2 751 /* Level 2 */ 752 pde = (pd_entry_t *) avail; 753 memset(pde, 0, PAGE_SIZE); 754 avail += PAGE_SIZE; 755 756 addr = ((u_long) pde) - KERNBASE; 757 pdtpe[pl3_pi(KERNTEXTOFF)] = 758 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 759 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 760 " -> L3[%#x]\n", 761 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 762 #elif defined(PAE) 763 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 764 pde = (pd_entry_t *) avail; 765 memset(pde, 0, PAGE_SIZE * 5); 766 avail += PAGE_SIZE * 5; 767 addr = ((u_long) pde) - KERNBASE; 768 /* 769 * enter L2 pages in the L3. 770 * The real L2 kernel PD will be the last one (so that 771 * pde[L2_SLOT_KERN] always point to the shadow). 772 */ 773 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 774 /* 775 * Xen doesn't want R/W mappings in L3 entries, it'll add it 776 * itself. 777 */ 778 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 779 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 780 " -> L3[%#x]\n", 781 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 782 } 783 addr += PAGE_SIZE; 784 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 785 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 786 " -> L3[%#x]\n", 787 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 788 789 #else /* PAE */ 790 pde = bt_pgd; 791 #endif /* PTP_LEVELS > 2 */ 792 793 /* Level 1 */ 794 page = KERNTEXTOFF; 795 for (i = 0; i < new_count; i ++) { 796 vaddr_t cur_page = page; 797 798 pte = (pd_entry_t *) avail; 799 avail += PAGE_SIZE; 800 801 memset(pte, 0, PAGE_SIZE); 802 while (pl2_pi(page) == pl2_pi (cur_page)) { 803 if (page >= map_end) { 804 /* not mapped at all */ 805 pte[pl1_pi(page)] = 0; 806 page += PAGE_SIZE; 807 continue; 808 } 809 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 810 if (page == (vaddr_t)HYPERVISOR_shared_info) { 811 pte[pl1_pi(page)] = xen_start_info.shared_info; 812 __PRINTK(("HYPERVISOR_shared_info " 813 "va %#lx pte %#" PRIxPADDR "\n", 814 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 815 } 816 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 817 == xen_start_info.console.domU.mfn) { 818 xencons_interface = (void *)page; 819 pte[pl1_pi(page)] = xen_start_info.console_mfn; 820 pte[pl1_pi(page)] <<= PAGE_SHIFT; 821 __PRINTK(("xencons_interface " 822 "va %#lx pte %#" PRIxPADDR "\n", 823 xencons_interface, pte[pl1_pi(page)])); 824 } 825 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 826 == xen_start_info.store_mfn) { 827 xenstore_interface = (void *)page; 828 pte[pl1_pi(page)] = xen_start_info.store_mfn; 829 pte[pl1_pi(page)] <<= PAGE_SHIFT; 830 __PRINTK(("xenstore_interface " 831 "va %#lx pte %#" PRIxPADDR "\n", 832 xenstore_interface, pte[pl1_pi(page)])); 833 } 834 #ifdef DOM0OPS 835 if (page >= (vaddr_t)atdevbase && 836 page < (vaddr_t)atdevbase + IOM_SIZE) { 837 pte[pl1_pi(page)] = 838 IOM_BEGIN + (page - (vaddr_t)atdevbase); 839 } 840 #endif 841 pte[pl1_pi(page)] |= PG_k | PG_V; 842 if (page < text_end) { 843 /* map kernel text RO */ 844 pte[pl1_pi(page)] |= 0; 845 } else if (page >= old_pgd 846 && page < old_pgd + (old_count * PAGE_SIZE)) { 847 /* map old page tables RO */ 848 pte[pl1_pi(page)] |= 0; 849 } else if (page >= new_pgd && 850 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 851 /* map new page tables RO */ 852 pte[pl1_pi(page)] |= 0; 853 } else { 854 /* map page RW */ 855 pte[pl1_pi(page)] |= PG_RW; 856 } 857 858 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 859 || page >= new_pgd) { 860 __PRINTK(("va %#lx pa %#lx " 861 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 862 page, page - KERNBASE, 863 pte[pl1_pi(page)], pl1_pi(page))); 864 } 865 page += PAGE_SIZE; 866 } 867 868 addr = ((u_long) pte) - KERNBASE; 869 pde[pl2_pi(cur_page)] = 870 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 871 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 872 " -> L2[%#x]\n", 873 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 874 /* Mark readonly */ 875 xen_bt_set_readonly((vaddr_t) pte); 876 } 877 878 /* Install recursive page tables mapping */ 879 #ifdef PAE 880 /* 881 * we need a shadow page for the kernel's L2 page 882 * The real L2 kernel PD will be the last one (so that 883 * pde[L2_SLOT_KERN] always point to the shadow. 884 */ 885 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 886 cpu_info_primary.ci_kpm_pdir = &pde[L2_SLOT_KERN + NPDPG]; 887 cpu_info_primary.ci_kpm_pdirpa = 888 (vaddr_t) cpu_info_primary.ci_kpm_pdir - KERNBASE; 889 890 /* 891 * We don't enter a recursive entry from the L3 PD. Instead, 892 * we enter the first 4 L2 pages, which includes the kernel's L2 893 * shadow. But we have to entrer the shadow after switching 894 * %cr3, or Xen will refcount some PTE with the wrong type. 895 */ 896 addr = (u_long)pde - KERNBASE; 897 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 898 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 899 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 900 " entry %#" PRIxPADDR "\n", 901 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 902 addr, pde[PDIR_SLOT_PTE + i])); 903 } 904 #if 0 905 addr += PAGE_SIZE; /* point to shadow L2 */ 906 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 907 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 908 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 909 (int64_t)pde[PDIR_SLOT_PTE + 3])); 910 #endif 911 /* Mark tables RO, and pin the kernel's shadow as L2 */ 912 addr = (u_long)pde - KERNBASE; 913 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 914 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 915 if (i == 2 || i == 3) 916 continue; 917 #if 0 918 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 919 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 920 #endif 921 } 922 if (final) { 923 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 924 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 925 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 926 } 927 #if 0 928 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 929 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 930 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 931 #endif 932 #else /* PAE */ 933 /* recursive entry in higher-level per-cpu PD and pmap_kernel() */ 934 bt_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_pgd - KERNBASE) | PG_k | PG_V; 935 #ifdef __x86_64__ 936 bt_cpu_pgd[PDIR_SLOT_PTE] = 937 xpmap_ptom_masked((paddr_t)bt_cpu_pgd - KERNBASE) | PG_k | PG_V; 938 #endif /* __x86_64__ */ 939 __PRINTK(("bt_cpu_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 940 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 941 bt_pgd[PDIR_SLOT_PTE])); 942 943 944 /* Mark tables RO */ 945 xen_bt_set_readonly((vaddr_t) pde); 946 #endif 947 #if PTP_LEVELS > 2 || defined(PAE) 948 xen_bt_set_readonly((vaddr_t) pdtpe); 949 #endif 950 #if PTP_LEVELS > 3 951 xen_bt_set_readonly(new_pgd); 952 #endif 953 /* Pin the PGD */ 954 __PRINTK(("pin PGD: %"PRIxVADDR"\n", new_pgd - KERNBASE)); 955 #ifdef __x86_64__ 956 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 957 #elif PAE 958 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 959 #else 960 xpq_queue_pin_l2_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 961 #endif 962 /* Save phys. addr of PDP, for libkvm. */ 963 #ifdef PAE 964 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 965 #else 966 PDPpaddr = (u_long)bt_pgd - KERNBASE; 967 #endif 968 969 /* Switch to new tables */ 970 __PRINTK(("switch to PGD\n")); 971 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 972 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 973 bt_pgd[PDIR_SLOT_PTE])); 974 975 #ifdef PAE 976 if (final) { 977 /* save the address of the L3 page */ 978 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 979 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 980 981 /* now enter kernel's PTE mappings */ 982 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 983 xpq_queue_pte_update( 984 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 985 xpmap_ptom_masked(addr) | PG_k | PG_V); 986 xpq_flush_queue(); 987 } 988 #elif defined(__x86_64__) 989 if (final) { 990 /* save the address of the real per-cpu L4 pgd page */ 991 cpu_info_primary.ci_kpm_pdir = bt_cpu_pgd; 992 cpu_info_primary.ci_kpm_pdirpa = ((paddr_t) bt_cpu_pgd - KERNBASE); 993 } 994 #endif 995 996 /* Now we can safely reclaim space taken by old tables */ 997 998 __PRINTK(("unpin old PGD\n")); 999 /* Unpin old PGD */ 1000 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 1001 /* Mark old tables RW */ 1002 page = old_pgd; 1003 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 1004 addr = xpmap_mtop(addr); 1005 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 1006 pte += pl1_pi(page); 1007 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 1008 pde[pl2_pi(page)], addr, (long)pte)); 1009 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 1010 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 1011 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 1012 "*pte %#" PRIxPADDR "\n", 1013 addr, (long)pte, *pte)); 1014 xpq_queue_pte_update(addr, *pte | PG_RW); 1015 page += PAGE_SIZE; 1016 /* 1017 * Our ptes are contiguous 1018 * so it's safe to just "++" here 1019 */ 1020 pte++; 1021 } 1022 xpq_flush_queue(); 1023 1024 } 1025 1026 1027 /* 1028 * Bootstrap helper functions 1029 */ 1030 1031 /* 1032 * Mark a page readonly 1033 * XXX: assuming vaddr = paddr + KERNBASE 1034 */ 1035 1036 static void 1037 xen_bt_set_readonly (vaddr_t page) 1038 { 1039 pt_entry_t entry; 1040 1041 entry = xpmap_ptom_masked(page - KERNBASE); 1042 entry |= PG_k | PG_V; 1043 1044 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 1045 } 1046 1047 #ifdef __x86_64__ 1048 void 1049 xen_set_user_pgd(paddr_t page) 1050 { 1051 struct mmuext_op op; 1052 int s = splvm(); 1053 1054 xpq_flush_queue(); 1055 op.cmd = MMUEXT_NEW_USER_BASEPTR; 1056 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 1057 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 1058 panic("xen_set_user_pgd: failed to install new user page" 1059 " directory %#" PRIxPADDR, page); 1060 splx(s); 1061 } 1062 #endif /* __x86_64__ */ 1063
Indexes created Wed Oct 22 13:09:56 GMT 2025