x86_xpmap.c revision 1.26.2.8
1 /* $NetBSD: x86_xpmap.c,v 1.26.2.8 2011/08/30 12:53:46 cherry Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.26.2.8 2011/08/30 12:53:46 cherry Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/simplelock.h> 81 82 #include <uvm/uvm.h> 83 84 #include <machine/pmap.h> 85 #include <machine/gdt.h> 86 #include <xen/xenfunc.h> 87 88 #include <dev/isa/isareg.h> 89 #include <machine/isa_machdep.h> 90 91 #undef XENDEBUG 92 /* #define XENDEBUG_SYNC */ 93 /* #define XENDEBUG_LOW */ 94 95 #ifdef XENDEBUG 96 #define XENPRINTF(x) printf x 97 #define XENPRINTK(x) printk x 98 #define XENPRINTK2(x) /* printk x */ 99 100 static char XBUF[256]; 101 #else 102 #define XENPRINTF(x) 103 #define XENPRINTK(x) 104 #define XENPRINTK2(x) 105 #endif 106 #define PRINTF(x) printf x 107 #define PRINTK(x) printk x 108 109 /* on x86_64 kernel runs in ring 3 */ 110 #ifdef __x86_64__ 111 #define PG_k PG_u 112 #else 113 #define PG_k 0 114 #endif 115 116 volatile shared_info_t *HYPERVISOR_shared_info; 117 /* Xen requires the start_info struct to be page aligned */ 118 union start_info_union start_info_union __aligned(PAGE_SIZE); 119 unsigned long *xpmap_phys_to_machine_mapping; 120 121 void xen_failsafe_handler(void); 122 123 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 124 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 125 126 void 127 xen_failsafe_handler(void) 128 { 129 130 panic("xen_failsafe_handler called!\n"); 131 } 132 133 134 void 135 xen_set_ldt(vaddr_t base, uint32_t entries) 136 { 137 vaddr_t va; 138 vaddr_t end; 139 pt_entry_t *ptp; 140 int s; 141 142 #ifdef __x86_64__ 143 end = base + (entries << 3); 144 #else 145 end = base + entries * sizeof(union descriptor); 146 #endif 147 148 for (va = base; va < end; va += PAGE_SIZE) { 149 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 150 ptp = kvtopte(va); 151 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 152 base, entries, ptp)); 153 pmap_pte_clearbits(ptp, PG_RW); 154 } 155 s = splvm(); 156 xpq_queue_lock(); 157 xpq_queue_set_ldt(base, entries); 158 xpq_queue_unlock(); 159 splx(s); 160 } 161 162 #ifdef XENDEBUG 163 void xpq_debug_dump(void); 164 #endif 165 166 #define XPQUEUE_SIZE 2048 167 static mmu_update_t xpq_queue_array[MAXCPUS][XPQUEUE_SIZE]; 168 static int xpq_idx_array[MAXCPUS]; 169 170 #ifdef MULTIPROCESSOR 171 static struct simplelock xpq_lock = SIMPLELOCK_INITIALIZER; 172 173 extern struct cpu_info * (*xpq_cpu)(void); 174 175 void 176 xpq_queue_lock(void) 177 { 178 simple_lock(&xpq_lock); 179 } 180 181 void 182 xpq_queue_unlock(void) 183 { 184 simple_unlock(&xpq_lock); 185 } 186 187 bool 188 xpq_queue_locked(void) 189 { 190 return simple_lock_held(&xpq_lock); 191 } 192 #endif /* MULTIPROCESSOR */ 193 194 /* Must be called with xpq_lock held */ 195 void 196 xpq_flush_queue(void) 197 { 198 int i, ok, ret; 199 200 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 201 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 202 203 KASSERT(xpq_queue_locked()); 204 205 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 206 for (i = 0; i < xpq_idx; i++) 207 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 208 xpq_queue[i].ptr, xpq_queue[i].val)); 209 210 ret = HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok); 211 212 if (xpq_idx != 0 && ret < 0) { 213 printf("xpq_flush_queue: %d entries (%d successful)\n", 214 xpq_idx, ok); 215 for (i = 0; i < xpq_idx; i++) 216 printf("0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 217 xpq_queue[i].ptr, xpq_queue[i].val); 218 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 219 } 220 xpq_idx_array[xpq_cpu()->ci_cpuid] = 0; 221 } 222 223 /* Must be called with xpq_lock held */ 224 static inline void 225 xpq_increment_idx(void) 226 { 227 228 KASSERT(xpq_queue_locked()); 229 230 if (__predict_false(++xpq_idx_array[xpq_cpu()->ci_cpuid] == XPQUEUE_SIZE)) 231 xpq_flush_queue(); 232 } 233 234 void 235 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 236 { 237 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 238 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 239 240 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 241 "\n", (int64_t)ma, (int64_t)pa)); 242 KASSERT(xpq_queue_locked()); 243 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 244 xpq_queue[xpq_idx].val = (pa - XPMAP_OFFSET) >> PAGE_SHIFT; 245 xpq_increment_idx(); 246 #ifdef XENDEBUG_SYNC 247 xpq_flush_queue(); 248 #endif 249 } 250 251 void 252 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 253 { 254 255 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 256 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 257 258 KASSERT((ptr & 3) == 0); 259 KASSERT(xpq_queue_locked()); 260 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 261 xpq_queue[xpq_idx].val = val; 262 xpq_increment_idx(); 263 #ifdef XENDEBUG_SYNC 264 xpq_flush_queue(); 265 #endif 266 } 267 268 void 269 xpq_queue_pt_switch(paddr_t pa) 270 { 271 struct mmuext_op op; 272 KASSERT(xpq_queue_locked()); 273 xpq_flush_queue(); 274 275 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 276 (int64_t)pa, (int64_t)pa)); 277 op.cmd = MMUEXT_NEW_BASEPTR; 278 op.arg1.mfn = pa >> PAGE_SHIFT; 279 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 280 panic("xpq_queue_pt_switch"); 281 } 282 283 void 284 xpq_queue_pin_table(paddr_t pa, int lvl) 285 { 286 struct mmuext_op op; 287 288 KASSERT(xpq_queue_locked()); 289 xpq_flush_queue(); 290 291 XENPRINTK2(("xpq_queue_pin_l%d_table: %#" PRIxPADDR "\n", 292 lvl + 1, pa)); 293 294 op.arg1.mfn = pa >> PAGE_SHIFT; 295 op.cmd = lvl; 296 297 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 298 panic("xpq_queue_pin_table"); 299 } 300 301 void 302 xpq_queue_unpin_table(paddr_t pa) 303 { 304 struct mmuext_op op; 305 306 KASSERT(xpq_queue_locked()); 307 xpq_flush_queue(); 308 309 XENPRINTK2(("xpq_queue_unpin_table: %#" PRIxPADDR "\n", pa)); 310 op.arg1.mfn = pa >> PAGE_SHIFT; 311 op.cmd = MMUEXT_UNPIN_TABLE; 312 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 313 panic("xpq_queue_unpin_table"); 314 } 315 316 void 317 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 318 { 319 struct mmuext_op op; 320 321 KASSERT(xpq_queue_locked()); 322 xpq_flush_queue(); 323 324 XENPRINTK2(("xpq_queue_set_ldt\n")); 325 KASSERT(va == (va & ~PAGE_MASK)); 326 op.cmd = MMUEXT_SET_LDT; 327 op.arg1.linear_addr = va; 328 op.arg2.nr_ents = entries; 329 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 330 panic("xpq_queue_set_ldt"); 331 } 332 333 void 334 xpq_queue_tlb_flush(void) 335 { 336 struct mmuext_op op; 337 338 KASSERT(xpq_queue_locked()); 339 xpq_flush_queue(); 340 341 XENPRINTK2(("xpq_queue_tlb_flush\n")); 342 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 343 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 344 panic("xpq_queue_tlb_flush"); 345 } 346 347 void 348 xpq_flush_cache(void) 349 { 350 struct mmuext_op op; 351 int s = splvm(), err; 352 353 xpq_queue_lock(); 354 xpq_flush_queue(); 355 356 XENPRINTK2(("xpq_queue_flush_cache\n")); 357 op.cmd = MMUEXT_FLUSH_CACHE; 358 if ((err = HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF)) < 0) 359 printf("errno == %d\n", err); 360 panic("xpq_flush_cache"); 361 xpq_queue_unlock(); 362 splx(s); /* XXX: removeme */ 363 } 364 365 void 366 xpq_queue_invlpg(vaddr_t va) 367 { 368 struct mmuext_op op; 369 KASSERT(xpq_queue_locked()); 370 xpq_flush_queue(); 371 372 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 373 op.cmd = MMUEXT_INVLPG_LOCAL; 374 op.arg1.linear_addr = (va & ~PAGE_MASK); 375 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 376 panic("xpq_queue_invlpg"); 377 } 378 379 void 380 xen_mcast_invlpg(vaddr_t va, uint32_t cpumask) 381 { 382 mmuext_op_t op; 383 384 KASSERT(xpq_queue_locked()); 385 386 /* Flush pending page updates */ 387 xpq_flush_queue(); 388 389 op.cmd = MMUEXT_INVLPG_MULTI; 390 op.arg1.linear_addr = va; 391 op.arg2.vcpumask = &cpumask; 392 393 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 394 panic("xpq_queue_invlpg_all"); 395 } 396 397 return; 398 } 399 400 void 401 xen_bcast_invlpg(vaddr_t va) 402 { 403 mmuext_op_t op; 404 405 /* Flush pending page updates */ 406 KASSERT(xpq_queue_locked()); 407 xpq_flush_queue(); 408 409 op.cmd = MMUEXT_INVLPG_ALL; 410 op.arg1.linear_addr = va; 411 412 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 413 panic("xpq_queue_invlpg_all"); 414 } 415 416 return; 417 } 418 419 /* This is a synchronous call. */ 420 void 421 xen_mcast_tlbflush(uint32_t cpumask) 422 { 423 mmuext_op_t op; 424 425 /* Flush pending page updates */ 426 KASSERT(xpq_queue_locked()); 427 xpq_flush_queue(); 428 429 op.cmd = MMUEXT_TLB_FLUSH_MULTI; 430 op.arg2.vcpumask = &cpumask; 431 432 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 433 panic("xpq_queue_invlpg_all"); 434 } 435 436 return; 437 } 438 439 /* This is a synchronous call. */ 440 void 441 xen_bcast_tlbflush(void) 442 { 443 mmuext_op_t op; 444 445 /* Flush pending page updates */ 446 KASSERT(xpq_queue_locked()); 447 xpq_flush_queue(); 448 449 op.cmd = MMUEXT_TLB_FLUSH_ALL; 450 451 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 452 panic("xpq_queue_invlpg_all"); 453 } 454 455 return; 456 } 457 458 /* This is a synchronous call. */ 459 void 460 xen_vcpu_mcast_invlpg(vaddr_t sva, vaddr_t eva, uint32_t cpumask) 461 { 462 KASSERT(eva > sva); 463 464 /* Flush pending page updates */ 465 KASSERT(xpq_queue_locked()); 466 xpq_flush_queue(); 467 468 /* Align to nearest page boundary */ 469 sva &= ~PAGE_MASK; 470 eva &= ~PAGE_MASK; 471 472 for ( ; sva <= eva; sva += PAGE_SIZE) { 473 xen_mcast_invlpg(sva, cpumask); 474 } 475 476 return; 477 } 478 479 /* This is a synchronous call. */ 480 void 481 xen_vcpu_bcast_invlpg(vaddr_t sva, vaddr_t eva) 482 { 483 KASSERT(eva > sva); 484 485 /* Flush pending page updates */ 486 KASSERT(xpq_queue_locked()); 487 xpq_flush_queue(); 488 489 /* Align to nearest page boundary */ 490 sva &= ~PAGE_MASK; 491 eva &= ~PAGE_MASK; 492 493 for ( ; sva <= eva; sva += PAGE_SIZE) { 494 xen_bcast_invlpg(sva); 495 } 496 497 return; 498 } 499 500 int 501 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 502 { 503 mmu_update_t op; 504 int ok; 505 506 KASSERT(xpq_queue_locked()); 507 xpq_flush_queue(); 508 509 op.ptr = ptr; 510 op.val = val; 511 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 512 return EFAULT; 513 return (0); 514 } 515 516 #ifdef XENDEBUG 517 void 518 xpq_debug_dump(void) 519 { 520 int i; 521 522 mmu_update_t *xpq_queue = xpq_queue_array[xpq_cpu()->ci_cpuid]; 523 int xpq_idx = xpq_idx_array[xpq_cpu()->ci_cpuid]; 524 525 XENPRINTK2(("idx: %d\n", xpq_idx)); 526 for (i = 0; i < xpq_idx; i++) { 527 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 528 xpq_queue[i].ptr, xpq_queue[i].val); 529 if (++i < xpq_idx) 530 snprintf(XBUF + strlen(XBUF), 531 sizeof(XBUF) - strlen(XBUF), 532 "%" PRIx64 " %08" PRIx64, 533 xpq_queue[i].ptr, xpq_queue[i].val); 534 if (++i < xpq_idx) 535 snprintf(XBUF + strlen(XBUF), 536 sizeof(XBUF) - strlen(XBUF), 537 "%" PRIx64 " %08" PRIx64, 538 xpq_queue[i].ptr, xpq_queue[i].val); 539 if (++i < xpq_idx) 540 snprintf(XBUF + strlen(XBUF), 541 sizeof(XBUF) - strlen(XBUF), 542 "%" PRIx64 " %08" PRIx64, 543 xpq_queue[i].ptr, xpq_queue[i].val); 544 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 545 } 546 } 547 #endif 548 549 550 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 551 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 552 553 static void xen_bt_set_readonly (vaddr_t); 554 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 555 556 /* How many PDEs ? */ 557 #if L2_SLOT_KERNBASE > 0 558 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 559 #else 560 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 561 #endif 562 563 /* 564 * Construct and switch to new pagetables 565 * first_avail is the first vaddr we can use after 566 * we get rid of Xen pagetables 567 */ 568 569 vaddr_t xen_pmap_bootstrap (void); 570 571 /* 572 * Function to get rid of Xen bootstrap tables 573 */ 574 575 /* How many PDP do we need: */ 576 #ifdef PAE 577 /* 578 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 579 * all of them mapped by the L3 page. We also need a shadow page 580 * for L3[3]. 581 */ 582 static const int l2_4_count = 6; 583 #elif defined(__x86_64__) 584 static const int l2_4_count = PTP_LEVELS; 585 #else 586 static const int l2_4_count = PTP_LEVELS - 1; 587 #endif 588 589 vaddr_t 590 xen_pmap_bootstrap(void) 591 { 592 int count, oldcount; 593 long mapsize; 594 vaddr_t bootstrap_tables, init_tables; 595 596 memset(xpq_idx_array, 0, sizeof xpq_idx_array); 597 598 xpmap_phys_to_machine_mapping = 599 (unsigned long *)xen_start_info.mfn_list; 600 init_tables = xen_start_info.pt_base; 601 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 602 603 /* Space after Xen boostrap tables should be free */ 604 bootstrap_tables = xen_start_info.pt_base + 605 (xen_start_info.nr_pt_frames * PAGE_SIZE); 606 607 /* 608 * Calculate how many space we need 609 * first everything mapped before the Xen bootstrap tables 610 */ 611 mapsize = init_tables - KERNTEXTOFF; 612 /* after the tables we'll have: 613 * - UAREA 614 * - dummy user PGD (x86_64) 615 * - HYPERVISOR_shared_info 616 * - ISA I/O mem (if needed) 617 */ 618 mapsize += UPAGES * NBPG; 619 #ifdef __x86_64__ 620 mapsize += NBPG; 621 #endif 622 mapsize += NBPG; 623 624 #ifdef DOM0OPS 625 if (xendomain_is_dom0()) { 626 /* space for ISA I/O mem */ 627 mapsize += IOM_SIZE; 628 } 629 #endif 630 /* at this point mapsize doens't include the table size */ 631 632 #ifdef __x86_64__ 633 count = TABLE_L2_ENTRIES; 634 #else 635 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 636 #endif /* __x86_64__ */ 637 638 /* now compute how many L2 pages we need exactly */ 639 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 640 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 641 ((long)count << L2_SHIFT) + KERNBASE) { 642 count++; 643 } 644 #ifndef __x86_64__ 645 /* 646 * one more L2 page: we'll alocate several pages after kva_start 647 * in pmap_bootstrap() before pmap_growkernel(), which have not been 648 * counted here. It's not a big issue to allocate one more L2 as 649 * pmap_growkernel() will be called anyway. 650 */ 651 count++; 652 nkptp[1] = count; 653 #endif 654 655 /* 656 * install bootstrap pages. We may need more L2 pages than will 657 * have the final table here, as it's installed after the final table 658 */ 659 oldcount = count; 660 661 bootstrap_again: 662 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 663 /* 664 * Xen space we'll reclaim may not be enough for our new page tables, 665 * move bootstrap tables if necessary 666 */ 667 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 668 bootstrap_tables = init_tables + 669 ((count + l2_4_count) * PAGE_SIZE); 670 /* make sure we have enough to map the bootstrap_tables */ 671 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 672 ((long)oldcount << L2_SHIFT) + KERNBASE) { 673 oldcount++; 674 goto bootstrap_again; 675 } 676 677 /* Create temporary tables */ 678 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 679 xen_start_info.nr_pt_frames, oldcount, 0); 680 681 /* Create final tables */ 682 xen_bootstrap_tables(bootstrap_tables, init_tables, 683 oldcount + l2_4_count, count, 1); 684 685 /* zero out free space after tables */ 686 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 687 (UPAGES + 1) * NBPG); 688 689 /* Finally, flush TLB. */ 690 xpq_queue_lock(); 691 xpq_queue_tlb_flush(); 692 xpq_queue_unlock(); 693 694 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 695 } 696 697 /* 698 * Build a new table and switch to it 699 * old_count is # of old tables (including PGD, PDTPE and PDE) 700 * new_count is # of new tables (PTE only) 701 * we assume areas don't overlap 702 */ 703 static void 704 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 705 int old_count, int new_count, int final) 706 { 707 pd_entry_t *pdtpe, *pde, *pte; 708 pd_entry_t *cur_pgd, *bt_pgd; 709 paddr_t addr; 710 vaddr_t page, avail, text_end, map_end; 711 int i; 712 extern char __data_start; 713 714 xpq_queue_lock(); 715 716 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 717 " %d, %d)\n", 718 old_pgd, new_pgd, old_count, new_count)); 719 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 720 /* 721 * size of R/W area after kernel text: 722 * xencons_interface (if present) 723 * xenstore_interface (if present) 724 * table pages (new_count + l2_4_count entries) 725 * extra mappings (only when final is true): 726 * UAREA 727 * dummy user PGD (x86_64 only)/gdt page (i386 only) 728 * HYPERVISOR_shared_info 729 * ISA I/O mem (if needed) 730 */ 731 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 732 if (final) { 733 map_end += (UPAGES + 1) * NBPG; 734 HYPERVISOR_shared_info = (shared_info_t *)map_end; 735 map_end += NBPG; 736 } 737 /* 738 * we always set atdevbase, as it's used by init386 to find the first 739 * available VA. map_end is updated only if we are dom0, so 740 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 741 * this case. 742 */ 743 if (final) 744 atdevbase = map_end; 745 #ifdef DOM0OPS 746 if (final && xendomain_is_dom0()) { 747 /* ISA I/O mem */ 748 map_end += IOM_SIZE; 749 } 750 #endif /* DOM0OPS */ 751 752 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 753 text_end, map_end)); 754 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 755 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 756 757 /* 758 * Create bootstrap page tables 759 * What we need: 760 * - a PGD (level 4) 761 * - a PDTPE (level 3) 762 * - a PDE (level2) 763 * - some PTEs (level 1) 764 */ 765 766 cur_pgd = (pd_entry_t *) old_pgd; 767 bt_pgd = (pd_entry_t *) new_pgd; 768 memset (bt_pgd, 0, PAGE_SIZE); 769 avail = new_pgd + PAGE_SIZE; 770 #if PTP_LEVELS > 3 771 /* per-cpu L4 PD */ 772 pd_entry_t *bt_cpu_pgd = bt_pgd; 773 /* pmap_kernel() "shadow" L4 PD */ 774 bt_pgd = (pd_entry_t *) avail; 775 memset(bt_pgd, 0, PAGE_SIZE); 776 avail += PAGE_SIZE; 777 778 /* Install level 3 */ 779 pdtpe = (pd_entry_t *) avail; 780 memset (pdtpe, 0, PAGE_SIZE); 781 avail += PAGE_SIZE; 782 783 addr = ((u_long) pdtpe) - KERNBASE; 784 bt_pgd[pl4_pi(KERNTEXTOFF)] = bt_cpu_pgd[pl4_pi(KERNTEXTOFF)] = 785 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 786 787 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 788 " -> L4[%#x]\n", 789 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 790 #else 791 pdtpe = bt_pgd; 792 #endif /* PTP_LEVELS > 3 */ 793 794 #if PTP_LEVELS > 2 795 /* Level 2 */ 796 pde = (pd_entry_t *) avail; 797 memset(pde, 0, PAGE_SIZE); 798 avail += PAGE_SIZE; 799 800 addr = ((u_long) pde) - KERNBASE; 801 pdtpe[pl3_pi(KERNTEXTOFF)] = 802 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 803 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 804 " -> L3[%#x]\n", 805 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 806 #elif defined(PAE) 807 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 808 pde = (pd_entry_t *) avail; 809 memset(pde, 0, PAGE_SIZE * 5); 810 avail += PAGE_SIZE * 5; 811 addr = ((u_long) pde) - KERNBASE; 812 /* 813 * enter L2 pages in the L3. 814 * The real L2 kernel PD will be the last one (so that 815 * pde[L2_SLOT_KERN] always point to the shadow). 816 */ 817 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 818 /* 819 * Xen doesn't want R/W mappings in L3 entries, it'll add it 820 * itself. 821 */ 822 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 823 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 824 " -> L3[%#x]\n", 825 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 826 } 827 addr += PAGE_SIZE; 828 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 829 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 830 " -> L3[%#x]\n", 831 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 832 833 #else /* PAE */ 834 pde = bt_pgd; 835 #endif /* PTP_LEVELS > 2 */ 836 837 /* Level 1 */ 838 page = KERNTEXTOFF; 839 for (i = 0; i < new_count; i ++) { 840 vaddr_t cur_page = page; 841 842 pte = (pd_entry_t *) avail; 843 avail += PAGE_SIZE; 844 845 memset(pte, 0, PAGE_SIZE); 846 while (pl2_pi(page) == pl2_pi (cur_page)) { 847 if (page >= map_end) { 848 /* not mapped at all */ 849 pte[pl1_pi(page)] = 0; 850 page += PAGE_SIZE; 851 continue; 852 } 853 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 854 if (page == (vaddr_t)HYPERVISOR_shared_info) { 855 pte[pl1_pi(page)] = xen_start_info.shared_info; 856 __PRINTK(("HYPERVISOR_shared_info " 857 "va %#lx pte %#" PRIxPADDR "\n", 858 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 859 } 860 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 861 == xen_start_info.console.domU.mfn) { 862 xencons_interface = (void *)page; 863 pte[pl1_pi(page)] = xen_start_info.console_mfn; 864 pte[pl1_pi(page)] <<= PAGE_SHIFT; 865 __PRINTK(("xencons_interface " 866 "va %#lx pte %#" PRIxPADDR "\n", 867 xencons_interface, pte[pl1_pi(page)])); 868 } 869 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 870 == xen_start_info.store_mfn) { 871 xenstore_interface = (void *)page; 872 pte[pl1_pi(page)] = xen_start_info.store_mfn; 873 pte[pl1_pi(page)] <<= PAGE_SHIFT; 874 __PRINTK(("xenstore_interface " 875 "va %#lx pte %#" PRIxPADDR "\n", 876 xenstore_interface, pte[pl1_pi(page)])); 877 } 878 #ifdef DOM0OPS 879 if (page >= (vaddr_t)atdevbase && 880 page < (vaddr_t)atdevbase + IOM_SIZE) { 881 pte[pl1_pi(page)] = 882 IOM_BEGIN + (page - (vaddr_t)atdevbase); 883 } 884 #endif 885 pte[pl1_pi(page)] |= PG_k | PG_V; 886 if (page < text_end) { 887 /* map kernel text RO */ 888 pte[pl1_pi(page)] |= 0; 889 } else if (page >= old_pgd 890 && page < old_pgd + (old_count * PAGE_SIZE)) { 891 /* map old page tables RO */ 892 pte[pl1_pi(page)] |= 0; 893 } else if (page >= new_pgd && 894 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 895 /* map new page tables RO */ 896 pte[pl1_pi(page)] |= 0; 897 } else { 898 /* map page RW */ 899 pte[pl1_pi(page)] |= PG_RW; 900 } 901 902 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 903 || page >= new_pgd) { 904 __PRINTK(("va %#lx pa %#lx " 905 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 906 page, page - KERNBASE, 907 pte[pl1_pi(page)], pl1_pi(page))); 908 } 909 page += PAGE_SIZE; 910 } 911 912 addr = ((u_long) pte) - KERNBASE; 913 pde[pl2_pi(cur_page)] = 914 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 915 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 916 " -> L2[%#x]\n", 917 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 918 /* Mark readonly */ 919 xen_bt_set_readonly((vaddr_t) pte); 920 } 921 922 /* Install recursive page tables mapping */ 923 #ifdef PAE 924 /* 925 * we need a shadow page for the kernel's L2 page 926 * The real L2 kernel PD will be the last one (so that 927 * pde[L2_SLOT_KERN] always point to the shadow. 928 */ 929 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 930 cpu_info_primary.ci_kpm_pdir = &pde[L2_SLOT_KERN + NPDPG]; 931 cpu_info_primary.ci_kpm_pdirpa = 932 (vaddr_t) cpu_info_primary.ci_kpm_pdir - KERNBASE; 933 934 /* 935 * We don't enter a recursive entry from the L3 PD. Instead, 936 * we enter the first 4 L2 pages, which includes the kernel's L2 937 * shadow. But we have to entrer the shadow after switching 938 * %cr3, or Xen will refcount some PTE with the wrong type. 939 */ 940 addr = (u_long)pde - KERNBASE; 941 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 942 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 943 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 944 " entry %#" PRIxPADDR "\n", 945 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 946 addr, pde[PDIR_SLOT_PTE + i])); 947 } 948 #if 0 949 addr += PAGE_SIZE; /* point to shadow L2 */ 950 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 951 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 952 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 953 (int64_t)pde[PDIR_SLOT_PTE + 3])); 954 #endif 955 /* Mark tables RO, and pin the kernel's shadow as L2 */ 956 addr = (u_long)pde - KERNBASE; 957 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 958 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 959 if (i == 2 || i == 3) 960 continue; 961 #if 0 962 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 963 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 964 #endif 965 } 966 if (final) { 967 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 968 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 969 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 970 } 971 #if 0 972 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 973 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 974 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 975 #endif 976 #else /* PAE */ 977 /* recursive entry in higher-level per-cpu PD and pmap_kernel() */ 978 bt_pgd[PDIR_SLOT_PTE] = 979 #ifdef __x86_64__ 980 bt_cpu_pgd[PDIR_SLOT_PTE] = 981 #endif /* __x86_64__ */ 982 xpmap_ptom_masked(new_pgd - KERNBASE) | PG_k | PG_V; 983 __PRINTK(("bt_cpu_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 984 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 985 bt_pgd[PDIR_SLOT_PTE])); 986 987 988 /* Mark tables RO */ 989 xen_bt_set_readonly((vaddr_t) pde); 990 #endif 991 #if PTP_LEVELS > 2 || defined(PAE) 992 xen_bt_set_readonly((vaddr_t) pdtpe); 993 #endif 994 #if PTP_LEVELS > 3 995 xen_bt_set_readonly(new_pgd); 996 #endif 997 /* Pin the PGD */ 998 __PRINTK(("pin PGD: %"PRIxVADDR"\n", new_pgd - KERNBASE)); 999 #ifdef __x86_64__ 1000 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1001 #elif PAE 1002 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1003 #else 1004 xpq_queue_pin_l2_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1005 #endif 1006 /* Save phys. addr of PDP, for libkvm. */ 1007 #ifdef PAE 1008 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 1009 #else 1010 PDPpaddr = (u_long)bt_pgd - KERNBASE; 1011 #endif 1012 1013 /* Switch to new tables */ 1014 __PRINTK(("switch to PGD\n")); 1015 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 1016 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 1017 bt_pgd[PDIR_SLOT_PTE])); 1018 1019 #ifdef PAE 1020 if (final) { 1021 /* save the address of the L3 page */ 1022 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 1023 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 1024 1025 /* now enter kernel's PTE mappings */ 1026 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 1027 xpq_queue_pte_update( 1028 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 1029 xpmap_ptom_masked(addr) | PG_k | PG_V); 1030 xpq_flush_queue(); 1031 } 1032 #elif defined(__x86_64__) 1033 if (final) { 1034 /* save the address of the real per-cpu L4 pgd page */ 1035 cpu_info_primary.ci_kpm_pdir = bt_cpu_pgd; 1036 cpu_info_primary.ci_kpm_pdirpa = ((paddr_t) bt_cpu_pgd - KERNBASE); 1037 } 1038 #endif 1039 1040 /* Now we can safely reclaim space taken by old tables */ 1041 1042 __PRINTK(("unpin old PGD\n")); 1043 /* Unpin old PGD */ 1044 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 1045 /* Mark old tables RW */ 1046 page = old_pgd; 1047 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 1048 addr = xpmap_mtop(addr); 1049 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 1050 pte += pl1_pi(page); 1051 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 1052 pde[pl2_pi(page)], addr, (long)pte)); 1053 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 1054 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 1055 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 1056 "*pte %#" PRIxPADDR "\n", 1057 addr, (long)pte, *pte)); 1058 xpq_queue_pte_update(addr, *pte | PG_RW); 1059 page += PAGE_SIZE; 1060 /* 1061 * Our ptes are contiguous 1062 * so it's safe to just "++" here 1063 */ 1064 pte++; 1065 } 1066 xpq_flush_queue(); 1067 xpq_queue_unlock(); 1068 } 1069 1070 1071 /* 1072 * Bootstrap helper functions 1073 */ 1074 1075 /* 1076 * Mark a page readonly 1077 * XXX: assuming vaddr = paddr + KERNBASE 1078 */ 1079 1080 static void 1081 xen_bt_set_readonly (vaddr_t page) 1082 { 1083 pt_entry_t entry; 1084 1085 entry = xpmap_ptom_masked(page - KERNBASE); 1086 entry |= PG_k | PG_V; 1087 1088 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 1089 } 1090 1091 #ifdef __x86_64__ 1092 void 1093 xen_set_user_pgd(paddr_t page) 1094 { 1095 struct mmuext_op op; 1096 int s = splvm(); 1097 1098 KASSERT(xpq_queue_locked()); 1099 xpq_flush_queue(); 1100 op.cmd = MMUEXT_NEW_USER_BASEPTR; 1101 op.arg1.mfn = xpmap_phys_to_machine_mapping[page >> PAGE_SHIFT]; 1102 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 1103 panic("xen_set_user_pgd: failed to install new user page" 1104 " directory %#" PRIxPADDR, page); 1105 splx(s); 1106 } 1107 #endif /* __x86_64__ */ 1108
Indexes created Wed Oct 22 13:09:56 GMT 2025