x86_xpmap.c revision 1.52
1 /* $NetBSD: x86_xpmap.c,v 1.52 2013/11/10 01:19:13 jnemeth Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Copyright (c) 2006, 2007 Manuel Bouyer. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 */ 43 44 /* 45 * 46 * Copyright (c) 2004 Christian Limpach. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.52 2013/11/10 01:19:13 jnemeth Exp $"); 73 74 #include "opt_xen.h" 75 #include "opt_ddb.h" 76 #include "ksyms.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mutex.h> 81 #include <sys/cpu.h> 82 83 #include <uvm/uvm.h> 84 85 #include <x86/pmap.h> 86 #include <machine/gdt.h> 87 #include <xen/xenfunc.h> 88 89 #include <dev/isa/isareg.h> 90 #include <machine/isa_machdep.h> 91 92 #undef XENDEBUG 93 /* #define XENDEBUG_SYNC */ 94 /* #define XENDEBUG_LOW */ 95 96 #ifdef XENDEBUG 97 #define XENPRINTF(x) printf x 98 #define XENPRINTK(x) printk x 99 #define XENPRINTK2(x) /* printk x */ 100 101 static char XBUF[256]; 102 #else 103 #define XENPRINTF(x) 104 #define XENPRINTK(x) 105 #define XENPRINTK2(x) 106 #endif 107 #define PRINTF(x) printf x 108 #define PRINTK(x) printk x 109 110 volatile shared_info_t *HYPERVISOR_shared_info; 111 /* Xen requires the start_info struct to be page aligned */ 112 union start_info_union start_info_union __aligned(PAGE_SIZE); 113 unsigned long *xpmap_phys_to_machine_mapping; 114 kmutex_t pte_lock; 115 116 void xen_failsafe_handler(void); 117 118 #define HYPERVISOR_mmu_update_self(req, count, success_count) \ 119 HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF) 120 121 /* 122 * kcpuset internally uses an array of uint32_t while xen uses an array of 123 * u_long. As we're little-endian we can cast one to the other. 124 */ 125 typedef union { 126 #ifdef _LP64 127 uint32_t xcpum_km[2]; 128 #else 129 uint32_t xcpum_km[1]; 130 #endif 131 u_long xcpum_xm; 132 } xcpumask_t; 133 134 void 135 xen_failsafe_handler(void) 136 { 137 138 panic("xen_failsafe_handler called!\n"); 139 } 140 141 142 void 143 xen_set_ldt(vaddr_t base, uint32_t entries) 144 { 145 vaddr_t va; 146 vaddr_t end; 147 pt_entry_t *ptp; 148 int s; 149 150 #ifdef __x86_64__ 151 end = base + (entries << 3); 152 #else 153 end = base + entries * sizeof(union descriptor); 154 #endif 155 156 for (va = base; va < end; va += PAGE_SIZE) { 157 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 158 ptp = kvtopte(va); 159 XENPRINTF(("xen_set_ldt %#" PRIxVADDR " %d %p\n", 160 base, entries, ptp)); 161 pmap_pte_clearbits(ptp, PG_RW); 162 } 163 s = splvm(); 164 xpq_queue_set_ldt(base, entries); 165 splx(s); 166 } 167 168 #ifdef XENDEBUG 169 void xpq_debug_dump(void); 170 #endif 171 172 #define XPQUEUE_SIZE 2048 173 static mmu_update_t xpq_queue_array[MAXCPUS][XPQUEUE_SIZE]; 174 static int xpq_idx_array[MAXCPUS]; 175 176 #ifdef i386 177 extern union descriptor tmpgdt[]; 178 #endif /* i386 */ 179 void 180 xpq_flush_queue(void) 181 { 182 int i, ok = 0, ret; 183 184 mmu_update_t *xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 185 int xpq_idx = xpq_idx_array[curcpu()->ci_cpuid]; 186 187 XENPRINTK2(("flush queue %p entries %d\n", xpq_queue, xpq_idx)); 188 for (i = 0; i < xpq_idx; i++) 189 XENPRINTK2(("%d: 0x%08" PRIx64 " 0x%08" PRIx64 "\n", i, 190 xpq_queue[i].ptr, xpq_queue[i].val)); 191 192 retry: 193 ret = HYPERVISOR_mmu_update_self(xpq_queue, xpq_idx, &ok); 194 195 if (xpq_idx != 0 && ret < 0) { 196 struct cpu_info *ci; 197 CPU_INFO_ITERATOR cii; 198 199 printf("xpq_flush_queue: %d entries (%d successful) on " 200 "cpu%d (%ld)\n", 201 xpq_idx, ok, curcpu()->ci_index, curcpu()->ci_cpuid); 202 203 if (ok != 0) { 204 xpq_queue += ok; 205 xpq_idx -= ok; 206 ok = 0; 207 goto retry; 208 } 209 210 for (CPU_INFO_FOREACH(cii, ci)) { 211 xpq_queue = xpq_queue_array[ci->ci_cpuid]; 212 xpq_idx = xpq_idx_array[ci->ci_cpuid]; 213 printf("cpu%d (%ld):\n", ci->ci_index, ci->ci_cpuid); 214 for (i = 0; i < xpq_idx; i++) { 215 printf(" 0x%016" PRIx64 ": 0x%016" PRIx64 "\n", 216 xpq_queue[i].ptr, xpq_queue[i].val); 217 } 218 #ifdef __x86_64__ 219 for (i = 0; i < PDIR_SLOT_PTE; i++) { 220 if (ci->ci_kpm_pdir[i] == 0) 221 continue; 222 printf(" kpm_pdir[%d]: 0x%" PRIx64 "\n", 223 i, ci->ci_kpm_pdir[i]); 224 } 225 #endif 226 } 227 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 228 } 229 xpq_idx_array[curcpu()->ci_cpuid] = 0; 230 } 231 232 static inline void 233 xpq_increment_idx(void) 234 { 235 236 if (__predict_false(++xpq_idx_array[curcpu()->ci_cpuid] == XPQUEUE_SIZE)) 237 xpq_flush_queue(); 238 } 239 240 void 241 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 242 { 243 244 mmu_update_t *xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 245 int xpq_idx = xpq_idx_array[curcpu()->ci_cpuid]; 246 247 XENPRINTK2(("xpq_queue_machphys_update ma=0x%" PRIx64 " pa=0x%" PRIx64 248 "\n", (int64_t)ma, (int64_t)pa)); 249 250 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 251 xpq_queue[xpq_idx].val = pa >> PAGE_SHIFT; 252 xpq_increment_idx(); 253 #ifdef XENDEBUG_SYNC 254 xpq_flush_queue(); 255 #endif 256 } 257 258 void 259 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 260 { 261 262 mmu_update_t *xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 263 int xpq_idx = xpq_idx_array[curcpu()->ci_cpuid]; 264 265 KASSERT((ptr & 3) == 0); 266 xpq_queue[xpq_idx].ptr = (paddr_t)ptr | MMU_NORMAL_PT_UPDATE; 267 xpq_queue[xpq_idx].val = val; 268 xpq_increment_idx(); 269 #ifdef XENDEBUG_SYNC 270 xpq_flush_queue(); 271 #endif 272 } 273 274 void 275 xpq_queue_pt_switch(paddr_t pa) 276 { 277 struct mmuext_op op; 278 xpq_flush_queue(); 279 280 XENPRINTK2(("xpq_queue_pt_switch: 0x%" PRIx64 " 0x%" PRIx64 "\n", 281 (int64_t)pa, (int64_t)pa)); 282 op.cmd = MMUEXT_NEW_BASEPTR; 283 op.arg1.mfn = pa >> PAGE_SHIFT; 284 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 285 panic("xpq_queue_pt_switch"); 286 } 287 288 void 289 xpq_queue_pin_table(paddr_t pa, int lvl) 290 { 291 struct mmuext_op op; 292 293 xpq_flush_queue(); 294 295 XENPRINTK2(("xpq_queue_pin_l%d_table: %#" PRIxPADDR "\n", 296 lvl + 1, pa)); 297 298 op.arg1.mfn = pa >> PAGE_SHIFT; 299 op.cmd = lvl; 300 301 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 302 panic("xpq_queue_pin_table"); 303 } 304 305 void 306 xpq_queue_unpin_table(paddr_t pa) 307 { 308 struct mmuext_op op; 309 310 xpq_flush_queue(); 311 312 XENPRINTK2(("xpq_queue_unpin_table: %#" PRIxPADDR "\n", pa)); 313 op.arg1.mfn = pa >> PAGE_SHIFT; 314 op.cmd = MMUEXT_UNPIN_TABLE; 315 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 316 panic("xpq_queue_unpin_table"); 317 } 318 319 void 320 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 321 { 322 struct mmuext_op op; 323 324 xpq_flush_queue(); 325 326 XENPRINTK2(("xpq_queue_set_ldt\n")); 327 KASSERT(va == (va & ~PAGE_MASK)); 328 op.cmd = MMUEXT_SET_LDT; 329 op.arg1.linear_addr = va; 330 op.arg2.nr_ents = entries; 331 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 332 panic("xpq_queue_set_ldt"); 333 } 334 335 void 336 xpq_queue_tlb_flush(void) 337 { 338 struct mmuext_op op; 339 340 xpq_flush_queue(); 341 342 XENPRINTK2(("xpq_queue_tlb_flush\n")); 343 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 344 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 345 panic("xpq_queue_tlb_flush"); 346 } 347 348 void 349 xpq_flush_cache(void) 350 { 351 int s = splvm(); 352 353 xpq_flush_queue(); 354 355 XENPRINTK2(("xpq_queue_flush_cache\n")); 356 asm("wbinvd":::"memory"); 357 splx(s); /* XXX: removeme */ 358 } 359 360 void 361 xpq_queue_invlpg(vaddr_t va) 362 { 363 struct mmuext_op op; 364 xpq_flush_queue(); 365 366 XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va)); 367 op.cmd = MMUEXT_INVLPG_LOCAL; 368 op.arg1.linear_addr = (va & ~PAGE_MASK); 369 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 370 panic("xpq_queue_invlpg"); 371 } 372 373 void 374 xen_mcast_invlpg(vaddr_t va, kcpuset_t *kc) 375 { 376 xcpumask_t xcpumask; 377 mmuext_op_t op; 378 379 kcpuset_export_u32(kc, &xcpumask.xcpum_km[0], sizeof(xcpumask)); 380 381 /* Flush pending page updates */ 382 xpq_flush_queue(); 383 384 op.cmd = MMUEXT_INVLPG_MULTI; 385 op.arg1.linear_addr = va; 386 op.arg2.vcpumask = &xcpumask.xcpum_xm; 387 388 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 389 panic("xpq_queue_invlpg_all"); 390 } 391 392 return; 393 } 394 395 void 396 xen_bcast_invlpg(vaddr_t va) 397 { 398 mmuext_op_t op; 399 400 /* Flush pending page updates */ 401 xpq_flush_queue(); 402 403 op.cmd = MMUEXT_INVLPG_ALL; 404 op.arg1.linear_addr = va; 405 406 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 407 panic("xpq_queue_invlpg_all"); 408 } 409 410 return; 411 } 412 413 /* This is a synchronous call. */ 414 void 415 xen_mcast_tlbflush(kcpuset_t *kc) 416 { 417 xcpumask_t xcpumask; 418 mmuext_op_t op; 419 420 kcpuset_export_u32(kc, &xcpumask.xcpum_km[0], sizeof(xcpumask)); 421 422 /* Flush pending page updates */ 423 xpq_flush_queue(); 424 425 op.cmd = MMUEXT_TLB_FLUSH_MULTI; 426 op.arg2.vcpumask = &xcpumask.xcpum_xm; 427 428 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 429 panic("xpq_queue_invlpg_all"); 430 } 431 432 return; 433 } 434 435 /* This is a synchronous call. */ 436 void 437 xen_bcast_tlbflush(void) 438 { 439 mmuext_op_t op; 440 441 /* Flush pending page updates */ 442 xpq_flush_queue(); 443 444 op.cmd = MMUEXT_TLB_FLUSH_ALL; 445 446 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) { 447 panic("xpq_queue_invlpg_all"); 448 } 449 450 return; 451 } 452 453 /* This is a synchronous call. */ 454 void 455 xen_vcpu_mcast_invlpg(vaddr_t sva, vaddr_t eva, kcpuset_t *kc) 456 { 457 KASSERT(eva > sva); 458 459 /* Flush pending page updates */ 460 xpq_flush_queue(); 461 462 /* Align to nearest page boundary */ 463 sva &= ~PAGE_MASK; 464 eva &= ~PAGE_MASK; 465 466 for ( ; sva <= eva; sva += PAGE_SIZE) { 467 xen_mcast_invlpg(sva, kc); 468 } 469 470 return; 471 } 472 473 /* This is a synchronous call. */ 474 void 475 xen_vcpu_bcast_invlpg(vaddr_t sva, vaddr_t eva) 476 { 477 KASSERT(eva > sva); 478 479 /* Flush pending page updates */ 480 xpq_flush_queue(); 481 482 /* Align to nearest page boundary */ 483 sva &= ~PAGE_MASK; 484 eva &= ~PAGE_MASK; 485 486 for ( ; sva <= eva; sva += PAGE_SIZE) { 487 xen_bcast_invlpg(sva); 488 } 489 490 return; 491 } 492 493 int 494 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 495 { 496 mmu_update_t op; 497 int ok; 498 499 xpq_flush_queue(); 500 501 op.ptr = ptr; 502 op.val = val; 503 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 504 return EFAULT; 505 return (0); 506 } 507 508 #ifdef XENDEBUG 509 void 510 xpq_debug_dump(void) 511 { 512 int i; 513 514 mmu_update_t *xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 515 int xpq_idx = xpq_idx_array[curcpu()->ci_cpuid]; 516 517 XENPRINTK2(("idx: %d\n", xpq_idx)); 518 for (i = 0; i < xpq_idx; i++) { 519 snprintf(XBUF, sizeof(XBUF), "%" PRIx64 " %08" PRIx64, 520 xpq_queue[i].ptr, xpq_queue[i].val); 521 if (++i < xpq_idx) 522 snprintf(XBUF + strlen(XBUF), 523 sizeof(XBUF) - strlen(XBUF), 524 "%" PRIx64 " %08" PRIx64, 525 xpq_queue[i].ptr, xpq_queue[i].val); 526 if (++i < xpq_idx) 527 snprintf(XBUF + strlen(XBUF), 528 sizeof(XBUF) - strlen(XBUF), 529 "%" PRIx64 " %08" PRIx64, 530 xpq_queue[i].ptr, xpq_queue[i].val); 531 if (++i < xpq_idx) 532 snprintf(XBUF + strlen(XBUF), 533 sizeof(XBUF) - strlen(XBUF), 534 "%" PRIx64 " %08" PRIx64, 535 xpq_queue[i].ptr, xpq_queue[i].val); 536 XENPRINTK2(("%d: %s\n", xpq_idx, XBUF)); 537 } 538 } 539 #endif 540 541 542 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 543 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 544 545 static void xen_bt_set_readonly (vaddr_t); 546 static void xen_bootstrap_tables (vaddr_t, vaddr_t, int, int, int); 547 548 /* How many PDEs ? */ 549 #if L2_SLOT_KERNBASE > 0 550 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 551 #else 552 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 553 #endif 554 555 /* 556 * Construct and switch to new pagetables 557 * first_avail is the first vaddr we can use after 558 * we get rid of Xen pagetables 559 */ 560 561 vaddr_t xen_pmap_bootstrap (void); 562 563 /* 564 * Function to get rid of Xen bootstrap tables 565 */ 566 567 /* How many PDP do we need: */ 568 #ifdef PAE 569 /* 570 * For PAE, we consider a single contigous L2 "superpage" of 4 pages, 571 * all of them mapped by the L3 page. We also need a shadow page 572 * for L3[3]. 573 */ 574 static const int l2_4_count = 6; 575 #elif defined(__x86_64__) 576 static const int l2_4_count = PTP_LEVELS; 577 #else 578 static const int l2_4_count = PTP_LEVELS - 1; 579 #endif 580 581 vaddr_t 582 xen_pmap_bootstrap(void) 583 { 584 int count, oldcount; 585 long mapsize; 586 vaddr_t bootstrap_tables, init_tables; 587 588 memset(xpq_idx_array, 0, sizeof xpq_idx_array); 589 590 xpmap_phys_to_machine_mapping = 591 (unsigned long *)xen_start_info.mfn_list; 592 init_tables = xen_start_info.pt_base; 593 __PRINTK(("xen_arch_pmap_bootstrap init_tables=0x%lx\n", init_tables)); 594 595 /* Space after Xen boostrap tables should be free */ 596 bootstrap_tables = xen_start_info.pt_base + 597 (xen_start_info.nr_pt_frames * PAGE_SIZE); 598 599 /* 600 * Calculate how many space we need 601 * first everything mapped before the Xen bootstrap tables 602 */ 603 mapsize = init_tables - KERNTEXTOFF; 604 /* after the tables we'll have: 605 * - UAREA 606 * - dummy user PGD (x86_64) 607 * - HYPERVISOR_shared_info 608 * - early_zerop 609 * - ISA I/O mem (if needed) 610 */ 611 mapsize += UPAGES * NBPG; 612 #ifdef __x86_64__ 613 mapsize += NBPG; 614 #endif 615 mapsize += NBPG; 616 mapsize += NBPG; 617 618 #ifdef DOM0OPS 619 if (xendomain_is_dom0()) { 620 /* space for ISA I/O mem */ 621 mapsize += IOM_SIZE; 622 } 623 #endif 624 /* at this point mapsize doens't include the table size */ 625 626 #ifdef __x86_64__ 627 count = TABLE_L2_ENTRIES; 628 #else 629 count = (mapsize + (NBPD_L2 -1)) >> L2_SHIFT; 630 #endif /* __x86_64__ */ 631 632 /* now compute how many L2 pages we need exactly */ 633 XENPRINTK(("bootstrap_final mapsize 0x%lx count %d\n", mapsize, count)); 634 while (mapsize + (count + l2_4_count) * PAGE_SIZE + KERNTEXTOFF > 635 ((long)count << L2_SHIFT) + KERNBASE) { 636 count++; 637 } 638 #ifndef __x86_64__ 639 /* 640 * one more L2 page: we'll alocate several pages after kva_start 641 * in pmap_bootstrap() before pmap_growkernel(), which have not been 642 * counted here. It's not a big issue to allocate one more L2 as 643 * pmap_growkernel() will be called anyway. 644 */ 645 count++; 646 nkptp[1] = count; 647 #endif 648 649 /* 650 * install bootstrap pages. We may need more L2 pages than will 651 * have the final table here, as it's installed after the final table 652 */ 653 oldcount = count; 654 655 bootstrap_again: 656 XENPRINTK(("bootstrap_again oldcount %d\n", oldcount)); 657 /* 658 * Xen space we'll reclaim may not be enough for our new page tables, 659 * move bootstrap tables if necessary 660 */ 661 if (bootstrap_tables < init_tables + ((count + l2_4_count) * PAGE_SIZE)) 662 bootstrap_tables = init_tables + 663 ((count + l2_4_count) * PAGE_SIZE); 664 /* make sure we have enough to map the bootstrap_tables */ 665 if (bootstrap_tables + ((oldcount + l2_4_count) * PAGE_SIZE) > 666 ((long)oldcount << L2_SHIFT) + KERNBASE) { 667 oldcount++; 668 goto bootstrap_again; 669 } 670 671 /* Create temporary tables */ 672 xen_bootstrap_tables(xen_start_info.pt_base, bootstrap_tables, 673 xen_start_info.nr_pt_frames, oldcount, 0); 674 675 /* Create final tables */ 676 xen_bootstrap_tables(bootstrap_tables, init_tables, 677 oldcount + l2_4_count, count, 1); 678 679 /* zero out free space after tables */ 680 memset((void *)(init_tables + ((count + l2_4_count) * PAGE_SIZE)), 0, 681 (UPAGES + 1) * NBPG); 682 683 /* Finally, flush TLB. */ 684 xpq_queue_tlb_flush(); 685 686 return (init_tables + ((count + l2_4_count) * PAGE_SIZE)); 687 } 688 689 /* 690 * Build a new table and switch to it 691 * old_count is # of old tables (including PGD, PDTPE and PDE) 692 * new_count is # of new tables (PTE only) 693 * we assume areas don't overlap 694 */ 695 static void 696 xen_bootstrap_tables (vaddr_t old_pgd, vaddr_t new_pgd, 697 int old_count, int new_count, int final) 698 { 699 pd_entry_t *pdtpe, *pde, *pte; 700 pd_entry_t *bt_pgd; 701 paddr_t addr; 702 vaddr_t page, avail, text_end, map_end; 703 int i; 704 extern char __data_start; 705 extern char *early_zerop; /* from pmap.c */ 706 707 __PRINTK(("xen_bootstrap_tables(%#" PRIxVADDR ", %#" PRIxVADDR "," 708 " %d, %d)\n", 709 old_pgd, new_pgd, old_count, new_count)); 710 text_end = ((vaddr_t)&__data_start) & ~PAGE_MASK; 711 /* 712 * size of R/W area after kernel text: 713 * xencons_interface (if present) 714 * xenstore_interface (if present) 715 * table pages (new_count + l2_4_count entries) 716 * extra mappings (only when final is true): 717 * UAREA 718 * dummy user PGD (x86_64 only)/gdt page (i386 only) 719 * HYPERVISOR_shared_info 720 * early_zerop 721 * ISA I/O mem (if needed) 722 */ 723 map_end = new_pgd + ((new_count + l2_4_count) * NBPG); 724 if (final) { 725 map_end += (UPAGES + 1) * NBPG; 726 HYPERVISOR_shared_info = (shared_info_t *)map_end; 727 map_end += NBPG; 728 early_zerop = (char *)map_end; 729 map_end += NBPG; 730 } 731 /* 732 * we always set atdevbase, as it's used by init386 to find the first 733 * available VA. map_end is updated only if we are dom0, so 734 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 735 * this case. 736 */ 737 if (final) 738 atdevbase = map_end; 739 #ifdef DOM0OPS 740 if (final && xendomain_is_dom0()) { 741 /* ISA I/O mem */ 742 map_end += IOM_SIZE; 743 } 744 #endif /* DOM0OPS */ 745 746 __PRINTK(("xen_bootstrap_tables text_end 0x%lx map_end 0x%lx\n", 747 text_end, map_end)); 748 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 749 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 750 751 /* 752 * Create bootstrap page tables 753 * What we need: 754 * - a PGD (level 4) 755 * - a PDTPE (level 3) 756 * - a PDE (level2) 757 * - some PTEs (level 1) 758 */ 759 760 bt_pgd = (pd_entry_t *) new_pgd; 761 memset (bt_pgd, 0, PAGE_SIZE); 762 avail = new_pgd + PAGE_SIZE; 763 #if PTP_LEVELS > 3 764 /* per-cpu L4 PD */ 765 pd_entry_t *bt_cpu_pgd = bt_pgd; 766 /* pmap_kernel() "shadow" L4 PD */ 767 bt_pgd = (pd_entry_t *) avail; 768 memset(bt_pgd, 0, PAGE_SIZE); 769 avail += PAGE_SIZE; 770 771 /* Install level 3 */ 772 pdtpe = (pd_entry_t *) avail; 773 memset (pdtpe, 0, PAGE_SIZE); 774 avail += PAGE_SIZE; 775 776 addr = ((u_long) pdtpe) - KERNBASE; 777 bt_pgd[pl4_pi(KERNTEXTOFF)] = bt_cpu_pgd[pl4_pi(KERNTEXTOFF)] = 778 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 779 780 __PRINTK(("L3 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 781 " -> L4[%#x]\n", 782 pdtpe, addr, bt_pgd[pl4_pi(KERNTEXTOFF)], pl4_pi(KERNTEXTOFF))); 783 #else 784 pdtpe = bt_pgd; 785 #endif /* PTP_LEVELS > 3 */ 786 787 #if PTP_LEVELS > 2 788 /* Level 2 */ 789 pde = (pd_entry_t *) avail; 790 memset(pde, 0, PAGE_SIZE); 791 avail += PAGE_SIZE; 792 793 addr = ((u_long) pde) - KERNBASE; 794 pdtpe[pl3_pi(KERNTEXTOFF)] = 795 xpmap_ptom_masked(addr) | PG_k | PG_V | PG_RW; 796 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 797 " -> L3[%#x]\n", 798 pde, addr, pdtpe[pl3_pi(KERNTEXTOFF)], pl3_pi(KERNTEXTOFF))); 799 #elif defined(PAE) 800 /* our PAE-style level 2: 5 contigous pages (4 L2 + 1 shadow) */ 801 pde = (pd_entry_t *) avail; 802 memset(pde, 0, PAGE_SIZE * 5); 803 avail += PAGE_SIZE * 5; 804 addr = ((u_long) pde) - KERNBASE; 805 /* 806 * enter L2 pages in the L3. 807 * The real L2 kernel PD will be the last one (so that 808 * pde[L2_SLOT_KERN] always point to the shadow). 809 */ 810 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 811 /* 812 * Xen doesn't want R/W mappings in L3 entries, it'll add it 813 * itself. 814 */ 815 pdtpe[i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 816 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 817 " -> L3[%#x]\n", 818 (vaddr_t)pde + PAGE_SIZE * i, addr, pdtpe[i], i)); 819 } 820 addr += PAGE_SIZE; 821 pdtpe[3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 822 __PRINTK(("L2 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 823 " -> L3[%#x]\n", 824 (vaddr_t)pde + PAGE_SIZE * 4, addr, pdtpe[3], 3)); 825 826 #else /* PAE */ 827 pde = bt_pgd; 828 #endif /* PTP_LEVELS > 2 */ 829 830 /* Level 1 */ 831 page = KERNTEXTOFF; 832 for (i = 0; i < new_count; i ++) { 833 vaddr_t cur_page = page; 834 835 pte = (pd_entry_t *) avail; 836 avail += PAGE_SIZE; 837 838 memset(pte, 0, PAGE_SIZE); 839 while (pl2_pi(page) == pl2_pi (cur_page)) { 840 if (page >= map_end) { 841 /* not mapped at all */ 842 pte[pl1_pi(page)] = 0; 843 page += PAGE_SIZE; 844 continue; 845 } 846 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 847 if (page == (vaddr_t)HYPERVISOR_shared_info) { 848 pte[pl1_pi(page)] = xen_start_info.shared_info; 849 __PRINTK(("HYPERVISOR_shared_info " 850 "va %#lx pte %#" PRIxPADDR "\n", 851 HYPERVISOR_shared_info, pte[pl1_pi(page)])); 852 } 853 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 854 == xen_start_info.console.domU.mfn) { 855 xencons_interface = (void *)page; 856 pte[pl1_pi(page)] = xen_start_info.console_mfn; 857 pte[pl1_pi(page)] <<= PAGE_SHIFT; 858 __PRINTK(("xencons_interface " 859 "va %#lx pte %#" PRIxPADDR "\n", 860 xencons_interface, pte[pl1_pi(page)])); 861 } 862 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 863 == xen_start_info.store_mfn) { 864 xenstore_interface = (void *)page; 865 pte[pl1_pi(page)] = xen_start_info.store_mfn; 866 pte[pl1_pi(page)] <<= PAGE_SHIFT; 867 __PRINTK(("xenstore_interface " 868 "va %#lx pte %#" PRIxPADDR "\n", 869 xenstore_interface, pte[pl1_pi(page)])); 870 } 871 #ifdef DOM0OPS 872 if (page >= (vaddr_t)atdevbase && 873 page < (vaddr_t)atdevbase + IOM_SIZE) { 874 pte[pl1_pi(page)] = 875 IOM_BEGIN + (page - (vaddr_t)atdevbase); 876 } 877 #endif 878 pte[pl1_pi(page)] |= PG_k | PG_V; 879 if (page < text_end) { 880 /* map kernel text RO */ 881 pte[pl1_pi(page)] |= 0; 882 } else if (page >= old_pgd 883 && page < old_pgd + (old_count * PAGE_SIZE)) { 884 /* map old page tables RO */ 885 pte[pl1_pi(page)] |= 0; 886 } else if (page >= new_pgd && 887 page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) { 888 /* map new page tables RO */ 889 pte[pl1_pi(page)] |= 0; 890 #ifdef i386 891 } else if (page == (vaddr_t)tmpgdt) { 892 /* 893 * Map bootstrap gdt R/O. Later, we 894 * will re-add this to page to uvm 895 * after making it writable. 896 */ 897 898 pte[pl1_pi(page)] = 0; 899 page += PAGE_SIZE; 900 continue; 901 #endif /* i386 */ 902 } else { 903 /* map page RW */ 904 pte[pl1_pi(page)] |= PG_RW; 905 } 906 907 if ((page >= old_pgd && page < old_pgd + (old_count * PAGE_SIZE)) 908 || page >= new_pgd) { 909 __PRINTK(("va %#lx pa %#lx " 910 "entry 0x%" PRIxPADDR " -> L1[%#x]\n", 911 page, page - KERNBASE, 912 pte[pl1_pi(page)], pl1_pi(page))); 913 } 914 page += PAGE_SIZE; 915 } 916 917 addr = ((u_long) pte) - KERNBASE; 918 pde[pl2_pi(cur_page)] = 919 xpmap_ptom_masked(addr) | PG_k | PG_RW | PG_V; 920 __PRINTK(("L1 va %#lx pa %#" PRIxPADDR " entry %#" PRIxPADDR 921 " -> L2[%#x]\n", 922 pte, addr, pde[pl2_pi(cur_page)], pl2_pi(cur_page))); 923 /* Mark readonly */ 924 xen_bt_set_readonly((vaddr_t) pte); 925 } 926 927 /* Install recursive page tables mapping */ 928 #ifdef PAE 929 /* 930 * we need a shadow page for the kernel's L2 page 931 * The real L2 kernel PD will be the last one (so that 932 * pde[L2_SLOT_KERN] always point to the shadow. 933 */ 934 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 935 cpu_info_primary.ci_kpm_pdir = &pde[L2_SLOT_KERN + NPDPG]; 936 cpu_info_primary.ci_kpm_pdirpa = 937 (vaddr_t) cpu_info_primary.ci_kpm_pdir - KERNBASE; 938 939 /* 940 * We don't enter a recursive entry from the L3 PD. Instead, 941 * we enter the first 4 L2 pages, which includes the kernel's L2 942 * shadow. But we have to entrer the shadow after switching 943 * %cr3, or Xen will refcount some PTE with the wrong type. 944 */ 945 addr = (u_long)pde - KERNBASE; 946 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 947 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_k | PG_V; 948 __PRINTK(("pde[%d] va %#" PRIxVADDR " pa %#" PRIxPADDR 949 " entry %#" PRIxPADDR "\n", 950 (int)(PDIR_SLOT_PTE + i), pde + PAGE_SIZE * i, 951 addr, pde[PDIR_SLOT_PTE + i])); 952 } 953 #if 0 954 addr += PAGE_SIZE; /* point to shadow L2 */ 955 pde[PDIR_SLOT_PTE + 3] = xpmap_ptom_masked(addr) | PG_k | PG_V; 956 __PRINTK(("pde[%d] va 0x%lx pa 0x%lx entry 0x%" PRIx64 "\n", 957 (int)(PDIR_SLOT_PTE + 3), pde + PAGE_SIZE * 4, (long)addr, 958 (int64_t)pde[PDIR_SLOT_PTE + 3])); 959 #endif 960 /* Mark tables RO, and pin the kernel's shadow as L2 */ 961 addr = (u_long)pde - KERNBASE; 962 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 963 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 964 if (i == 2 || i == 3) 965 continue; 966 #if 0 967 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", i, (int64_t)addr)); 968 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 969 #endif 970 } 971 if (final) { 972 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 973 __PRINTK(("pin L2 %d addr %#" PRIxPADDR "\n", 2, addr)); 974 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 975 } 976 #if 0 977 addr = (u_long)pde - KERNBASE + 2 * PAGE_SIZE; 978 __PRINTK(("pin L2 %d addr 0x%" PRIx64 "\n", 2, (int64_t)addr)); 979 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 980 #endif 981 #else /* PAE */ 982 /* recursive entry in higher-level per-cpu PD and pmap_kernel() */ 983 bt_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_pgd - KERNBASE) | PG_k | PG_V; 984 #ifdef __x86_64__ 985 bt_cpu_pgd[PDIR_SLOT_PTE] = 986 xpmap_ptom_masked((paddr_t)bt_cpu_pgd - KERNBASE) | PG_k | PG_V; 987 #endif /* __x86_64__ */ 988 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR 989 " entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE, 990 bt_pgd[PDIR_SLOT_PTE])); 991 /* Mark tables RO */ 992 xen_bt_set_readonly((vaddr_t) pde); 993 #endif 994 #if PTP_LEVELS > 2 || defined(PAE) 995 xen_bt_set_readonly((vaddr_t) pdtpe); 996 #endif 997 #if PTP_LEVELS > 3 998 xen_bt_set_readonly(new_pgd); 999 #endif 1000 /* Pin the PGD */ 1001 __PRINTK(("pin PGD: %"PRIxVADDR"\n", new_pgd - KERNBASE)); 1002 #ifdef __x86_64__ 1003 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1004 #elif PAE 1005 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1006 #else 1007 xpq_queue_pin_l2_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 1008 #endif 1009 1010 /* Save phys. addr of PDP, for libkvm. */ 1011 #ifdef PAE 1012 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 1013 #else 1014 PDPpaddr = (u_long)bt_pgd - KERNBASE; 1015 #endif 1016 1017 /* Switch to new tables */ 1018 __PRINTK(("switch to PGD\n")); 1019 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 1020 __PRINTK(("bt_pgd[PDIR_SLOT_PTE] now entry %#" PRIxPADDR "\n", 1021 bt_pgd[PDIR_SLOT_PTE])); 1022 1023 #ifdef PAE 1024 if (final) { 1025 /* save the address of the L3 page */ 1026 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 1027 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 1028 1029 /* now enter kernel's PTE mappings */ 1030 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 1031 xpq_queue_pte_update( 1032 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 1033 xpmap_ptom_masked(addr) | PG_k | PG_V); 1034 xpq_flush_queue(); 1035 } 1036 #elif defined(__x86_64__) 1037 if (final) { 1038 /* save the address of the real per-cpu L4 pgd page */ 1039 cpu_info_primary.ci_kpm_pdir = bt_cpu_pgd; 1040 cpu_info_primary.ci_kpm_pdirpa = ((paddr_t) bt_cpu_pgd - KERNBASE); 1041 } 1042 #endif 1043 __USE(pdtpe); 1044 1045 /* Now we can safely reclaim space taken by old tables */ 1046 1047 __PRINTK(("unpin old PGD\n")); 1048 /* Unpin old PGD */ 1049 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 1050 /* Mark old tables RW */ 1051 page = old_pgd; 1052 addr = (paddr_t) pde[pl2_pi(page)] & PG_FRAME; 1053 addr = xpmap_mtop(addr); 1054 pte = (pd_entry_t *) ((u_long)addr + KERNBASE); 1055 pte += pl1_pi(page); 1056 __PRINTK(("*pde %#" PRIxPADDR " addr %#" PRIxPADDR " pte %#lx\n", 1057 pde[pl2_pi(page)], addr, (long)pte)); 1058 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 1059 addr = xpmap_ptom(((u_long) pte) - KERNBASE); 1060 XENPRINTK(("addr %#" PRIxPADDR " pte %#lx " 1061 "*pte %#" PRIxPADDR "\n", 1062 addr, (long)pte, *pte)); 1063 xpq_queue_pte_update(addr, *pte | PG_RW); 1064 page += PAGE_SIZE; 1065 /* 1066 * Our ptes are contiguous 1067 * so it's safe to just "++" here 1068 */ 1069 pte++; 1070 } 1071 xpq_flush_queue(); 1072 } 1073 1074 1075 /* 1076 * Bootstrap helper functions 1077 */ 1078 1079 /* 1080 * Mark a page readonly 1081 * XXX: assuming vaddr = paddr + KERNBASE 1082 */ 1083 1084 static void 1085 xen_bt_set_readonly (vaddr_t page) 1086 { 1087 pt_entry_t entry; 1088 1089 entry = xpmap_ptom_masked(page - KERNBASE); 1090 entry |= PG_k | PG_V; 1091 1092 HYPERVISOR_update_va_mapping (page, entry, UVMF_INVLPG); 1093 } 1094 1095 #ifdef __x86_64__ 1096 void 1097 xen_set_user_pgd(paddr_t page) 1098 { 1099 struct mmuext_op op; 1100 int s = splvm(); 1101 1102 xpq_flush_queue(); 1103 op.cmd = MMUEXT_NEW_USER_BASEPTR; 1104 op.arg1.mfn = xpmap_ptom_masked(page) >> PAGE_SHIFT; 1105 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 1106 panic("xen_set_user_pgd: failed to install new user page" 1107 " directory %#" PRIxPADDR, page); 1108 splx(s); 1109 } 1110 #endif /* __x86_64__ */ 1111
Indexes created Mon Sep 29 21:09:56 GMT 2025