x86_xpmap.c revision 1.80
1 /* $NetBSD: x86_xpmap.c,v 1.80 2018/07/27 10:04:22 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2006 Mathieu Ropert <mro (at) adviseo.fr> 34 * 35 * Permission to use, copy, modify, and distribute this software for any 36 * purpose with or without fee is hereby granted, provided that the above 37 * copyright notice and this permission notice appear in all copies. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 40 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 41 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 42 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 43 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 44 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 45 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 46 */ 47 48 /* 49 * Copyright (c) 2006, 2007 Manuel Bouyer. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 61 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 62 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 63 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 64 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 65 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 66 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 67 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 68 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 69 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Copyright (c) 2004 Christian Limpach. 74 * All rights reserved. 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions 78 * are met: 79 * 1. Redistributions of source code must retain the above copyright 80 * notice, this list of conditions and the following disclaimer. 81 * 2. Redistributions in binary form must reproduce the above copyright 82 * notice, this list of conditions and the following disclaimer in the 83 * documentation and/or other materials provided with the distribution. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 86 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 87 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 89 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 90 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 91 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 92 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 93 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 94 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 95 */ 96 97 #include <sys/cdefs.h> 98 __KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.80 2018/07/27 10:04:22 maxv Exp $"); 99 100 #include "opt_xen.h" 101 #include "opt_ddb.h" 102 #include "ksyms.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/mutex.h> 107 #include <sys/cpu.h> 108 109 #include <uvm/uvm.h> 110 111 #include <x86/pmap.h> 112 #include <machine/gdt.h> 113 #include <xen/xenfunc.h> 114 115 #include <dev/isa/isareg.h> 116 #include <machine/isa_machdep.h> 117 118 #ifdef XENDEBUG 119 #define __PRINTK(x) printk x 120 #else 121 #define __PRINTK(x) 122 #endif 123 124 /* Xen requires the start_info struct to be page aligned */ 125 union start_info_union start_info_union __aligned(PAGE_SIZE); 126 127 volatile shared_info_t *HYPERVISOR_shared_info __read_mostly; 128 unsigned long *xpmap_phys_to_machine_mapping __read_mostly; 129 kmutex_t pte_lock __cacheline_aligned; 130 vaddr_t xen_dummy_page; 131 pt_entry_t xpmap_pg_nx __read_mostly; 132 133 #define XPQUEUE_SIZE 2048 134 static mmu_update_t xpq_queue_array[MAXCPUS][XPQUEUE_SIZE]; 135 136 void xen_failsafe_handler(void); 137 138 extern volatile struct xencons_interface *xencons_interface; /* XXX */ 139 extern struct xenstore_domain_interface *xenstore_interface; /* XXX */ 140 141 static void xen_bt_set_readonly(vaddr_t); 142 static void xen_bootstrap_tables(vaddr_t, vaddr_t, size_t, size_t, bool); 143 144 vaddr_t xen_locore(void); 145 146 /* 147 * kcpuset internally uses an array of uint32_t while xen uses an array of 148 * u_long. As we're little-endian we can cast one to the other. 149 */ 150 typedef union { 151 #ifdef _LP64 152 uint32_t xcpum_km[2]; 153 #else 154 uint32_t xcpum_km[1]; 155 #endif 156 u_long xcpum_xm; 157 } xcpumask_t; 158 159 void 160 xen_failsafe_handler(void) 161 { 162 163 panic("xen_failsafe_handler called!\n"); 164 } 165 166 void 167 xen_set_ldt(vaddr_t base, uint32_t entries) 168 { 169 vaddr_t va; 170 vaddr_t end; 171 pt_entry_t *ptp; 172 int s; 173 174 #ifdef __x86_64__ 175 end = base + (entries << 3); 176 #else 177 end = base + entries * sizeof(union descriptor); 178 #endif 179 180 for (va = base; va < end; va += PAGE_SIZE) { 181 KASSERT(va >= VM_MIN_KERNEL_ADDRESS); 182 ptp = kvtopte(va); 183 pmap_pte_clearbits(ptp, PG_RW); 184 } 185 s = splvm(); /* XXXSMP */ 186 xpq_queue_set_ldt(base, entries); 187 splx(s); 188 } 189 190 void 191 xpq_flush_queue(void) 192 { 193 mmu_update_t *xpq_queue; 194 int done = 0, ret; 195 size_t xpq_idx; 196 197 xpq_idx = curcpu()->ci_xpq_idx; 198 xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 199 200 retry: 201 ret = HYPERVISOR_mmu_update(xpq_queue, xpq_idx, &done, DOMID_SELF); 202 203 if (ret < 0 && xpq_idx != 0) { 204 printf("xpq_flush_queue: %zu entries (%d successful) on " 205 "cpu%d (%ld)\n", 206 xpq_idx, done, curcpu()->ci_index, curcpu()->ci_cpuid); 207 208 if (done != 0) { 209 xpq_queue += done; 210 xpq_idx -= done; 211 done = 0; 212 goto retry; 213 } 214 215 panic("HYPERVISOR_mmu_update failed, ret: %d\n", ret); 216 } 217 curcpu()->ci_xpq_idx = 0; 218 } 219 220 static inline void 221 xpq_increment_idx(void) 222 { 223 224 if (__predict_false(++curcpu()->ci_xpq_idx == XPQUEUE_SIZE)) 225 xpq_flush_queue(); 226 } 227 228 void 229 xpq_queue_machphys_update(paddr_t ma, paddr_t pa) 230 { 231 mmu_update_t *xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 232 size_t xpq_idx = curcpu()->ci_xpq_idx; 233 234 xpq_queue[xpq_idx].ptr = ma | MMU_MACHPHYS_UPDATE; 235 xpq_queue[xpq_idx].val = pa >> PAGE_SHIFT; 236 xpq_increment_idx(); 237 } 238 239 void 240 xpq_queue_pte_update(paddr_t ptr, pt_entry_t val) 241 { 242 mmu_update_t *xpq_queue = xpq_queue_array[curcpu()->ci_cpuid]; 243 size_t xpq_idx = curcpu()->ci_xpq_idx; 244 245 xpq_queue[xpq_idx].ptr = ptr | MMU_NORMAL_PT_UPDATE; 246 xpq_queue[xpq_idx].val = val; 247 xpq_increment_idx(); 248 } 249 250 void 251 xpq_queue_pt_switch(paddr_t pa) 252 { 253 struct mmuext_op op; 254 255 xpq_flush_queue(); 256 257 op.cmd = MMUEXT_NEW_BASEPTR; 258 op.arg1.mfn = pa >> PAGE_SHIFT; 259 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 260 panic(__func__); 261 } 262 263 void 264 xpq_queue_pin_table(paddr_t pa, int lvl) 265 { 266 struct mmuext_op op; 267 268 xpq_flush_queue(); 269 270 op.cmd = lvl; 271 op.arg1.mfn = pa >> PAGE_SHIFT; 272 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 273 panic(__func__); 274 } 275 276 void 277 xpq_queue_unpin_table(paddr_t pa) 278 { 279 struct mmuext_op op; 280 281 xpq_flush_queue(); 282 283 op.cmd = MMUEXT_UNPIN_TABLE; 284 op.arg1.mfn = pa >> PAGE_SHIFT; 285 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 286 panic(__func__); 287 } 288 289 void 290 xpq_queue_set_ldt(vaddr_t va, uint32_t entries) 291 { 292 struct mmuext_op op; 293 294 xpq_flush_queue(); 295 296 KASSERT(va == (va & ~PAGE_MASK)); 297 op.cmd = MMUEXT_SET_LDT; 298 op.arg1.linear_addr = va; 299 op.arg2.nr_ents = entries; 300 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 301 panic(__func__); 302 } 303 304 void 305 xpq_queue_tlb_flush(void) 306 { 307 struct mmuext_op op; 308 309 xpq_flush_queue(); 310 311 op.cmd = MMUEXT_TLB_FLUSH_LOCAL; 312 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 313 panic(__func__); 314 } 315 316 void 317 xpq_flush_cache(void) 318 { 319 int s = splvm(); /* XXXSMP */ 320 321 xpq_flush_queue(); 322 323 asm("wbinvd":::"memory"); 324 splx(s); /* XXX: removeme */ 325 } 326 327 void 328 xpq_queue_invlpg(vaddr_t va) 329 { 330 struct mmuext_op op; 331 332 xpq_flush_queue(); 333 334 op.cmd = MMUEXT_INVLPG_LOCAL; 335 op.arg1.linear_addr = (va & ~PAGE_MASK); 336 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 337 panic(__func__); 338 } 339 340 void 341 xen_mcast_invlpg(vaddr_t va, kcpuset_t *kc) 342 { 343 xcpumask_t xcpumask; 344 mmuext_op_t op; 345 346 kcpuset_export_u32(kc, &xcpumask.xcpum_km[0], sizeof(xcpumask)); 347 348 xpq_flush_queue(); 349 350 op.cmd = MMUEXT_INVLPG_MULTI; 351 op.arg1.linear_addr = va; 352 op.arg2.vcpumask = &xcpumask.xcpum_xm; 353 354 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 355 panic(__func__); 356 } 357 358 void 359 xen_bcast_invlpg(vaddr_t va) 360 { 361 mmuext_op_t op; 362 363 xpq_flush_queue(); 364 365 op.cmd = MMUEXT_INVLPG_ALL; 366 op.arg1.linear_addr = va; 367 368 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 369 panic(__func__); 370 } 371 372 /* This is a synchronous call. */ 373 void 374 xen_mcast_tlbflush(kcpuset_t *kc) 375 { 376 xcpumask_t xcpumask; 377 mmuext_op_t op; 378 379 kcpuset_export_u32(kc, &xcpumask.xcpum_km[0], sizeof(xcpumask)); 380 381 xpq_flush_queue(); 382 383 op.cmd = MMUEXT_TLB_FLUSH_MULTI; 384 op.arg2.vcpumask = &xcpumask.xcpum_xm; 385 386 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 387 panic(__func__); 388 } 389 390 /* This is a synchronous call. */ 391 void 392 xen_bcast_tlbflush(void) 393 { 394 mmuext_op_t op; 395 396 xpq_flush_queue(); 397 398 op.cmd = MMUEXT_TLB_FLUSH_ALL; 399 400 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 401 panic(__func__); 402 } 403 404 void 405 xen_copy_page(paddr_t srcpa, paddr_t dstpa) 406 { 407 mmuext_op_t op; 408 409 op.cmd = MMUEXT_COPY_PAGE; 410 op.arg1.mfn = xpmap_ptom(dstpa) >> PAGE_SHIFT; 411 op.arg2.src_mfn = xpmap_ptom(srcpa) >> PAGE_SHIFT; 412 413 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 414 panic(__func__); 415 } 416 417 void 418 xen_pagezero(paddr_t pa) 419 { 420 mmuext_op_t op; 421 422 op.cmd = MMUEXT_CLEAR_PAGE; 423 op.arg1.mfn = xpmap_ptom(pa) >> PAGE_SHIFT; 424 425 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 426 panic(__func__); 427 } 428 429 int 430 xpq_update_foreign(paddr_t ptr, pt_entry_t val, int dom) 431 { 432 mmu_update_t op; 433 int ok; 434 435 xpq_flush_queue(); 436 437 op.ptr = ptr; 438 op.val = val; 439 if (HYPERVISOR_mmu_update(&op, 1, &ok, dom) < 0) 440 return EFAULT; 441 return 0; 442 } 443 444 #if L2_SLOT_KERNBASE > 0 445 #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) 446 #else 447 #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) 448 #endif 449 450 #ifdef __x86_64__ 451 #define PDIRSZ PTP_LEVELS 452 #else 453 /* 454 * For PAE, we consider a single contiguous L2 "superpage" of 4 pages, all of 455 * them mapped by the L3 page. We also need a shadow page for L3[3]. 456 * XXX so why 6? 457 */ 458 #define PDIRSZ 6 459 #endif 460 461 /* 462 * Xen locore: get rid of the Xen bootstrap tables. Build and switch to new page 463 * tables. 464 * 465 * Virtual address space of the kernel when leaving this function: 466 * +--------------+------------------+-------------+------------+--------------- 467 * | KERNEL IMAGE | BOOTSTRAP TABLES | PROC0 UAREA | DUMMY PAGE | HYPER. SHARED 468 * +--------------+------------------+-------------+------------+--------------- 469 * 470 * ------+-----------------+-------------+ 471 * INFO | EARLY ZERO PAGE | ISA I/O MEM | 472 * ------+-----------------+-------------+ 473 * 474 * DUMMY PAGE is either a PDG for amd64 or a GDT for i386. 475 * 476 * (HYPER. SHARED INFO + EARLY ZERO PAGE + ISA I/O MEM) have no physical 477 * addresses preallocated. 478 */ 479 vaddr_t 480 xen_locore(void) 481 { 482 size_t nL2, oldcount, mapsize; 483 vaddr_t our_tables, xen_tables; 484 u_int descs[4]; 485 486 xen_init_features(); 487 488 xpmap_phys_to_machine_mapping = 489 (unsigned long *)xen_start_info.mfn_list; 490 491 /* Set the NX/XD bit, if available. descs[3] = %edx. */ 492 x86_cpuid(0x80000001, descs); 493 xpmap_pg_nx = (descs[3] & CPUID_NOX) ? PG_NX : 0; 494 495 /* Space after Xen boostrap tables should be free */ 496 xen_tables = xen_start_info.pt_base; 497 our_tables = xen_tables + (xen_start_info.nr_pt_frames * PAGE_SIZE); 498 499 /* 500 * Calculate how much space we need. First, everything mapped before 501 * the Xen bootstrap tables. 502 */ 503 mapsize = xen_tables - KERNTEXTOFF; 504 505 /* After the tables we'll have: 506 * - UAREA 507 * - dummy user PGD (x86_64) 508 * - HYPERVISOR_shared_info 509 * - early_zerop 510 * - ISA I/O mem (if needed) 511 */ 512 mapsize += UPAGES * PAGE_SIZE; 513 #ifdef __x86_64__ 514 mapsize += PAGE_SIZE; 515 #endif 516 mapsize += PAGE_SIZE; 517 mapsize += PAGE_SIZE; 518 #ifdef DOM0OPS 519 if (xendomain_is_dom0()) { 520 mapsize += IOM_SIZE; 521 } 522 #endif 523 524 /* 525 * At this point, mapsize doesn't include the table size. 526 */ 527 #ifdef __x86_64__ 528 nL2 = TABLE_L2_ENTRIES; 529 #else 530 nL2 = (mapsize + (NBPD_L2 - 1)) >> L2_SHIFT; 531 #endif 532 533 /* 534 * Now compute how many L2 pages we need exactly. This is useful only 535 * on i386, since the initial count for amd64 is already enough. 536 */ 537 while (KERNTEXTOFF + mapsize + (nL2 + PDIRSZ) * PAGE_SIZE > 538 KERNBASE + (nL2 << L2_SHIFT)) { 539 nL2++; 540 } 541 542 #ifdef i386 543 /* 544 * One more L2 page: we'll allocate several pages after kva_start 545 * in pmap_bootstrap() before pmap_growkernel(), which have not been 546 * counted here. It's not a big issue to allocate one more L2 as 547 * pmap_growkernel() will be called anyway. 548 */ 549 nL2++; 550 nkptp[1] = nL2; 551 #endif 552 553 /* 554 * Install bootstrap pages. We may need more L2 pages than will 555 * have the final table here, as it's installed after the final table. 556 */ 557 oldcount = nL2; 558 559 bootstrap_again: 560 561 /* 562 * Xen space we'll reclaim may not be enough for our new page tables, 563 * move bootstrap tables if necessary. 564 */ 565 if (our_tables < xen_tables + ((nL2 + PDIRSZ) * PAGE_SIZE)) 566 our_tables = xen_tables + ((nL2 + PDIRSZ) * PAGE_SIZE); 567 568 /* 569 * Make sure the number of L2 pages we have is enough to map everything 570 * from KERNBASE to the bootstrap tables themselves. 571 */ 572 if (our_tables + ((oldcount + PDIRSZ) * PAGE_SIZE) > 573 KERNBASE + (oldcount << L2_SHIFT)) { 574 oldcount++; 575 goto bootstrap_again; 576 } 577 578 /* Create temporary tables */ 579 xen_bootstrap_tables(xen_tables, our_tables, 580 xen_start_info.nr_pt_frames, oldcount, false); 581 582 /* Create final tables */ 583 xen_bootstrap_tables(our_tables, xen_tables, 584 oldcount + PDIRSZ, nL2, true); 585 586 /* Zero out PROC0 UAREA and DUMMY PAGE. */ 587 memset((void *)(xen_tables + ((nL2 + PDIRSZ) * PAGE_SIZE)), 0, 588 (UPAGES + 1) * PAGE_SIZE); 589 590 /* Finally, flush TLB. */ 591 xpq_queue_tlb_flush(); 592 593 return (xen_tables + ((nL2 + PDIRSZ) * PAGE_SIZE)); 594 } 595 596 /* 597 * Build a new table and switch to it. 598 * old_count is # of old tables (including PGD, PDTPE and PDE). 599 * new_count is # of new tables (PTE only). 600 * We assume the areas don't overlap. 601 */ 602 static void 603 xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count, 604 size_t new_count, bool final) 605 { 606 pd_entry_t *pdtpe, *pde, *pte; 607 pd_entry_t *bt_pgd; 608 paddr_t addr; 609 vaddr_t page, avail, map_end; 610 int i; 611 extern char __rodata_start; 612 extern char __data_start; 613 extern char __kernel_end; 614 extern char *early_zerop; /* from pmap.c */ 615 #ifdef i386 616 extern union descriptor tmpgdt[]; 617 #endif 618 619 /* 620 * Layout of RW area after the kernel image: 621 * xencons_interface (if present) 622 * xenstore_interface (if present) 623 * table pages (new_count + PDIRSZ entries) 624 * Extra mappings (only when final is true): 625 * UAREA 626 * dummy user PGD (x86_64 only) / GDT page (i386 only) 627 * HYPERVISOR_shared_info 628 * early_zerop 629 * ISA I/O mem (if needed) 630 */ 631 map_end = new_pgd + ((new_count + PDIRSZ) * PAGE_SIZE); 632 if (final) { 633 map_end += UPAGES * PAGE_SIZE; 634 xen_dummy_page = (vaddr_t)map_end; 635 map_end += PAGE_SIZE; 636 HYPERVISOR_shared_info = (shared_info_t *)map_end; 637 map_end += PAGE_SIZE; 638 early_zerop = (char *)map_end; 639 map_end += PAGE_SIZE; 640 } 641 642 /* 643 * We always set atdevbase, as it's used by init386 to find the first 644 * available VA. map_end is updated only if we are dom0, so 645 * atdevbase -> atdevbase + IOM_SIZE will be mapped only in 646 * this case. 647 */ 648 if (final) { 649 atdevbase = map_end; 650 #ifdef DOM0OPS 651 if (xendomain_is_dom0()) { 652 /* ISA I/O mem */ 653 map_end += IOM_SIZE; 654 } 655 #endif 656 } 657 658 __PRINTK(("xen_bootstrap_tables map_end 0x%lx\n", map_end)); 659 __PRINTK(("console %#lx ", xen_start_info.console_mfn)); 660 __PRINTK(("xenstore %#" PRIx32 "\n", xen_start_info.store_mfn)); 661 662 /* 663 * Create bootstrap page tables. What we need: 664 * - a PGD (level 4) 665 * - a PDTPE (level 3) 666 * - a PDE (level 2) 667 * - some PTEs (level 1) 668 */ 669 670 bt_pgd = (pd_entry_t *)new_pgd; 671 memset(bt_pgd, 0, PAGE_SIZE); 672 avail = new_pgd + PAGE_SIZE; 673 674 #ifdef __x86_64__ 675 /* Per-cpu L4 */ 676 pd_entry_t *bt_cpu_pgd = bt_pgd; 677 /* pmap_kernel() "shadow" L4 */ 678 bt_pgd = (pd_entry_t *)avail; 679 memset(bt_pgd, 0, PAGE_SIZE); 680 avail += PAGE_SIZE; 681 682 /* Install L3 */ 683 pdtpe = (pd_entry_t *)avail; 684 memset(pdtpe, 0, PAGE_SIZE); 685 avail += PAGE_SIZE; 686 687 addr = ((u_long)pdtpe) - KERNBASE; 688 bt_pgd[pl4_pi(KERNTEXTOFF)] = bt_cpu_pgd[pl4_pi(KERNTEXTOFF)] = 689 xpmap_ptom_masked(addr) | PG_V | PG_RW; 690 691 /* Level 2 */ 692 pde = (pd_entry_t *)avail; 693 memset(pde, 0, PAGE_SIZE); 694 avail += PAGE_SIZE; 695 696 addr = ((u_long)pde) - KERNBASE; 697 pdtpe[pl3_pi(KERNTEXTOFF)] = 698 xpmap_ptom_masked(addr) | PG_V | PG_RW; 699 #else 700 pdtpe = bt_pgd; 701 702 /* 703 * Our PAE-style level 2, 5 contiguous pages (4 L2 + 1 shadow). 704 * +-----------------+----------------+---------+ 705 * Physical layout: | 3 * USERLAND L2 | L2 KERN SHADOW | L2 KERN | 706 * +-----------------+----------------+---------+ 707 * However, we enter pdtpte[3] into L2 KERN, and not L2 KERN SHADOW. 708 * This way, pde[L2_SLOT_KERN] always points to the shadow. 709 */ 710 pde = (pd_entry_t *)avail; 711 memset(pde, 0, PAGE_SIZE * 5); 712 avail += PAGE_SIZE * 5; 713 714 /* 715 * Link L2 pages in L3, with a special case for L2 KERN. Xen doesn't 716 * want RW permissions in L3 entries, it'll add them itself. 717 */ 718 addr = ((u_long)pde) - KERNBASE; 719 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 720 pdtpe[i] = xpmap_ptom_masked(addr) | PG_V; 721 } 722 addr += PAGE_SIZE; 723 pdtpe[3] = xpmap_ptom_masked(addr) | PG_V; 724 #endif 725 726 /* Level 1 */ 727 page = KERNTEXTOFF; 728 for (i = 0; i < new_count; i ++) { 729 vaddr_t cur_page = page; 730 731 pte = (pd_entry_t *)avail; 732 avail += PAGE_SIZE; 733 734 memset(pte, 0, PAGE_SIZE); 735 while (pl2_pi(page) == pl2_pi(cur_page)) { 736 if (page >= map_end) { 737 /* not mapped at all */ 738 pte[pl1_pi(page)] = 0; 739 page += PAGE_SIZE; 740 continue; 741 } 742 pte[pl1_pi(page)] = xpmap_ptom_masked(page - KERNBASE); 743 if (page == (vaddr_t)HYPERVISOR_shared_info) { 744 pte[pl1_pi(page)] = xen_start_info.shared_info; 745 } 746 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 747 == xen_start_info.console.domU.mfn) { 748 xencons_interface = (void *)page; 749 pte[pl1_pi(page)] = xen_start_info.console_mfn; 750 pte[pl1_pi(page)] <<= PAGE_SHIFT; 751 } 752 if ((xpmap_ptom_masked(page - KERNBASE) >> PAGE_SHIFT) 753 == xen_start_info.store_mfn) { 754 xenstore_interface = (void *)page; 755 pte[pl1_pi(page)] = xen_start_info.store_mfn; 756 pte[pl1_pi(page)] <<= PAGE_SHIFT; 757 } 758 #ifdef DOM0OPS 759 if (page >= (vaddr_t)atdevbase && 760 page < (vaddr_t)atdevbase + IOM_SIZE) { 761 pte[pl1_pi(page)] = 762 IOM_BEGIN + (page - (vaddr_t)atdevbase); 763 pte[pl1_pi(page)] |= xpmap_pg_nx; 764 } 765 #endif 766 767 pte[pl1_pi(page)] |= PG_V; 768 if (page < (vaddr_t)&__rodata_start) { 769 /* Map the kernel text RX. */ 770 pte[pl1_pi(page)] |= PG_RO; 771 } else if (page >= (vaddr_t)&__rodata_start && 772 page < (vaddr_t)&__data_start) { 773 /* Map the kernel rodata R. */ 774 pte[pl1_pi(page)] |= PG_RO | xpmap_pg_nx; 775 } else if (page >= old_pgd && 776 page < old_pgd + (old_count * PAGE_SIZE)) { 777 /* Map the old page tables R. */ 778 pte[pl1_pi(page)] |= PG_RO | xpmap_pg_nx; 779 } else if (page >= new_pgd && 780 page < new_pgd + ((new_count + PDIRSZ) * PAGE_SIZE)) { 781 /* Map the new page tables R. */ 782 pte[pl1_pi(page)] |= PG_RO | xpmap_pg_nx; 783 #ifdef i386 784 } else if (page == (vaddr_t)tmpgdt) { 785 /* 786 * Map bootstrap gdt R/O. Later, we will re-add 787 * this page to uvm after making it writable. 788 */ 789 pte[pl1_pi(page)] = 0; 790 page += PAGE_SIZE; 791 continue; 792 #endif 793 } else if (page >= (vaddr_t)&__data_start && 794 page < (vaddr_t)&__kernel_end) { 795 /* Map the kernel data+bss RW. */ 796 pte[pl1_pi(page)] |= PG_RW | xpmap_pg_nx; 797 } else { 798 /* Map the page RW. */ 799 pte[pl1_pi(page)] |= PG_RW | xpmap_pg_nx; 800 } 801 802 page += PAGE_SIZE; 803 } 804 805 addr = ((u_long)pte) - KERNBASE; 806 pde[pl2_pi(cur_page)] = 807 xpmap_ptom_masked(addr) | PG_RW | PG_V; 808 809 /* Mark readonly */ 810 xen_bt_set_readonly((vaddr_t)pte); 811 } 812 813 /* Install recursive page tables mapping */ 814 #ifdef __x86_64__ 815 /* Recursive entry in pmap_kernel(). */ 816 bt_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_pgd - KERNBASE) 817 | PG_RO | PG_V | xpmap_pg_nx; 818 /* Recursive entry in higher-level per-cpu PD. */ 819 bt_cpu_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_cpu_pgd - KERNBASE) 820 | PG_RO | PG_V | xpmap_pg_nx; 821 822 /* Mark tables RO */ 823 xen_bt_set_readonly((vaddr_t)pde); 824 #else 825 /* Copy L2 KERN into L2 KERN SHADOW, and reference the latter in cpu0. */ 826 memcpy(&pde[L2_SLOT_KERN + NPDPG], &pde[L2_SLOT_KERN], PAGE_SIZE); 827 cpu_info_primary.ci_kpm_pdir = &pde[L2_SLOT_KERN + NPDPG]; 828 cpu_info_primary.ci_kpm_pdirpa = 829 (vaddr_t)cpu_info_primary.ci_kpm_pdir - KERNBASE; 830 831 /* 832 * We don't enter a recursive entry from the L3 PD. Instead, we enter 833 * the first 4 L2 pages, which includes the kernel's L2 shadow. But we 834 * have to enter the shadow after switching %cr3, or Xen will refcount 835 * some PTEs with the wrong type. 836 */ 837 addr = (u_long)pde - KERNBASE; 838 for (i = 0; i < 3; i++, addr += PAGE_SIZE) { 839 pde[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_V | 840 xpmap_pg_nx; 841 } 842 843 /* Mark tables RO, and pin L2 KERN SHADOW. */ 844 addr = (u_long)pde - KERNBASE; 845 for (i = 0; i < 5; i++, addr += PAGE_SIZE) { 846 xen_bt_set_readonly(((vaddr_t)pde) + PAGE_SIZE * i); 847 } 848 if (final) { 849 addr = (u_long)pde - KERNBASE + 3 * PAGE_SIZE; 850 xpq_queue_pin_l2_table(xpmap_ptom_masked(addr)); 851 } 852 #endif 853 854 xen_bt_set_readonly((vaddr_t)pdtpe); 855 #ifdef __x86_64__ 856 xen_bt_set_readonly(new_pgd); 857 #endif 858 859 /* Pin the PGD */ 860 #ifdef __x86_64__ 861 xpq_queue_pin_l4_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 862 #else 863 xpq_queue_pin_l3_table(xpmap_ptom_masked(new_pgd - KERNBASE)); 864 #endif 865 866 /* Save phys. addr of PDP, for libkvm. */ 867 #ifdef __x86_64__ 868 PDPpaddr = (u_long)bt_pgd - KERNBASE; 869 #else 870 PDPpaddr = (u_long)pde - KERNBASE; /* PDP is the L2 with PAE */ 871 #endif 872 873 /* Switch to new tables */ 874 xpq_queue_pt_switch(xpmap_ptom_masked(new_pgd - KERNBASE)); 875 876 if (final) { 877 #ifdef __x86_64__ 878 /* Save the address of the real per-cpu L4 page. */ 879 cpu_info_primary.ci_kpm_pdir = bt_cpu_pgd; 880 cpu_info_primary.ci_kpm_pdirpa = ((paddr_t)bt_cpu_pgd - KERNBASE); 881 #else 882 /* Save the address of the L3 page */ 883 cpu_info_primary.ci_pae_l3_pdir = pdtpe; 884 cpu_info_primary.ci_pae_l3_pdirpa = (new_pgd - KERNBASE); 885 886 /* Now enter the kernel's PTE mappings */ 887 addr = (u_long)pde - KERNBASE + PAGE_SIZE * 3; 888 xpq_queue_pte_update( 889 xpmap_ptom(((vaddr_t)&pde[PDIR_SLOT_PTE + 3]) - KERNBASE), 890 xpmap_ptom_masked(addr) | PG_V); 891 xpq_flush_queue(); 892 #endif 893 } 894 895 /* 896 * Now we can safely reclaim the space taken by the old tables. 897 */ 898 899 /* Unpin old PGD */ 900 xpq_queue_unpin_table(xpmap_ptom_masked(old_pgd - KERNBASE)); 901 902 /* Mark old tables RW */ 903 page = old_pgd; 904 addr = xpmap_mtop((paddr_t)pde[pl2_pi(page)] & PG_FRAME); 905 pte = (pd_entry_t *)((u_long)addr + KERNBASE); 906 pte += pl1_pi(page); 907 while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) { 908 addr = xpmap_ptom(((u_long)pte) - KERNBASE); 909 xpq_queue_pte_update(addr, *pte | PG_RW); 910 page += PAGE_SIZE; 911 /* 912 * Our PTEs are contiguous so it's safe to just "++" here. 913 */ 914 pte++; 915 } 916 xpq_flush_queue(); 917 } 918 919 /* 920 * Mark a page read-only, assuming vaddr = paddr + KERNBASE. 921 */ 922 static void 923 xen_bt_set_readonly(vaddr_t page) 924 { 925 pt_entry_t entry; 926 927 entry = xpmap_ptom_masked(page - KERNBASE); 928 entry |= PG_V | xpmap_pg_nx; 929 930 HYPERVISOR_update_va_mapping(page, entry, UVMF_INVLPG); 931 } 932 933 #ifdef __x86_64__ 934 void 935 xen_set_user_pgd(paddr_t page) 936 { 937 struct mmuext_op op; 938 int s = splvm(); /* XXXSMP */ 939 940 xpq_flush_queue(); 941 op.cmd = MMUEXT_NEW_USER_BASEPTR; 942 op.arg1.mfn = xpmap_ptom_masked(page) >> PAGE_SHIFT; 943 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) 944 panic("xen_set_user_pgd: failed to install new user page" 945 " directory %#" PRIxPADDR, page); 946 splx(s); 947 } 948 #endif /* __x86_64__ */ 949
Indexes created Tue Sep 30 10:09:55 GMT 2025