xen_intr.c revision 1.29 1 1.29 andvar /* $NetBSD: xen_intr.c,v 1.29 2021/08/09 21:20:50 andvar Exp $ */
2 1.2 bouyer
3 1.2 bouyer /*-
4 1.2 bouyer * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
5 1.2 bouyer * All rights reserved.
6 1.2 bouyer *
7 1.2 bouyer * This code is derived from software contributed to The NetBSD Foundation
8 1.2 bouyer * by Charles M. Hannum, and by Jason R. Thorpe.
9 1.2 bouyer *
10 1.2 bouyer * Redistribution and use in source and binary forms, with or without
11 1.2 bouyer * modification, are permitted provided that the following conditions
12 1.2 bouyer * are met:
13 1.2 bouyer * 1. Redistributions of source code must retain the above copyright
14 1.2 bouyer * notice, this list of conditions and the following disclaimer.
15 1.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright
16 1.2 bouyer * notice, this list of conditions and the following disclaimer in the
17 1.2 bouyer * documentation and/or other materials provided with the distribution.
18 1.2 bouyer *
19 1.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.2 bouyer * POSSIBILITY OF SUCH DAMAGE.
30 1.2 bouyer */
31 1.2 bouyer
32 1.2 bouyer #include <sys/cdefs.h>
33 1.29 andvar __KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.29 2021/08/09 21:20:50 andvar Exp $");
34 1.19 ad
35 1.19 ad #include "opt_multiprocessor.h"
36 1.28 jdolecek #include "opt_pci.h"
37 1.2 bouyer
38 1.2 bouyer #include <sys/param.h>
39 1.10 cherry #include <sys/kernel.h>
40 1.10 cherry #include <sys/kmem.h>
41 1.11 cherry #include <sys/cpu.h>
42 1.19 ad #include <sys/device.h>
43 1.11 cherry
44 1.24 bouyer #include <xen/intr.h>
45 1.10 cherry #include <xen/evtchn.h>
46 1.15 cherry #include <xen/xenfunc.h>
47 1.2 bouyer
48 1.12 cherry #include <uvm/uvm.h>
49 1.12 cherry
50 1.2 bouyer #include <machine/cpu.h>
51 1.2 bouyer #include <machine/intr.h>
52 1.2 bouyer
53 1.11 cherry #include "acpica.h"
54 1.11 cherry #include "ioapic.h"
55 1.11 cherry #include "lapic.h"
56 1.11 cherry #include "pci.h"
57 1.11 cherry
58 1.11 cherry #if NACPICA > 0
59 1.11 cherry #include <dev/acpi/acpivar.h>
60 1.11 cherry #endif
61 1.11 cherry
62 1.11 cherry #if NIOAPIC > 0 || NACPICA > 0
63 1.11 cherry #include <machine/i82093var.h>
64 1.11 cherry #endif
65 1.11 cherry
66 1.11 cherry #if NLAPIC > 0
67 1.11 cherry #include <machine/i82489var.h>
68 1.11 cherry #endif
69 1.11 cherry
70 1.11 cherry #if NPCI > 0
71 1.11 cherry #include <dev/pci/ppbreg.h>
72 1.23 jdolecek #ifdef __HAVE_PCI_MSI_MSIX
73 1.23 jdolecek #include <x86/pci/msipic.h>
74 1.23 jdolecek #include <x86/pci/pci_msi_machdep.h>
75 1.23 jdolecek #endif
76 1.11 cherry #endif
77 1.11 cherry
78 1.19 ad #if defined(MULTIPROCESSOR)
79 1.19 ad static const char *xen_ipi_names[XEN_NIPIS] = XEN_IPI_NAMES;
80 1.19 ad #endif
81 1.19 ad
82 1.17 cherry #if !defined(XENPVHVM)
83 1.2 bouyer void
84 1.16 bouyer x86_disable_intr(void)
85 1.2 bouyer {
86 1.16 bouyer curcpu()->ci_vcpu->evtchn_upcall_mask = 1;
87 1.16 bouyer x86_lfence();
88 1.2 bouyer }
89 1.2 bouyer
90 1.2 bouyer void
91 1.16 bouyer x86_enable_intr(void)
92 1.2 bouyer {
93 1.16 bouyer volatile struct vcpu_info *_vci = curcpu()->ci_vcpu;
94 1.16 bouyer __insn_barrier();
95 1.16 bouyer _vci->evtchn_upcall_mask = 0;
96 1.16 bouyer x86_lfence(); /* unmask then check (avoid races) */
97 1.16 bouyer if (__predict_false(_vci->evtchn_upcall_pending))
98 1.16 bouyer hypervisor_force_callback();
99 1.2 bouyer }
100 1.2 bouyer
101 1.17 cherry #endif /* !XENPVHVM */
102 1.17 cherry
103 1.2 bouyer u_long
104 1.11 cherry xen_read_psl(void)
105 1.2 bouyer {
106 1.2 bouyer
107 1.4 cegger return (curcpu()->ci_vcpu->evtchn_upcall_mask);
108 1.2 bouyer }
109 1.2 bouyer
110 1.2 bouyer void
111 1.11 cherry xen_write_psl(u_long psl)
112 1.2 bouyer {
113 1.4 cegger struct cpu_info *ci = curcpu();
114 1.2 bouyer
115 1.4 cegger ci->ci_vcpu->evtchn_upcall_mask = psl;
116 1.9 jym xen_rmb();
117 1.4 cegger if (ci->ci_vcpu->evtchn_upcall_pending && psl == 0) {
118 1.2 bouyer hypervisor_force_callback();
119 1.2 bouyer }
120 1.2 bouyer }
121 1.10 cherry
122 1.10 cherry void *
123 1.10 cherry xen_intr_establish(int legacy_irq, struct pic *pic, int pin,
124 1.10 cherry int type, int level, int (*handler)(void *), void *arg,
125 1.10 cherry bool known_mpsafe)
126 1.10 cherry {
127 1.10 cherry
128 1.10 cherry return xen_intr_establish_xname(legacy_irq, pic, pin, type, level,
129 1.10 cherry handler, arg, known_mpsafe, "XEN");
130 1.10 cherry }
131 1.10 cherry
132 1.10 cherry void *
133 1.10 cherry xen_intr_establish_xname(int legacy_irq, struct pic *pic, int pin,
134 1.10 cherry int type, int level, int (*handler)(void *), void *arg,
135 1.10 cherry bool known_mpsafe, const char *xname)
136 1.10 cherry {
137 1.10 cherry const char *intrstr;
138 1.10 cherry char intrstr_buf[INTRIDBUF];
139 1.10 cherry
140 1.10 cherry if (pic->pic_type == PIC_XEN) {
141 1.10 cherry struct intrhand *rih;
142 1.10 cherry
143 1.10 cherry intrstr = intr_create_intrid(legacy_irq, pic, pin, intrstr_buf,
144 1.10 cherry sizeof(intrstr_buf));
145 1.10 cherry
146 1.24 bouyer rih = event_set_handler(pin, handler, arg, level,
147 1.27 bouyer intrstr, xname, known_mpsafe, NULL);
148 1.10 cherry
149 1.10 cherry if (rih == NULL) {
150 1.24 bouyer printf("%s: can't establish interrupt\n", __func__);
151 1.10 cherry return NULL;
152 1.10 cherry }
153 1.10 cherry
154 1.10 cherry return rih;
155 1.10 cherry } /* Else we assume pintr */
156 1.10 cherry
157 1.14 cherry #if (NPCI > 0 || NISA > 0) && defined(XENPV) /* XXX: support PVHVM pirq */
158 1.10 cherry struct pintrhand *pih;
159 1.10 cherry int gsi;
160 1.25 jdolecek int evtchn;
161 1.27 bouyer /* the hack below is from x86's intr_establish_xname() */
162 1.27 bouyer bool mpsafe = (known_mpsafe || level != IPL_VM);
163 1.10 cherry
164 1.10 cherry KASSERTMSG(legacy_irq == -1 || (0 <= legacy_irq && legacy_irq < NUM_XEN_IRQS),
165 1.10 cherry "bad legacy IRQ value: %d", legacy_irq);
166 1.10 cherry KASSERTMSG(!(legacy_irq == -1 && pic == &i8259_pic),
167 1.10 cherry "non-legacy IRQon i8259 ");
168 1.10 cherry
169 1.10 cherry gsi = xen_pic_to_gsi(pic, pin);
170 1.25 jdolecek KASSERTMSG(gsi < NR_EVENT_CHANNELS, "gsi %d >= NR_EVENT_CHANNELS %u",
171 1.25 jdolecek gsi, (int)NR_EVENT_CHANNELS);
172 1.10 cherry
173 1.10 cherry intrstr = intr_create_intrid(gsi, pic, pin, intrstr_buf,
174 1.10 cherry sizeof(intrstr_buf));
175 1.10 cherry
176 1.10 cherry if (irq2port[gsi] == 0) {
177 1.10 cherry extern struct cpu_info phycpu_info_primary; /* XXX */
178 1.10 cherry struct cpu_info *ci = &phycpu_info_primary;
179 1.10 cherry
180 1.25 jdolecek pic->pic_addroute(pic, ci, pin, gsi, type);
181 1.10 cherry
182 1.10 cherry evtchn = bind_pirq_to_evtch(gsi);
183 1.10 cherry KASSERT(evtchn > 0);
184 1.10 cherry KASSERT(evtchn < NR_EVENT_CHANNELS);
185 1.10 cherry irq2port[gsi] = evtchn + 1;
186 1.10 cherry xen_atomic_set_bit(&ci->ci_evtmask[0], evtchn);
187 1.10 cherry } else {
188 1.10 cherry /*
189 1.10 cherry * Shared interrupt - we can't rebind.
190 1.10 cherry * The port is shared instead.
191 1.10 cherry */
192 1.10 cherry evtchn = irq2port[gsi] - 1;
193 1.10 cherry }
194 1.10 cherry
195 1.10 cherry pih = pirq_establish(gsi, evtchn, handler, arg, level,
196 1.27 bouyer intrstr, xname, mpsafe);
197 1.24 bouyer pih->pic = pic;
198 1.10 cherry return pih;
199 1.10 cherry #endif /* NPCI > 0 || NISA > 0 */
200 1.10 cherry
201 1.10 cherry /* FALLTHROUGH */
202 1.10 cherry return NULL;
203 1.10 cherry }
204 1.10 cherry
205 1.10 cherry /*
206 1.18 thorpej * Mask an interrupt source.
207 1.18 thorpej */
208 1.18 thorpej void
209 1.18 thorpej xen_intr_mask(struct intrhand *ih)
210 1.18 thorpej {
211 1.18 thorpej /* XXX */
212 1.18 thorpej panic("xen_intr_mask: not yet implemented.");
213 1.18 thorpej }
214 1.18 thorpej
215 1.18 thorpej /*
216 1.18 thorpej * Unmask an interrupt source.
217 1.18 thorpej */
218 1.18 thorpej void
219 1.18 thorpej xen_intr_unmask(struct intrhand *ih)
220 1.18 thorpej {
221 1.18 thorpej /* XXX */
222 1.18 thorpej panic("xen_intr_unmask: not yet implemented.");
223 1.18 thorpej }
224 1.18 thorpej
225 1.18 thorpej /*
226 1.10 cherry * Deregister an interrupt handler.
227 1.10 cherry */
228 1.10 cherry void
229 1.10 cherry xen_intr_disestablish(struct intrhand *ih)
230 1.10 cherry {
231 1.10 cherry
232 1.24 bouyer if (ih->ih_pic->pic_type == PIC_XEN) {
233 1.10 cherry event_remove_handler(ih->ih_pin, ih->ih_realfun,
234 1.10 cherry ih->ih_realarg);
235 1.24 bouyer /* event_remove_handler frees ih */
236 1.10 cherry return;
237 1.10 cherry }
238 1.26 bouyer #if defined(DOM0OPS) && defined(XENPV)
239 1.10 cherry /*
240 1.10 cherry * Cache state, to prevent a use after free situation with
241 1.10 cherry * ih.
242 1.10 cherry */
243 1.10 cherry
244 1.10 cherry struct pintrhand *pih = (struct pintrhand *)ih;
245 1.10 cherry
246 1.10 cherry int pirq = pih->pirq;
247 1.10 cherry int port = pih->evtch;
248 1.10 cherry KASSERT(irq2port[pirq] != 0);
249 1.10 cherry
250 1.10 cherry pirq_disestablish(pih);
251 1.10 cherry
252 1.10 cherry if (evtsource[port] == NULL) {
253 1.10 cherry /*
254 1.10 cherry * Last handler was removed by
255 1.10 cherry * event_remove_handler().
256 1.10 cherry *
257 1.10 cherry * We can safely unbind the pirq now.
258 1.10 cherry */
259 1.10 cherry
260 1.10 cherry port = unbind_pirq_from_evtch(pirq);
261 1.10 cherry KASSERT(port == pih->evtch);
262 1.10 cherry irq2port[pirq] = 0;
263 1.10 cherry }
264 1.10 cherry #endif
265 1.10 cherry return;
266 1.10 cherry }
267 1.10 cherry
268 1.11 cherry /* MI interface for kern_cpu.c */
269 1.11 cherry void xen_cpu_intr_redistribute(void);
270 1.11 cherry
271 1.11 cherry void
272 1.11 cherry xen_cpu_intr_redistribute(void)
273 1.11 cherry {
274 1.11 cherry KASSERT(mutex_owned(&cpu_lock));
275 1.11 cherry KASSERT(mp_online);
276 1.11 cherry
277 1.11 cherry return;
278 1.11 cherry }
279 1.11 cherry
280 1.11 cherry /* MD - called by x86/cpu.c */
281 1.12 cherry #if defined(INTRSTACKSIZE)
282 1.12 cherry static inline bool
283 1.12 cherry redzone_const_or_false(bool x)
284 1.12 cherry {
285 1.12 cherry #ifdef DIAGNOSTIC
286 1.12 cherry return x;
287 1.12 cherry #else
288 1.12 cherry return false;
289 1.12 cherry #endif /* !DIAGNOSTIC */
290 1.12 cherry }
291 1.12 cherry
292 1.12 cherry static inline int
293 1.12 cherry redzone_const_or_zero(int x)
294 1.12 cherry {
295 1.12 cherry return redzone_const_or_false(true) ? x : 0;
296 1.12 cherry }
297 1.12 cherry #endif
298 1.12 cherry
299 1.14 cherry void xen_cpu_intr_init(struct cpu_info *);
300 1.11 cherry void
301 1.14 cherry xen_cpu_intr_init(struct cpu_info *ci)
302 1.11 cherry {
303 1.24 bouyer #if defined(__HAVE_PREEMPTION)
304 1.24 bouyer x86_init_preempt(ci);
305 1.24 bouyer #endif
306 1.24 bouyer x86_intr_calculatemasks(ci);
307 1.11 cherry
308 1.11 cherry #if defined(INTRSTACKSIZE)
309 1.11 cherry vaddr_t istack;
310 1.11 cherry
311 1.11 cherry /*
312 1.11 cherry * If the red zone is activated, protect both the top and
313 1.11 cherry * the bottom of the stack with an unmapped page.
314 1.11 cherry */
315 1.11 cherry istack = uvm_km_alloc(kernel_map,
316 1.11 cherry INTRSTACKSIZE + redzone_const_or_zero(2 * PAGE_SIZE), 0,
317 1.11 cherry UVM_KMF_WIRED|UVM_KMF_ZERO);
318 1.11 cherry if (redzone_const_or_false(true)) {
319 1.11 cherry pmap_kremove(istack, PAGE_SIZE);
320 1.11 cherry pmap_kremove(istack + INTRSTACKSIZE + PAGE_SIZE, PAGE_SIZE);
321 1.11 cherry pmap_update(pmap_kernel());
322 1.11 cherry }
323 1.11 cherry
324 1.11 cherry /*
325 1.11 cherry * 33 used to be 1. Arbitrarily reserve 32 more register_t's
326 1.11 cherry * of space for ddb(4) to examine some subroutine arguments
327 1.11 cherry * and to hunt for the next stack frame.
328 1.11 cherry */
329 1.11 cherry ci->ci_intrstack = (char *)istack + redzone_const_or_zero(PAGE_SIZE) +
330 1.11 cherry INTRSTACKSIZE - 33 * sizeof(register_t);
331 1.11 cherry #endif
332 1.11 cherry
333 1.19 ad #ifdef MULTIPROCESSOR
334 1.24 bouyer for (int i = 0; i < XEN_NIPIS; i++)
335 1.19 ad evcnt_attach_dynamic(&ci->ci_ipi_events[i], EVCNT_TYPE_MISC,
336 1.19 ad NULL, device_xname(ci->ci_dev), xen_ipi_names[i]);
337 1.19 ad #endif
338 1.19 ad
339 1.11 cherry ci->ci_idepth = -1;
340 1.11 cherry }
341 1.11 cherry
342 1.11 cherry /*
343 1.11 cherry * Everything below from here is duplicated from x86/intr.c
344 1.11 cherry * When intr.c and xen_intr.c are unified, these will need to be
345 1.11 cherry * merged.
346 1.11 cherry */
347 1.11 cherry
348 1.11 cherry u_int xen_cpu_intr_count(struct cpu_info *ci);
349 1.11 cherry
350 1.11 cherry u_int
351 1.11 cherry xen_cpu_intr_count(struct cpu_info *ci)
352 1.11 cherry {
353 1.11 cherry
354 1.11 cherry KASSERT(ci->ci_nintrhand >= 0);
355 1.11 cherry
356 1.11 cherry return ci->ci_nintrhand;
357 1.11 cherry }
358 1.11 cherry
359 1.11 cherry static const char *
360 1.11 cherry xen_intr_string(int port, char *buf, size_t len, struct pic *pic)
361 1.11 cherry {
362 1.11 cherry KASSERT(pic->pic_type == PIC_XEN);
363 1.11 cherry
364 1.11 cherry KASSERT(port >= 0);
365 1.11 cherry KASSERT(port < NR_EVENT_CHANNELS);
366 1.11 cherry
367 1.24 bouyer snprintf(buf, len, "%s chan %d", pic->pic_name, port);
368 1.11 cherry
369 1.11 cherry return buf;
370 1.11 cherry }
371 1.11 cherry
372 1.11 cherry static const char *
373 1.11 cherry legacy_intr_string(int ih, char *buf, size_t len, struct pic *pic)
374 1.11 cherry {
375 1.11 cherry int legacy_irq;
376 1.11 cherry
377 1.11 cherry KASSERT(pic->pic_type == PIC_I8259);
378 1.11 cherry #if NLAPIC > 0
379 1.11 cherry KASSERT(APIC_IRQ_ISLEGACY(ih));
380 1.11 cherry
381 1.11 cherry legacy_irq = APIC_IRQ_LEGACY_IRQ(ih);
382 1.11 cherry #else
383 1.11 cherry legacy_irq = ih;
384 1.11 cherry #endif
385 1.11 cherry KASSERT(legacy_irq >= 0 && legacy_irq < 16);
386 1.11 cherry
387 1.11 cherry snprintf(buf, len, "%s pin %d", pic->pic_name, legacy_irq);
388 1.11 cherry
389 1.11 cherry return buf;
390 1.11 cherry }
391 1.11 cherry
392 1.14 cherry const char * xintr_string(intr_handle_t ih, char *buf, size_t len);
393 1.14 cherry
394 1.11 cherry const char *
395 1.14 cherry xintr_string(intr_handle_t ih, char *buf, size_t len)
396 1.11 cherry {
397 1.11 cherry #if NIOAPIC > 0
398 1.11 cherry struct ioapic_softc *pic;
399 1.11 cherry #endif
400 1.11 cherry
401 1.11 cherry if (ih == 0)
402 1.11 cherry panic("%s: bogus handle 0x%" PRIx64, __func__, ih);
403 1.11 cherry
404 1.11 cherry #if NIOAPIC > 0
405 1.11 cherry if (ih & APIC_INT_VIA_APIC) {
406 1.11 cherry pic = ioapic_find(APIC_IRQ_APIC(ih));
407 1.11 cherry if (pic != NULL) {
408 1.11 cherry snprintf(buf, len, "%s pin %d",
409 1.11 cherry device_xname(pic->sc_dev), APIC_IRQ_PIN(ih));
410 1.11 cherry } else {
411 1.11 cherry snprintf(buf, len,
412 1.11 cherry "apic %d int %d (irq %d)",
413 1.11 cherry APIC_IRQ_APIC(ih),
414 1.11 cherry APIC_IRQ_PIN(ih),
415 1.11 cherry APIC_IRQ_LEGACY_IRQ(ih));
416 1.11 cherry }
417 1.11 cherry } else
418 1.11 cherry snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih));
419 1.11 cherry
420 1.11 cherry #elif NLAPIC > 0
421 1.14 cherry snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih));
422 1.11 cherry #else
423 1.11 cherry snprintf(buf, len, "irq %d", (int) ih);
424 1.11 cherry #endif
425 1.11 cherry return buf;
426 1.11 cherry
427 1.11 cherry }
428 1.11 cherry
429 1.11 cherry /*
430 1.11 cherry * Create an interrupt id such as "ioapic0 pin 9". This interrupt id is used
431 1.11 cherry * by MI code and intrctl(8).
432 1.11 cherry */
433 1.14 cherry const char * xen_intr_create_intrid(int legacy_irq, struct pic *pic,
434 1.14 cherry int pin, char *buf, size_t len);
435 1.14 cherry
436 1.11 cherry const char *
437 1.14 cherry xen_intr_create_intrid(int legacy_irq, struct pic *pic, int pin, char *buf, size_t len)
438 1.11 cherry {
439 1.11 cherry int ih = 0;
440 1.11 cherry
441 1.24 bouyer #if NPCI > 0 && defined(XENPV)
442 1.11 cherry #if defined(__HAVE_PCI_MSI_MSIX)
443 1.11 cherry if ((pic->pic_type == PIC_MSI) || (pic->pic_type == PIC_MSIX)) {
444 1.11 cherry uint64_t pih;
445 1.11 cherry int dev, vec;
446 1.11 cherry
447 1.11 cherry dev = msipic_get_devid(pic);
448 1.11 cherry vec = pin;
449 1.11 cherry pih = __SHIFTIN((uint64_t)dev, MSI_INT_DEV_MASK)
450 1.11 cherry | __SHIFTIN((uint64_t)vec, MSI_INT_VEC_MASK)
451 1.11 cherry | APIC_INT_VIA_MSI;
452 1.11 cherry if (pic->pic_type == PIC_MSI)
453 1.11 cherry MSI_INT_MAKE_MSI(pih);
454 1.11 cherry else if (pic->pic_type == PIC_MSIX)
455 1.11 cherry MSI_INT_MAKE_MSIX(pih);
456 1.11 cherry
457 1.11 cherry return x86_pci_msi_string(NULL, pih, buf, len);
458 1.11 cherry }
459 1.11 cherry #endif /* __HAVE_PCI_MSI_MSIX */
460 1.11 cherry #endif
461 1.11 cherry
462 1.11 cherry if (pic->pic_type == PIC_XEN) {
463 1.11 cherry ih = pin; /* Port == pin */
464 1.11 cherry return xen_intr_string(pin, buf, len, pic);
465 1.11 cherry }
466 1.11 cherry
467 1.11 cherry /*
468 1.29 andvar * If the device is pci, "legacy_irq" is always -1. Least 8 bit of "ih"
469 1.11 cherry * is only used in intr_string() to show the irq number.
470 1.11 cherry * If the device is "legacy"(such as floppy), it should not use
471 1.11 cherry * intr_string().
472 1.11 cherry */
473 1.11 cherry if (pic->pic_type == PIC_I8259) {
474 1.11 cherry ih = legacy_irq;
475 1.11 cherry return legacy_intr_string(ih, buf, len, pic);
476 1.11 cherry }
477 1.11 cherry
478 1.11 cherry #if NIOAPIC > 0 || NACPICA > 0
479 1.11 cherry ih = ((pic->pic_apicid << APIC_INT_APIC_SHIFT) & APIC_INT_APIC_MASK)
480 1.11 cherry | ((pin << APIC_INT_PIN_SHIFT) & APIC_INT_PIN_MASK);
481 1.11 cherry if (pic->pic_type == PIC_IOAPIC) {
482 1.11 cherry ih |= APIC_INT_VIA_APIC;
483 1.11 cherry }
484 1.11 cherry ih |= pin;
485 1.11 cherry return intr_string(ih, buf, len);
486 1.11 cherry #endif
487 1.11 cherry
488 1.11 cherry return NULL; /* No pic found! */
489 1.11 cherry }
490 1.11 cherry
491 1.23 jdolecek static struct intrsource xen_dummy_intrsource;
492 1.23 jdolecek
493 1.23 jdolecek struct intrsource *
494 1.23 jdolecek xen_intr_allocate_io_intrsource(const char *intrid)
495 1.23 jdolecek {
496 1.23 jdolecek /* Nothing to do, required by MSI code */
497 1.23 jdolecek return &xen_dummy_intrsource;
498 1.23 jdolecek }
499 1.23 jdolecek
500 1.23 jdolecek void
501 1.23 jdolecek xen_intr_free_io_intrsource(const char *intrid)
502 1.23 jdolecek {
503 1.23 jdolecek /* Nothing to do, required by MSI code */
504 1.23 jdolecek }
505 1.23 jdolecek
506 1.24 bouyer #if defined(XENPV)
507 1.14 cherry __strong_alias(x86_read_psl, xen_read_psl);
508 1.14 cherry __strong_alias(x86_write_psl, xen_write_psl);
509 1.14 cherry
510 1.14 cherry __strong_alias(intr_string, xintr_string);
511 1.14 cherry __strong_alias(intr_create_intrid, xen_intr_create_intrid);
512 1.14 cherry __strong_alias(intr_establish, xen_intr_establish);
513 1.14 cherry __strong_alias(intr_establish_xname, xen_intr_establish_xname);
514 1.18 thorpej __strong_alias(intr_mask, xen_intr_mask);
515 1.18 thorpej __strong_alias(intr_unmask, xen_intr_unmask);
516 1.14 cherry __strong_alias(intr_disestablish, xen_intr_disestablish);
517 1.14 cherry __strong_alias(cpu_intr_redistribute, xen_cpu_intr_redistribute);
518 1.14 cherry __strong_alias(cpu_intr_count, xen_cpu_intr_count);
519 1.14 cherry __strong_alias(cpu_intr_init, xen_cpu_intr_init);
520 1.23 jdolecek __strong_alias(intr_allocate_io_intrsource, xen_intr_allocate_io_intrsource);
521 1.23 jdolecek __strong_alias(intr_free_io_intrsource, xen_intr_free_io_intrsource);
522 1.24 bouyer #endif /* XENPV */
523