xen_intr.c revision 1.21.2.4 1 /* $NetBSD: xen_intr.c,v 1.21.2.4 2020/04/14 16:52:35 bouyer Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, and by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.21.2.4 2020/04/14 16:52:35 bouyer Exp $");
34
35 #include "opt_multiprocessor.h"
36
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/kmem.h>
40 #include <sys/cpu.h>
41 #include <sys/device.h>
42
43 #include <xen/evtchn.h>
44 #include <xen/xenfunc.h>
45
46 #include <uvm/uvm.h>
47
48 #include <machine/cpu.h>
49 #include <machine/intr.h>
50
51 #include "acpica.h"
52 #include "ioapic.h"
53 #include "lapic.h"
54 #include "pci.h"
55
56 #if NACPICA > 0
57 #include <dev/acpi/acpivar.h>
58 #endif
59
60 #if NIOAPIC > 0 || NACPICA > 0
61 #include <machine/i82093var.h>
62 #endif
63
64 #if NLAPIC > 0
65 #include <machine/i82489var.h>
66 #endif
67
68 #if NPCI > 0
69 #include <dev/pci/ppbreg.h>
70 #endif
71
72 #if defined(MULTIPROCESSOR)
73 static const char *xen_ipi_names[XEN_NIPIS] = XEN_IPI_NAMES;
74 #endif
75
76 #if !defined(XENPVHVM)
77 void
78 x86_disable_intr(void)
79 {
80 curcpu()->ci_vcpu->evtchn_upcall_mask = 1;
81 x86_lfence();
82 }
83
84 void
85 x86_enable_intr(void)
86 {
87 volatile struct vcpu_info *_vci = curcpu()->ci_vcpu;
88 __insn_barrier();
89 _vci->evtchn_upcall_mask = 0;
90 x86_lfence(); /* unmask then check (avoid races) */
91 if (__predict_false(_vci->evtchn_upcall_pending))
92 hypervisor_force_callback();
93 }
94
95 #endif /* !XENPVHVM */
96
97 u_long
98 xen_read_psl(void)
99 {
100
101 return (curcpu()->ci_vcpu->evtchn_upcall_mask);
102 }
103
104 void
105 xen_write_psl(u_long psl)
106 {
107 struct cpu_info *ci = curcpu();
108
109 ci->ci_vcpu->evtchn_upcall_mask = psl;
110 xen_rmb();
111 if (ci->ci_vcpu->evtchn_upcall_pending && psl == 0) {
112 hypervisor_force_callback();
113 }
114 }
115
116 void *
117 xen_intr_establish(int legacy_irq, struct pic *pic, int pin,
118 int type, int level, int (*handler)(void *), void *arg,
119 bool known_mpsafe)
120 {
121
122 return xen_intr_establish_xname(legacy_irq, pic, pin, type, level,
123 handler, arg, known_mpsafe, "XEN");
124 }
125
126 void *
127 xen_intr_establish_xname(int legacy_irq, struct pic *pic, int pin,
128 int type, int level, int (*handler)(void *), void *arg,
129 bool known_mpsafe, const char *xname)
130 {
131 const char *intrstr;
132 char intrstr_buf[INTRIDBUF];
133
134 if (pic->pic_type == PIC_XEN) {
135 struct intrhand *rih;
136
137 intrstr = intr_create_intrid(legacy_irq, pic, pin, intrstr_buf,
138 sizeof(intrstr_buf));
139
140 event_set_handler(pin, handler, arg, level, intrstr, xname,
141 known_mpsafe);
142
143 rih = kmem_zalloc(sizeof(*rih), cold ? KM_NOSLEEP : KM_SLEEP);
144 if (rih == NULL) {
145 printf("%s: can't allocate handler info\n", __func__);
146 return NULL;
147 }
148
149 /*
150 * XXX:
151 * This is just a copy for API conformance.
152 * The real ih is lost in the innards of
153 * event_set_handler(); where the details of
154 * biglock_wrapper etc are taken care of.
155 * All that goes away when we nuke event_set_handler()
156 * et. al. and unify with x86/intr.c
157 */
158 rih->ih_pin = pin; /* port */
159 rih->ih_fun = rih->ih_realfun = handler;
160 rih->ih_arg = rih->ih_realarg = arg;
161 rih->pic_type = pic->pic_type;
162 return rih;
163 } /* Else we assume pintr */
164
165 #if (NPCI > 0 || NISA > 0) && defined(XENPV) /* XXX: support PVHVM pirq */
166 struct pintrhand *pih;
167 int gsi;
168 int vector, evtchn;
169
170 KASSERTMSG(legacy_irq == -1 || (0 <= legacy_irq && legacy_irq < NUM_XEN_IRQS),
171 "bad legacy IRQ value: %d", legacy_irq);
172 KASSERTMSG(!(legacy_irq == -1 && pic == &i8259_pic),
173 "non-legacy IRQon i8259 ");
174
175 gsi = xen_pic_to_gsi(pic, pin);
176
177 intrstr = intr_create_intrid(gsi, pic, pin, intrstr_buf,
178 sizeof(intrstr_buf));
179
180 vector = xen_vec_alloc(gsi);
181
182 if (irq2port[gsi] == 0) {
183 extern struct cpu_info phycpu_info_primary; /* XXX */
184 struct cpu_info *ci = &phycpu_info_primary;
185
186 pic->pic_addroute(pic, ci, pin, vector, type);
187
188 evtchn = bind_pirq_to_evtch(gsi);
189 KASSERT(evtchn > 0);
190 KASSERT(evtchn < NR_EVENT_CHANNELS);
191 irq2port[gsi] = evtchn + 1;
192 xen_atomic_set_bit(&ci->ci_evtmask[0], evtchn);
193 } else {
194 /*
195 * Shared interrupt - we can't rebind.
196 * The port is shared instead.
197 */
198 evtchn = irq2port[gsi] - 1;
199 }
200
201 pih = pirq_establish(gsi, evtchn, handler, arg, level,
202 intrstr, xname, known_mpsafe);
203 pih->pic_type = pic->pic_type;
204 return pih;
205 #endif /* NPCI > 0 || NISA > 0 */
206
207 /* FALLTHROUGH */
208 return NULL;
209 }
210
211 /*
212 * Mask an interrupt source.
213 */
214 void
215 xen_intr_mask(struct intrhand *ih)
216 {
217 /* XXX */
218 panic("xen_intr_mask: not yet implemented.");
219 }
220
221 /*
222 * Unmask an interrupt source.
223 */
224 void
225 xen_intr_unmask(struct intrhand *ih)
226 {
227 /* XXX */
228 panic("xen_intr_unmask: not yet implemented.");
229 }
230
231 /*
232 * Deregister an interrupt handler.
233 */
234 void
235 xen_intr_disestablish(struct intrhand *ih)
236 {
237
238 if (ih->pic_type == PIC_XEN) {
239 event_remove_handler(ih->ih_pin, ih->ih_realfun,
240 ih->ih_realarg);
241 kmem_free(ih, sizeof(*ih));
242 return;
243 }
244 #if defined(DOM0OPS)
245 /*
246 * Cache state, to prevent a use after free situation with
247 * ih.
248 */
249
250 struct pintrhand *pih = (struct pintrhand *)ih;
251
252 int pirq = pih->pirq;
253 int port = pih->evtch;
254 KASSERT(irq2port[pirq] != 0);
255
256 pirq_disestablish(pih);
257
258 if (evtsource[port] == NULL) {
259 /*
260 * Last handler was removed by
261 * event_remove_handler().
262 *
263 * We can safely unbind the pirq now.
264 */
265
266 port = unbind_pirq_from_evtch(pirq);
267 KASSERT(port == pih->evtch);
268 irq2port[pirq] = 0;
269 }
270 #endif
271 return;
272 }
273
274 /* MI interface for kern_cpu.c */
275 void xen_cpu_intr_redistribute(void);
276
277 void
278 xen_cpu_intr_redistribute(void)
279 {
280 KASSERT(mutex_owned(&cpu_lock));
281 KASSERT(mp_online);
282
283 return;
284 }
285
286 /* MD - called by x86/cpu.c */
287 #if defined(INTRSTACKSIZE)
288 static inline bool
289 redzone_const_or_false(bool x)
290 {
291 #ifdef DIAGNOSTIC
292 return x;
293 #else
294 return false;
295 #endif /* !DIAGNOSTIC */
296 }
297
298 static inline int
299 redzone_const_or_zero(int x)
300 {
301 return redzone_const_or_false(true) ? x : 0;
302 }
303 #endif
304
305 void xen_cpu_intr_init(struct cpu_info *);
306 void
307 xen_cpu_intr_init(struct cpu_info *ci)
308 {
309 #if defined(__HAVE_PREEMPTION)
310 x86_init_preempt(ci);
311 #endif
312 x86_intr_calculatemasks(ci);
313
314 #if defined(INTRSTACKSIZE)
315 vaddr_t istack;
316
317 /*
318 * If the red zone is activated, protect both the top and
319 * the bottom of the stack with an unmapped page.
320 */
321 istack = uvm_km_alloc(kernel_map,
322 INTRSTACKSIZE + redzone_const_or_zero(2 * PAGE_SIZE), 0,
323 UVM_KMF_WIRED|UVM_KMF_ZERO);
324 if (redzone_const_or_false(true)) {
325 pmap_kremove(istack, PAGE_SIZE);
326 pmap_kremove(istack + INTRSTACKSIZE + PAGE_SIZE, PAGE_SIZE);
327 pmap_update(pmap_kernel());
328 }
329
330 /*
331 * 33 used to be 1. Arbitrarily reserve 32 more register_t's
332 * of space for ddb(4) to examine some subroutine arguments
333 * and to hunt for the next stack frame.
334 */
335 ci->ci_intrstack = (char *)istack + redzone_const_or_zero(PAGE_SIZE) +
336 INTRSTACKSIZE - 33 * sizeof(register_t);
337 #endif
338
339 #ifdef MULTIPROCESSOR
340 for (int i = 0; i < XEN_NIPIS; i++)
341 evcnt_attach_dynamic(&ci->ci_ipi_events[i], EVCNT_TYPE_MISC,
342 NULL, device_xname(ci->ci_dev), xen_ipi_names[i]);
343 #endif
344
345 ci->ci_idepth = -1;
346 }
347
348 /*
349 * Everything below from here is duplicated from x86/intr.c
350 * When intr.c and xen_intr.c are unified, these will need to be
351 * merged.
352 */
353
354 u_int xen_cpu_intr_count(struct cpu_info *ci);
355
356 u_int
357 xen_cpu_intr_count(struct cpu_info *ci)
358 {
359
360 KASSERT(ci->ci_nintrhand >= 0);
361
362 return ci->ci_nintrhand;
363 }
364
365 static const char *
366 xen_intr_string(int port, char *buf, size_t len, struct pic *pic)
367 {
368 KASSERT(pic->pic_type == PIC_XEN);
369
370 KASSERT(port >= 0);
371 KASSERT(port < NR_EVENT_CHANNELS);
372
373 snprintf(buf, len, "%s channel %d", pic->pic_name, port);
374
375 return buf;
376 }
377
378 static const char *
379 legacy_intr_string(int ih, char *buf, size_t len, struct pic *pic)
380 {
381 int legacy_irq;
382
383 KASSERT(pic->pic_type == PIC_I8259);
384 #if NLAPIC > 0
385 KASSERT(APIC_IRQ_ISLEGACY(ih));
386
387 legacy_irq = APIC_IRQ_LEGACY_IRQ(ih);
388 #else
389 legacy_irq = ih;
390 #endif
391 KASSERT(legacy_irq >= 0 && legacy_irq < 16);
392
393 snprintf(buf, len, "%s pin %d", pic->pic_name, legacy_irq);
394
395 return buf;
396 }
397
398 const char * xintr_string(intr_handle_t ih, char *buf, size_t len);
399
400 const char *
401 xintr_string(intr_handle_t ih, char *buf, size_t len)
402 {
403 #if NIOAPIC > 0
404 struct ioapic_softc *pic;
405 #endif
406
407 if (ih == 0)
408 panic("%s: bogus handle 0x%" PRIx64, __func__, ih);
409
410 #if NIOAPIC > 0
411 if (ih & APIC_INT_VIA_APIC) {
412 pic = ioapic_find(APIC_IRQ_APIC(ih));
413 if (pic != NULL) {
414 snprintf(buf, len, "%s pin %d",
415 device_xname(pic->sc_dev), APIC_IRQ_PIN(ih));
416 } else {
417 snprintf(buf, len,
418 "apic %d int %d (irq %d)",
419 APIC_IRQ_APIC(ih),
420 APIC_IRQ_PIN(ih),
421 APIC_IRQ_LEGACY_IRQ(ih));
422 }
423 } else
424 snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih));
425
426 #elif NLAPIC > 0
427 snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih));
428 #else
429 snprintf(buf, len, "irq %d", (int) ih);
430 #endif
431 return buf;
432
433 }
434
435 /*
436 * Create an interrupt id such as "ioapic0 pin 9". This interrupt id is used
437 * by MI code and intrctl(8).
438 */
439 const char * xen_intr_create_intrid(int legacy_irq, struct pic *pic,
440 int pin, char *buf, size_t len);
441
442 const char *
443 xen_intr_create_intrid(int legacy_irq, struct pic *pic, int pin, char *buf, size_t len)
444 {
445 int ih = 0;
446
447 #if NPCI > 0
448 #if defined(__HAVE_PCI_MSI_MSIX)
449 if ((pic->pic_type == PIC_MSI) || (pic->pic_type == PIC_MSIX)) {
450 uint64_t pih;
451 int dev, vec;
452
453 dev = msipic_get_devid(pic);
454 vec = pin;
455 pih = __SHIFTIN((uint64_t)dev, MSI_INT_DEV_MASK)
456 | __SHIFTIN((uint64_t)vec, MSI_INT_VEC_MASK)
457 | APIC_INT_VIA_MSI;
458 if (pic->pic_type == PIC_MSI)
459 MSI_INT_MAKE_MSI(pih);
460 else if (pic->pic_type == PIC_MSIX)
461 MSI_INT_MAKE_MSIX(pih);
462
463 return x86_pci_msi_string(NULL, pih, buf, len);
464 }
465 #endif /* __HAVE_PCI_MSI_MSIX */
466 #endif
467
468 if (pic->pic_type == PIC_XEN) {
469 ih = pin; /* Port == pin */
470 return xen_intr_string(pin, buf, len, pic);
471 }
472
473 /*
474 * If the device is pci, "legacy_irq" is alway -1. Least 8 bit of "ih"
475 * is only used in intr_string() to show the irq number.
476 * If the device is "legacy"(such as floppy), it should not use
477 * intr_string().
478 */
479 if (pic->pic_type == PIC_I8259) {
480 ih = legacy_irq;
481 return legacy_intr_string(ih, buf, len, pic);
482 }
483
484 #if NIOAPIC > 0 || NACPICA > 0
485 ih = ((pic->pic_apicid << APIC_INT_APIC_SHIFT) & APIC_INT_APIC_MASK)
486 | ((pin << APIC_INT_PIN_SHIFT) & APIC_INT_PIN_MASK);
487 if (pic->pic_type == PIC_IOAPIC) {
488 ih |= APIC_INT_VIA_APIC;
489 }
490 ih |= pin;
491 return intr_string(ih, buf, len);
492 #endif
493
494 return NULL; /* No pic found! */
495 }
496
497 #if !defined(XENPVHVM)
498 __strong_alias(x86_read_psl, xen_read_psl);
499 __strong_alias(x86_write_psl, xen_write_psl);
500
501 __strong_alias(intr_string, xintr_string);
502 __strong_alias(intr_create_intrid, xen_intr_create_intrid);
503 __strong_alias(intr_establish, xen_intr_establish);
504 __strong_alias(intr_establish_xname, xen_intr_establish_xname);
505 __strong_alias(intr_mask, xen_intr_mask);
506 __strong_alias(intr_unmask, xen_intr_unmask);
507 __strong_alias(intr_disestablish, xen_intr_disestablish);
508 __strong_alias(cpu_intr_redistribute, xen_cpu_intr_redistribute);
509 __strong_alias(cpu_intr_count, xen_cpu_intr_count);
510 __strong_alias(cpu_intr_init, xen_cpu_intr_init);
511 #endif /* !XENPVHVM */
512