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xen_intr.c revision 1.21.2.8 
      1 /*	$NetBSD: xen_intr.c,v 1.21.2.8 2020/04/20 11:29:01 bouyer Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Charles M. Hannum, and by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.21.2.8 2020/04/20 11:29:01 bouyer Exp $");
     34 
     35 #include "opt_multiprocessor.h"
     36 
     37 #include <sys/param.h>
     38 #include <sys/kernel.h>
     39 #include <sys/kmem.h>
     40 #include <sys/cpu.h>
     41 #include <sys/device.h>
     42 
     43 #include <xen/intr.h>
     44 #include <xen/evtchn.h>
     45 #include <xen/xenfunc.h>
     46 
     47 #include <uvm/uvm.h>
     48 
     49 #include <machine/cpu.h>
     50 #include <machine/intr.h>
     51 
     52 #include "acpica.h"
     53 #include "ioapic.h"
     54 #include "lapic.h"
     55 #include "pci.h"
     56 
     57 #if NACPICA > 0
     58 #include <dev/acpi/acpivar.h>
     59 #endif
     60 
     61 #if NIOAPIC > 0 || NACPICA > 0
     62 #include <machine/i82093var.h>
     63 #endif
     64 
     65 #if NLAPIC > 0
     66 #include <machine/i82489var.h>
     67 #endif
     68 
     69 #if NPCI > 0
     70 #include <dev/pci/ppbreg.h>
     71 #endif
     72 
     73 #if defined(MULTIPROCESSOR)
     74 static const char *xen_ipi_names[XEN_NIPIS] = XEN_IPI_NAMES;
     75 #endif
     76 
     77 #if !defined(XENPVHVM)
     78 void
     79 x86_disable_intr(void)
     80 {
     81 	curcpu()->ci_vcpu->evtchn_upcall_mask = 1;
     82 	x86_lfence();
     83 }
     84 
     85 void
     86 x86_enable_intr(void)
     87 {
     88 	volatile struct vcpu_info *_vci = curcpu()->ci_vcpu;
     89 	__insn_barrier();
     90 	_vci->evtchn_upcall_mask = 0;
     91 	x86_lfence(); /* unmask then check (avoid races) */
     92 	if (__predict_false(_vci->evtchn_upcall_pending))
     93 		hypervisor_force_callback();
     94 }
     95 
     96 #endif /* !XENPVHVM */
     97 
     98 u_long
     99 xen_read_psl(void)
    100 {
    101 
    102 	return (curcpu()->ci_vcpu->evtchn_upcall_mask);
    103 }
    104 
    105 void
    106 xen_write_psl(u_long psl)
    107 {
    108 	struct cpu_info *ci = curcpu();
    109 
    110 	ci->ci_vcpu->evtchn_upcall_mask = psl;
    111 	xen_rmb();
    112 	if (ci->ci_vcpu->evtchn_upcall_pending && psl == 0) {
    113 	    	hypervisor_force_callback();
    114 	}
    115 }
    116 
    117 void *
    118 xen_intr_establish(int legacy_irq, struct pic *pic, int pin,
    119     int type, int level, int (*handler)(void *), void *arg,
    120     bool known_mpsafe)
    121 {
    122 
    123 	return xen_intr_establish_xname(legacy_irq, pic, pin, type, level,
    124 	    handler, arg, known_mpsafe, "XEN");
    125 }
    126 
    127 void *
    128 xen_intr_establish_xname(int legacy_irq, struct pic *pic, int pin,
    129     int type, int level, int (*handler)(void *), void *arg,
    130     bool known_mpsafe, const char *xname)
    131 {
    132 	const char *intrstr;
    133 	char intrstr_buf[INTRIDBUF];
    134 
    135 	if (pic->pic_type == PIC_XEN) {
    136 		struct intrhand *rih;
    137 
    138 		intrstr = intr_create_intrid(legacy_irq, pic, pin, intrstr_buf,
    139 		    sizeof(intrstr_buf));
    140 
    141 		rih = event_set_handler(pin, handler, arg, level,
    142 		    intrstr, xname, known_mpsafe, true);
    143 
    144 		if (rih == NULL) {
    145 			printf("%s: can't establish interrupt\n", __func__);
    146 			return NULL;
    147 		}
    148 
    149 		return rih;
    150 	} 	/* Else we assume pintr */
    151 
    152 #if (NPCI > 0 || NISA > 0) && defined(XENPV) /* XXX: support PVHVM pirq */
    153 	struct pintrhand *pih;
    154 	int gsi;
    155 	int vector, evtchn;
    156 
    157 	KASSERTMSG(legacy_irq == -1 || (0 <= legacy_irq && legacy_irq < NUM_XEN_IRQS),
    158 	    "bad legacy IRQ value: %d", legacy_irq);
    159 	KASSERTMSG(!(legacy_irq == -1 && pic == &i8259_pic),
    160 	    "non-legacy IRQon i8259 ");
    161 
    162 	gsi = xen_pic_to_gsi(pic, pin);
    163 
    164 	intrstr = intr_create_intrid(gsi, pic, pin, intrstr_buf,
    165 	    sizeof(intrstr_buf));
    166 
    167 	vector = xen_vec_alloc(gsi);
    168 
    169 	if (irq2port[gsi] == 0) {
    170 		extern struct cpu_info phycpu_info_primary; /* XXX */
    171 		struct cpu_info *ci = &phycpu_info_primary;
    172 
    173 		pic->pic_addroute(pic, ci, pin, vector, type);
    174 
    175 		evtchn = bind_pirq_to_evtch(gsi);
    176 		KASSERT(evtchn > 0);
    177 		KASSERT(evtchn < NR_EVENT_CHANNELS);
    178 		irq2port[gsi] = evtchn + 1;
    179 		xen_atomic_set_bit(&ci->ci_evtmask[0], evtchn);
    180 	} else {
    181 		/*
    182 		 * Shared interrupt - we can't rebind.
    183 		 * The port is shared instead.
    184 		 */
    185 		evtchn = irq2port[gsi] - 1;
    186 	}
    187 
    188 	pih = pirq_establish(gsi, evtchn, handler, arg, level,
    189 			     intrstr, xname, known_mpsafe);
    190 	pih->pic = pic;
    191 	return pih;
    192 #endif /* NPCI > 0 || NISA > 0 */
    193 
    194 	/* FALLTHROUGH */
    195 	return NULL;
    196 }
    197 
    198 /*
    199  * Mask an interrupt source.
    200  */
    201 void
    202 xen_intr_mask(struct intrhand *ih)
    203 {
    204 	/* XXX */
    205 	panic("xen_intr_mask: not yet implemented.");
    206 }
    207 
    208 /*
    209  * Unmask an interrupt source.
    210  */
    211 void
    212 xen_intr_unmask(struct intrhand *ih)
    213 {
    214 	/* XXX */
    215 	panic("xen_intr_unmask: not yet implemented.");
    216 }
    217 
    218 /*
    219  * Deregister an interrupt handler.
    220  */
    221 void
    222 xen_intr_disestablish(struct intrhand *ih)
    223 {
    224 
    225 	if (ih->ih_pic->pic_type == PIC_XEN) {
    226 		event_remove_handler(ih->ih_pin, ih->ih_realfun,
    227 		    ih->ih_realarg);
    228 		/* event_remove_handler frees ih */
    229 		return;
    230 	}
    231 #if defined(DOM0OPS)
    232 	/*
    233 	 * Cache state, to prevent a use after free situation with
    234 	 * ih.
    235 	 */
    236 
    237 	struct pintrhand *pih = (struct pintrhand *)ih;
    238 
    239 	int pirq = pih->pirq;
    240 	int port = pih->evtch;
    241 	KASSERT(irq2port[pirq] != 0);
    242 
    243 	pirq_disestablish(pih);
    244 
    245 	if (evtsource[port] == NULL) {
    246 			/*
    247 			 * Last handler was removed by
    248 			 * event_remove_handler().
    249 			 *
    250 			 * We can safely unbind the pirq now.
    251 			 */
    252 
    253 			port = unbind_pirq_from_evtch(pirq);
    254 			KASSERT(port == pih->evtch);
    255 			irq2port[pirq] = 0;
    256 	}
    257 #endif
    258 	return;
    259 }
    260 
    261 /* MI interface for kern_cpu.c */
    262 void xen_cpu_intr_redistribute(void);
    263 
    264 void
    265 xen_cpu_intr_redistribute(void)
    266 {
    267 	KASSERT(mutex_owned(&cpu_lock));
    268 	KASSERT(mp_online);
    269 
    270 	return;
    271 }
    272 
    273 /* MD - called by x86/cpu.c */
    274 #if defined(INTRSTACKSIZE)
    275 static inline bool
    276 redzone_const_or_false(bool x)
    277 {
    278 #ifdef DIAGNOSTIC
    279 	return x;
    280 #else
    281 	return false;
    282 #endif /* !DIAGNOSTIC */
    283 }
    284 
    285 static inline int
    286 redzone_const_or_zero(int x)
    287 {
    288 	return redzone_const_or_false(true) ? x : 0;
    289 }
    290 #endif
    291 
    292 void xen_cpu_intr_init(struct cpu_info *);
    293 void
    294 xen_cpu_intr_init(struct cpu_info *ci)
    295 {
    296 #if defined(__HAVE_PREEMPTION)
    297 	x86_init_preempt(ci);
    298 #endif
    299 	x86_intr_calculatemasks(ci);
    300 
    301 #if defined(INTRSTACKSIZE)
    302 	vaddr_t istack;
    303 
    304 	/*
    305 	 * If the red zone is activated, protect both the top and
    306 	 * the bottom of the stack with an unmapped page.
    307 	 */
    308 	istack = uvm_km_alloc(kernel_map,
    309 	    INTRSTACKSIZE + redzone_const_or_zero(2 * PAGE_SIZE), 0,
    310 	    UVM_KMF_WIRED|UVM_KMF_ZERO);
    311 	if (redzone_const_or_false(true)) {
    312 		pmap_kremove(istack, PAGE_SIZE);
    313 		pmap_kremove(istack + INTRSTACKSIZE + PAGE_SIZE, PAGE_SIZE);
    314 		pmap_update(pmap_kernel());
    315 	}
    316 
    317 	/*
    318 	 * 33 used to be 1.  Arbitrarily reserve 32 more register_t's
    319 	 * of space for ddb(4) to examine some subroutine arguments
    320 	 * and to hunt for the next stack frame.
    321 	 */
    322 	ci->ci_intrstack = (char *)istack + redzone_const_or_zero(PAGE_SIZE) +
    323 	    INTRSTACKSIZE - 33 * sizeof(register_t);
    324 #endif
    325 
    326 #ifdef MULTIPROCESSOR
    327 	for (int i = 0; i < XEN_NIPIS; i++)
    328 		evcnt_attach_dynamic(&ci->ci_ipi_events[i], EVCNT_TYPE_MISC,
    329 		    NULL, device_xname(ci->ci_dev), xen_ipi_names[i]);
    330 #endif
    331 
    332 	ci->ci_idepth = -1;
    333 }
    334 
    335 /*
    336  * Everything below from here is duplicated from x86/intr.c
    337  * When intr.c and xen_intr.c are unified, these will need to be
    338  * merged.
    339  */
    340 
    341 u_int xen_cpu_intr_count(struct cpu_info *ci);
    342 
    343 u_int
    344 xen_cpu_intr_count(struct cpu_info *ci)
    345 {
    346 
    347 	KASSERT(ci->ci_nintrhand >= 0);
    348 
    349 	return ci->ci_nintrhand;
    350 }
    351 
    352 static const char *
    353 xen_intr_string(int port, char *buf, size_t len, struct pic *pic)
    354 {
    355 	KASSERT(pic->pic_type == PIC_XEN);
    356 
    357 	KASSERT(port >= 0);
    358 	KASSERT(port < NR_EVENT_CHANNELS);
    359 
    360 	snprintf(buf, len, "%s channel %d", pic->pic_name, port);
    361 
    362 	return buf;
    363 }
    364 
    365 static const char *
    366 legacy_intr_string(int ih, char *buf, size_t len, struct pic *pic)
    367 {
    368 	int legacy_irq;
    369 
    370 	KASSERT(pic->pic_type == PIC_I8259);
    371 #if NLAPIC > 0
    372 	KASSERT(APIC_IRQ_ISLEGACY(ih));
    373 
    374 	legacy_irq = APIC_IRQ_LEGACY_IRQ(ih);
    375 #else
    376 	legacy_irq = ih;
    377 #endif
    378 	KASSERT(legacy_irq >= 0 && legacy_irq < 16);
    379 
    380 	snprintf(buf, len, "%s pin %d", pic->pic_name, legacy_irq);
    381 
    382 	return buf;
    383 }
    384 
    385 const char * xintr_string(intr_handle_t ih, char *buf, size_t len);
    386 
    387 const char *
    388 xintr_string(intr_handle_t ih, char *buf, size_t len)
    389 {
    390 #if NIOAPIC > 0
    391 	struct ioapic_softc *pic;
    392 #endif
    393 
    394 	if (ih == 0)
    395 		panic("%s: bogus handle 0x%" PRIx64, __func__, ih);
    396 
    397 #if NIOAPIC > 0
    398 	if (ih & APIC_INT_VIA_APIC) {
    399 		pic = ioapic_find(APIC_IRQ_APIC(ih));
    400 		if (pic != NULL) {
    401 			snprintf(buf, len, "%s pin %d",
    402 			    device_xname(pic->sc_dev), APIC_IRQ_PIN(ih));
    403 		} else {
    404 			snprintf(buf, len,
    405 			    "apic %d int %d (irq %d)",
    406 			    APIC_IRQ_APIC(ih),
    407 			    APIC_IRQ_PIN(ih),
    408 			    APIC_IRQ_LEGACY_IRQ(ih));
    409 		}
    410 	} else
    411 		snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih));
    412 
    413 #elif NLAPIC > 0
    414 	snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih));
    415 #else
    416 	snprintf(buf, len, "irq %d", (int) ih);
    417 #endif
    418 	return buf;
    419 
    420 }
    421 
    422 /*
    423  * Create an interrupt id such as "ioapic0 pin 9". This interrupt id is used
    424  * by MI code and intrctl(8).
    425  */
    426 const char * xen_intr_create_intrid(int legacy_irq, struct pic *pic,
    427     int pin, char *buf, size_t len);
    428 
    429 const char *
    430 xen_intr_create_intrid(int legacy_irq, struct pic *pic, int pin, char *buf, size_t len)
    431 {
    432 	int ih = 0;
    433 
    434 #if NPCI > 0 && defined(XENPV)
    435 #if defined(__HAVE_PCI_MSI_MSIX)
    436 	if ((pic->pic_type == PIC_MSI) || (pic->pic_type == PIC_MSIX)) {
    437 		uint64_t pih;
    438 		int dev, vec;
    439 
    440 		dev = msipic_get_devid(pic);
    441 		vec = pin;
    442 		pih = __SHIFTIN((uint64_t)dev, MSI_INT_DEV_MASK)
    443 			| __SHIFTIN((uint64_t)vec, MSI_INT_VEC_MASK)
    444 			| APIC_INT_VIA_MSI;
    445 		if (pic->pic_type == PIC_MSI)
    446 			MSI_INT_MAKE_MSI(pih);
    447 		else if (pic->pic_type == PIC_MSIX)
    448 			MSI_INT_MAKE_MSIX(pih);
    449 
    450 		return x86_pci_msi_string(NULL, pih, buf, len);
    451 	}
    452 #endif /* __HAVE_PCI_MSI_MSIX */
    453 #endif
    454 
    455 	if (pic->pic_type == PIC_XEN) {
    456 		ih = pin;	/* Port == pin */
    457 		return xen_intr_string(pin, buf, len, pic);
    458 	}
    459 
    460 	/*
    461 	 * If the device is pci, "legacy_irq" is alway -1. Least 8 bit of "ih"
    462 	 * is only used in intr_string() to show the irq number.
    463 	 * If the device is "legacy"(such as floppy), it should not use
    464 	 * intr_string().
    465 	 */
    466 	if (pic->pic_type == PIC_I8259) {
    467 		ih = legacy_irq;
    468 		return legacy_intr_string(ih, buf, len, pic);
    469 	}
    470 
    471 #if NIOAPIC > 0 || NACPICA > 0
    472 	ih = ((pic->pic_apicid << APIC_INT_APIC_SHIFT) & APIC_INT_APIC_MASK)
    473 	    | ((pin << APIC_INT_PIN_SHIFT) & APIC_INT_PIN_MASK);
    474 	if (pic->pic_type == PIC_IOAPIC) {
    475 		ih |= APIC_INT_VIA_APIC;
    476 	}
    477 	ih |= pin;
    478 	return intr_string(ih, buf, len);
    479 #endif
    480 
    481 	return NULL; /* No pic found! */
    482 }
    483 
    484 #if defined(XENPV)
    485 __strong_alias(x86_read_psl, xen_read_psl);
    486 __strong_alias(x86_write_psl, xen_write_psl);
    487 
    488 __strong_alias(intr_string, xintr_string);
    489 __strong_alias(intr_create_intrid, xen_intr_create_intrid);
    490 __strong_alias(intr_establish, xen_intr_establish);
    491 __strong_alias(intr_establish_xname, xen_intr_establish_xname);
    492 __strong_alias(intr_mask, xen_intr_mask);
    493 __strong_alias(intr_unmask, xen_intr_unmask);
    494 __strong_alias(intr_disestablish, xen_intr_disestablish);
    495 __strong_alias(cpu_intr_redistribute, xen_cpu_intr_redistribute);
    496 __strong_alias(cpu_intr_count, xen_cpu_intr_count);
    497 __strong_alias(cpu_intr_init, xen_cpu_intr_init);
    498 #endif /* XENPV */
    499