zssp.c revision 1.1
1 /* $OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Uwe Stuehler <uwe (at) bsdx.de> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.1 2006/12/16 05:23:49 ober Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/device.h> 25 26 #include <machine/bus.h> 27 28 #include <arm/xscale/pxa2x0reg.h> 29 #include <arm/xscale/pxa2x0var.h> 30 #include <arm/xscale/pxa2x0_gpio.h> 31 32 #include <zaurus/dev/zsspvar.h> 33 #include <zaurus/zaurus/zaurus_var.h> 34 35 #include "ioconf.h" 36 37 #define GPIO_ADS7846_CS_C3000 14 /* SSP SFRM */ 38 #define GPIO_MAX1111_CS_C3000 20 39 #define GPIO_TG_CS_C3000 53 40 41 #define SSCR0_ADS7846_C3000 0x06ab 42 #define SSCR0_LZ9JG18 0x01ab 43 #define SSCR0_MAX1111 0x0387 44 45 struct zssp_softc { 46 struct device sc_dev; 47 bus_space_tag_t sc_iot; 48 bus_space_handle_t sc_ioh; 49 }; 50 51 static int zssp_match(struct device *, struct cfdata *, void *); 52 static void zssp_attach(struct device *, struct device *, void *); 53 static void zssp_init(void); 54 static void zssp_powerhook(int, void *); 55 56 CFATTACH_DECL(zssp, sizeof(struct zssp_softc), 57 zssp_match, zssp_attach, NULL, NULL); 58 59 static int 60 zssp_match(struct device *parent, struct cfdata *cf, void *aux) 61 { 62 63 return 1; 64 } 65 66 static void 67 zssp_attach(struct device *parent, struct device *self, void *aux) 68 { 69 struct zssp_softc *sc = (struct zssp_softc *)self; 70 71 sc->sc_iot = &pxa2x0_bs_tag; 72 if (bus_space_map(sc->sc_iot, PXA2X0_SSP1_BASE, PXA2X0_SSP_SIZE, 73 0, &sc->sc_ioh)) { 74 printf(": can't map bus space\n"); 75 return; 76 } 77 78 printf("\n"); 79 80 if (powerhook_establish(sc->sc_dev.dv_xname, zssp_powerhook, sc) 81 == NULL) { 82 printf("%s: can't establish power hook\n", 83 sc->sc_dev.dv_xname); 84 } 85 86 zssp_init(); 87 } 88 89 /* 90 * Initialize the dedicated SSP unit and disable all chip selects. 91 * This function is called with interrupts disabled. 92 */ 93 static void 94 zssp_init(void) 95 { 96 struct zssp_softc *sc; 97 98 KASSERT(zssp_cd.cd_ndevs > 0 && zssp_cd.cd_devs[0] != NULL); 99 sc = (struct zssp_softc *)zssp_cd.cd_devs[0]; 100 101 pxa2x0_clkman_config(CKEN_SSP, 1); 102 103 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_LZ9JG18); 104 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0); 105 106 pxa2x0_gpio_set_function(GPIO_ADS7846_CS_C3000, GPIO_OUT|GPIO_SET); 107 pxa2x0_gpio_set_function(GPIO_MAX1111_CS_C3000, GPIO_OUT|GPIO_SET); 108 pxa2x0_gpio_set_function(GPIO_TG_CS_C3000, GPIO_OUT|GPIO_SET); 109 } 110 111 static void 112 zssp_powerhook(int why, void *arg) 113 { 114 int s; 115 116 if (why == PWR_RESUME) { 117 s = splhigh(); 118 zssp_init(); 119 splx(s); 120 } 121 } 122 123 /* 124 * Transmit a single data word to one of the ICs, keep the chip selected 125 * afterwards, and don't wait for data to be returned in SSDR. Interrupts 126 * must be held off until zssp_ic_stop() gets called. 127 */ 128 void 129 zssp_ic_start(int ic, uint32_t data) 130 { 131 struct zssp_softc *sc; 132 133 KASSERT(zssp_cd.cd_ndevs > 0 && zssp_cd.cd_devs[0] != NULL); 134 sc = (struct zssp_softc *)zssp_cd.cd_devs[0]; 135 136 /* disable other ICs */ 137 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 138 if (ic != ZSSP_IC_ADS7846) 139 pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000); 140 if (ic != ZSSP_IC_LZ9JG18) 141 pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000); 142 if (ic != ZSSP_IC_MAX1111) 143 pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000); 144 145 /* activate the chosen one */ 146 switch (ic) { 147 case ZSSP_IC_ADS7846: 148 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 149 SSCR0_ADS7846_C3000); 150 pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000); 151 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data); 152 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 153 & SSSR_TNF) != SSSR_TNF) 154 continue; /* poll */ 155 break; 156 case ZSSP_IC_LZ9JG18: 157 pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000); 158 break; 159 case ZSSP_IC_MAX1111: 160 pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000); 161 break; 162 } 163 } 164 165 /* 166 * Read the last value from SSDR and deactivate all chip-selects. 167 */ 168 uint32_t 169 zssp_ic_stop(int ic) 170 { 171 struct zssp_softc *sc; 172 uint32_t rv; 173 174 KASSERT(zssp_cd.cd_ndevs > 0 && zssp_cd.cd_devs[0] != NULL); 175 sc = (struct zssp_softc *)zssp_cd.cd_devs[0]; 176 177 switch (ic) { 178 case ZSSP_IC_ADS7846: 179 /* read result of last command */ 180 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 181 & SSSR_RNE) != SSSR_RNE) 182 continue; /* poll */ 183 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 184 break; 185 case ZSSP_IC_LZ9JG18: 186 case ZSSP_IC_MAX1111: 187 /* last value received is irrelevant or undefined */ 188 default: 189 rv = 0; 190 break; 191 } 192 193 pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000); 194 pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000); 195 pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000); 196 197 return rv; 198 } 199 200 /* 201 * Activate one of the chip-select lines, transmit one word value in 202 * each direction, and deactivate the chip-select again. 203 */ 204 uint32_t 205 zssp_ic_send(int ic, uint32_t data) 206 { 207 208 switch (ic) { 209 case ZSSP_IC_MAX1111: 210 return (zssp_read_max1111(data)); 211 case ZSSP_IC_ADS7846: 212 return (zssp_read_ads7846(data)); 213 case ZSSP_IC_LZ9JG18: 214 zssp_write_lz9jg18(data); 215 return 0; 216 default: 217 printf("zssp_ic_send: invalid IC %d\n", ic); 218 return 0; 219 } 220 } 221 222 int 223 zssp_read_max1111(uint32_t cmd) 224 { 225 struct zssp_softc *sc; 226 int voltage[2]; 227 int i; 228 int s; 229 230 KASSERT(zssp_cd.cd_ndevs > 0 && zssp_cd.cd_devs[0] != NULL); 231 sc = (struct zssp_softc *)zssp_cd.cd_devs[0]; 232 233 s = splhigh(); 234 235 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 236 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_MAX1111); 237 238 pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000); 239 pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000); 240 pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000); 241 242 delay(1); 243 244 /* Send the command word and read a dummy word back. */ 245 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 246 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 247 & SSSR_TNF) != SSSR_TNF) 248 continue; /* poll */ 249 /* XXX is this delay necessary? */ 250 delay(1); 251 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 252 & SSSR_RNE) != SSSR_RNE) 253 continue; /* poll */ 254 (void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 255 256 for (i = 0; i < 2; i++) { 257 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, 0); 258 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 259 & SSSR_TNF) != SSSR_TNF) 260 continue; /* poll */ 261 /* XXX again, is this delay necessary? */ 262 delay(1); 263 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 264 & SSSR_RNE) != SSSR_RNE) 265 continue; /* poll */ 266 voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 267 SSP_SSDR); 268 } 269 270 pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000); 271 pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000); 272 pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000); 273 274 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 275 276 splx(s); 277 278 /* XXX no idea what this means, but it's what Linux would do. */ 279 if ((voltage[0] & 0xc0) != 0 || (voltage[1] & 0x3f) != 0) { 280 voltage[0] = -1; 281 } else { 282 voltage[0] = ((voltage[0] << 2) & 0xfc) | 283 ((voltage[1] >> 6) & 0x03); 284 } 285 286 return voltage[0]; 287 } 288 289 /* XXX - only does CS_ADS7846 */ 290 uint32_t 291 zssp_read_ads7846(uint32_t cmd) 292 { 293 struct zssp_softc *sc; 294 295 sc = (struct zssp_softc *)zssp_cd.cd_devs[0]; 296 unsigned int cr0; 297 int s; 298 uint32_t val; 299 300 if (zssp_cd.cd_ndevs < 1 || zssp_cd.cd_devs[0] == NULL) { 301 printf("zssp_read_ads7846: not configured\n"); 302 return 0; 303 } 304 305 sc = (struct zssp_softc *)zssp_cd.cd_devs[0]; 306 307 s = splhigh(); 308 if (1) { 309 cr0 = SSCR0_ADS7846_C3000; 310 } else { 311 cr0 = 0x00ab; 312 } 313 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 314 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, cr0); 315 316 pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000); 317 pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000); 318 pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000); 319 320 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 321 322 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 323 & SSSR_TNF) != SSSR_TNF) 324 continue; /* poll */ 325 326 delay(1); 327 328 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 329 & SSSR_RNE) != SSSR_RNE) 330 continue; /* poll */ 331 332 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 333 334 pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000); /* deselect */ 335 336 splx(s); 337 338 return val; 339 } 340 341 void 342 zssp_write_lz9jg18(uint32_t data) 343 { 344 int s; 345 int sclk_pin, sclk_fn; 346 int sfrm_pin, sfrm_fn; 347 int txd_pin, txd_fn; 348 int rxd_pin, rxd_fn; 349 int i; 350 351 /* XXX this creates a DAC command from a backlight duty value. */ 352 data = 0x40 | (data & 0x1f); 353 354 if (ZAURUS_ISC3000) { 355 /* C3000 */ 356 sclk_pin = 19; 357 sfrm_pin = 14; 358 txd_pin = 87; 359 rxd_pin = 86; 360 } else { 361 sclk_pin = 23; 362 sfrm_pin = 24; 363 txd_pin = 25; 364 rxd_pin = 26; 365 } 366 367 s = splhigh(); 368 369 sclk_fn = pxa2x0_gpio_get_function(sclk_pin); 370 sfrm_fn = pxa2x0_gpio_get_function(sfrm_pin); 371 txd_fn = pxa2x0_gpio_get_function(txd_pin); 372 rxd_fn = pxa2x0_gpio_get_function(rxd_pin); 373 374 pxa2x0_gpio_set_function(sfrm_pin, GPIO_OUT | GPIO_SET); 375 pxa2x0_gpio_set_function(sclk_pin, GPIO_OUT | GPIO_CLR); 376 pxa2x0_gpio_set_function(txd_pin, GPIO_OUT | GPIO_CLR); 377 pxa2x0_gpio_set_function(rxd_pin, GPIO_IN); 378 379 pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000); 380 pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000); 381 pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000); 382 383 delay(10); 384 385 for (i = 0; i < 8; i++) { 386 if (data & 0x80) 387 pxa2x0_gpio_set_bit(txd_pin); 388 else 389 pxa2x0_gpio_clear_bit(txd_pin); 390 delay(10); 391 pxa2x0_gpio_set_bit(sclk_pin); 392 delay(10); 393 pxa2x0_gpio_clear_bit(sclk_pin); 394 delay(10); 395 data <<= 1; 396 } 397 398 pxa2x0_gpio_clear_bit(txd_pin); 399 pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000); 400 401 pxa2x0_gpio_set_function(sclk_pin, sclk_fn); 402 pxa2x0_gpio_set_function(sfrm_pin, sfrm_fn); 403 pxa2x0_gpio_set_function(txd_pin, txd_fn); 404 pxa2x0_gpio_set_function(rxd_pin, rxd_fn); 405 406 splx(s); 407 } 408
Indexes created Tue Sep 23 14:10:03 GMT 2025