zssp.c revision 1.13.62.1 1 /* $NetBSD: zssp.c,v 1.13.62.1 2021/03/20 19:33:39 thorpej Exp $ */
2 /* $OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $ */
3
4 /*
5 * Copyright (c) 2005 Uwe Stuehler <uwe (at) bsdx.de>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.13.62.1 2021/03/20 19:33:39 thorpej Exp $");
22
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/bus.h>
27
28 #include <arm/xscale/pxa2x0reg.h>
29 #include <arm/xscale/pxa2x0var.h>
30 #include <arm/xscale/pxa2x0_gpio.h>
31
32 #include <zaurus/dev/zsspvar.h>
33 #include <zaurus/zaurus/zaurus_var.h>
34
35 #define GPIO_ADS7846_CS_C3000 14 /* SSP SFRM */
36 #define GPIO_MAX1111_CS_C3000 20
37 #define GPIO_TG_CS_C3000 53
38 #define GPIO_ADS7846_CS_C860 24 /* SSP SFRM */
39 #define GPIO_MAX1111_CS_C860 20
40 #define GPIO_TG_CS_C860 19
41
42 #define SSCR0_ADS7846_C3000 0x06ab /* 12bit/Microwire/div by 7 */
43 #define SSCR0_MAX1111 0x0387
44 #define SSCR0_LZ9JG18 0x01ab
45 #define SSCR0_ADS7846_C860 0x00ab /* 12bit/Microwire/div by 7 */
46
47 struct zssp_ads7846 {
48 u_int gpio;
49 uint32_t sscr0;
50 };
51 struct zssp_max1111 {
52 u_int gpio;
53 uint32_t sscr0;
54 };
55 struct zssp_lz9jg18 {
56 u_int gpio;
57 uint32_t sscr0;
58 int sclk_pin;
59 int sfrm_pin;
60 int txd_pin;
61 int rxd_pin;
62 };
63
64 struct zssp_softc {
65 device_t sc_dev;
66 bus_space_tag_t sc_iot;
67 bus_space_handle_t sc_ioh;
68 bus_addr_t sc_ssp;
69 struct zssp_ads7846 ads7846;
70 struct zssp_max1111 max1111;
71 struct zssp_lz9jg18 lz9jg18;
72 };
73
74 static int zssp_match(device_t, cfdata_t, void *);
75 static void zssp_attach(device_t, device_t, void *);
76 static int zssp_search(device_t, cfdata_t, const int *, void *);
77 static int zssp_print(void *, const char *);
78
79 CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
80 zssp_match, zssp_attach, NULL, NULL);
81
82 static void zssp_init(void);
83 static bool zssp_resume(device_t dv, const pmf_qual_t *);
84
85 static struct zssp_softc *zssp_sc;
86
87 static int
88 zssp_match(device_t parent, cfdata_t cf, void *aux)
89 {
90
91 if (zssp_sc != NULL)
92 return 0;
93 return 1;
94 }
95
96 static void
97 zssp_attach(device_t parent, device_t self, void *aux)
98 {
99 struct zssp_softc *sc = device_private(self);
100
101 sc->sc_dev = self;
102 zssp_sc = sc;
103
104 aprint_normal("\n");
105 aprint_naive("\n");
106
107 sc->sc_iot = &pxa2x0_bs_tag;
108 if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
109 sc->sc_ssp = PXA2X0_SSP1_BASE;
110 sc->ads7846.gpio = GPIO_ADS7846_CS_C3000;
111 sc->ads7846.sscr0 = SSCR0_ADS7846_C3000;
112 sc->max1111.gpio = GPIO_MAX1111_CS_C3000;
113 sc->max1111.sscr0 = SSCR0_MAX1111;
114 sc->lz9jg18.gpio = GPIO_TG_CS_C3000;
115 sc->lz9jg18.sscr0 = SSCR0_LZ9JG18;
116 sc->lz9jg18.sclk_pin = 19;
117 sc->lz9jg18.sfrm_pin = 14;
118 sc->lz9jg18.txd_pin = 87;
119 sc->lz9jg18.rxd_pin = 86;
120 } else {
121 sc->sc_ssp = PXA2X0_SSP_BASE;
122 sc->ads7846.gpio = GPIO_ADS7846_CS_C860;
123 sc->ads7846.sscr0 = SSCR0_ADS7846_C860;
124 sc->max1111.gpio = GPIO_MAX1111_CS_C860;
125 sc->max1111.sscr0 = SSCR0_MAX1111;
126 sc->lz9jg18.gpio = GPIO_TG_CS_C860;
127 sc->lz9jg18.sscr0 = SSCR0_LZ9JG18;
128 sc->lz9jg18.sclk_pin = 23;
129 sc->lz9jg18.sfrm_pin = 24;
130 sc->lz9jg18.txd_pin = 25;
131 sc->lz9jg18.rxd_pin = 26;
132 }
133
134 if (bus_space_map(sc->sc_iot, sc->sc_ssp, PXA2X0_SSP_SIZE,
135 0, &sc->sc_ioh)) {
136 aprint_error_dev(sc->sc_dev, "can't map bus space\n");
137 return;
138 }
139
140 if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
141 aprint_error_dev(sc->sc_dev,
142 "couldn't establish power handler\n");
143
144 zssp_init();
145
146 /* Attach all devices */
147 config_search(self, sc,
148 CFARG_SUBMATCH, zssp_search,
149 CFARG_IATTR, "zssp",
150 CFARG_EOL);
151 }
152
153 static int
154 zssp_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
155 {
156 struct zssp_attach_args aa;
157
158 aa.zaa_name = cf->cf_name;
159
160 if (config_match(parent, cf, &aa))
161 config_attach(parent, cf, &aa, zssp_print);
162
163 return 0;
164 }
165
166 static int
167 zssp_print(void *aux, const char *name)
168 {
169
170 return UNCONF;
171 }
172
173 /*
174 * Initialize the dedicated SSP unit and disable all chip selects.
175 * This function is called with interrupts disabled.
176 */
177 static void
178 zssp_init(void)
179 {
180 struct zssp_softc *sc;
181
182 if (__predict_false(zssp_sc == NULL)) {
183 aprint_error("%s: not configured.\n", __func__);
184 return;
185 }
186 sc = zssp_sc;
187
188 pxa2x0_clkman_config(CKEN_SSP, 1);
189
190 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->lz9jg18.sscr0);
191 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
192
193 pxa2x0_gpio_set_function(sc->ads7846.gpio, GPIO_OUT|GPIO_SET);
194 pxa2x0_gpio_set_function(sc->max1111.gpio, GPIO_OUT|GPIO_SET);
195 pxa2x0_gpio_set_function(sc->lz9jg18.gpio, GPIO_OUT|GPIO_SET);
196 }
197
198 static bool
199 zssp_resume(device_t dv, const pmf_qual_t *qual)
200 {
201 int s;
202
203 s = splhigh();
204 zssp_init();
205 splx(s);
206
207 return true;
208 }
209
210 /*
211 * Transmit a single data word to one of the ICs, keep the chip selected
212 * afterwards, and don't wait for data to be returned in SSDR. Interrupts
213 * must be held off until zssp_ic_stop() gets called.
214 */
215 void
216 zssp_ic_start(int ic, uint32_t data)
217 {
218 struct zssp_softc *sc;
219
220 if (__predict_false(zssp_sc == NULL)) {
221 aprint_error("%s: not configured.\n", __func__);
222 return;
223 }
224 sc = zssp_sc;
225
226 /* disable other ICs */
227 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
228 if (ic != ZSSP_IC_ADS7846)
229 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
230 if (ic != ZSSP_IC_LZ9JG18)
231 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
232 if (ic != ZSSP_IC_MAX1111)
233 pxa2x0_gpio_set_bit(sc->max1111.gpio);
234
235 /* activate the chosen one */
236 switch (ic) {
237 case ZSSP_IC_ADS7846:
238 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
239 sc->ads7846.sscr0);
240 pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
241 delay(1); /* ADS7846 Tcss = 100ns */
242 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
243 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
244 & SSSR_TNF) != SSSR_TNF)
245 continue; /* poll */
246 break;
247 case ZSSP_IC_LZ9JG18:
248 pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
249 break;
250 case ZSSP_IC_MAX1111:
251 pxa2x0_gpio_clear_bit(sc->max1111.gpio);
252 break;
253 }
254 }
255
256 /*
257 * Read the last value from SSDR and deactivate all chip-selects.
258 */
259 uint32_t
260 zssp_ic_stop(int ic)
261 {
262 struct zssp_softc *sc;
263 uint32_t rv;
264
265 if (__predict_false(zssp_sc == NULL)) {
266 aprint_error("%s: not configured.\n", __func__);
267 return 0;
268 }
269 sc = zssp_sc;
270
271 switch (ic) {
272 case ZSSP_IC_ADS7846:
273 /* read result of last command */
274 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
275 & SSSR_RNE) != SSSR_RNE)
276 continue; /* poll */
277 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
278 break;
279 case ZSSP_IC_LZ9JG18:
280 case ZSSP_IC_MAX1111:
281 /* last value received is irrelevant or undefined */
282 default:
283 rv = 0;
284 break;
285 }
286
287 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
288 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
289 pxa2x0_gpio_set_bit(sc->max1111.gpio);
290
291 return rv;
292 }
293
294 /*
295 * Activate one of the chip-select lines, transmit one word value in
296 * each direction, and deactivate the chip-select again.
297 */
298 uint32_t
299 zssp_ic_send(int ic, uint32_t data)
300 {
301
302 switch (ic) {
303 case ZSSP_IC_MAX1111:
304 return (zssp_read_max1111(data));
305 case ZSSP_IC_ADS7846:
306 return (zssp_read_ads7846(data));
307 case ZSSP_IC_LZ9JG18:
308 zssp_write_lz9jg18(data);
309 return 0;
310 default:
311 aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
312 return 0;
313 }
314 }
315
316 int
317 zssp_read_max1111(uint32_t cmd)
318 {
319 struct zssp_softc *sc;
320 int data[3];
321 int voltage[3]; /* voltage[0]: dummy */
322 int i;
323 int s;
324
325 if (__predict_false(zssp_sc == NULL)) {
326 aprint_error("%s: not configured.\n", __func__);
327 return 0;
328 }
329 sc = zssp_sc;
330
331 s = splhigh();
332
333 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
334 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->max1111.sscr0);
335
336 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
337 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
338 pxa2x0_gpio_clear_bit(sc->max1111.gpio);
339
340 delay(1);
341
342 memset(data, 0, sizeof(data));
343 data[0] = cmd;
344 for (i = 0; i < __arraycount(data); i++) {
345 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
346 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
347 & SSSR_TNF) != SSSR_TNF)
348 continue; /* poll */
349 /* XXX is this delay necessary? */
350 delay(1);
351 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
352 & SSSR_RNE) != SSSR_RNE)
353 continue; /* poll */
354 voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
355 SSP_SSDR);
356 }
357
358 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
359 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
360 pxa2x0_gpio_set_bit(sc->max1111.gpio);
361
362 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
363
364 splx(s);
365
366 /* XXX no idea what this means, but it's what Linux would do. */
367 if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
368 return -1;
369 return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
370 }
371
372 /* XXX - only does CS_ADS7846 */
373 uint32_t
374 zssp_read_ads7846(uint32_t cmd)
375 {
376 struct zssp_softc *sc;
377 uint32_t val;
378 int s;
379
380 if (__predict_false(zssp_sc == NULL)) {
381 aprint_error("%s: not configured\n", __func__);
382 return 0;
383 }
384 sc = zssp_sc;
385
386 s = splhigh();
387
388 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
389 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->ads7846.sscr0);
390
391 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
392 pxa2x0_gpio_set_bit(sc->max1111.gpio);
393 pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
394 delay(1); /* ADS7846 Tcss = 100ns */
395
396 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
397
398 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
399 & SSSR_TNF) != SSSR_TNF)
400 continue; /* poll */
401
402 delay(1);
403
404 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
405 & SSSR_RNE) != SSSR_RNE)
406 continue; /* poll */
407
408 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
409
410 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
411
412 splx(s);
413
414 return val;
415 }
416
417 void
418 zssp_write_lz9jg18(uint32_t data)
419 {
420 struct zssp_softc *sc;
421 int sclk_fn;
422 int sfrm_fn;
423 int txd_fn;
424 int rxd_fn;
425 int i;
426 int s;
427
428 KASSERT(zssp_sc != NULL);
429 sc = zssp_sc;
430
431 /* XXX this creates a DAC command from a backlight duty value. */
432 data = 0x40 | (data & 0x1f);
433
434 s = splhigh();
435
436 sclk_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sclk_pin);
437 sfrm_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sfrm_pin);
438 txd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.txd_pin);
439 rxd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.rxd_pin);
440
441 pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, GPIO_OUT | GPIO_SET);
442 pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, GPIO_OUT | GPIO_CLR);
443 pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, GPIO_OUT | GPIO_CLR);
444 pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, GPIO_IN);
445
446 pxa2x0_gpio_set_bit(sc->max1111.gpio);
447 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
448 pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
449
450 delay(10);
451
452 for (i = 0; i < 8; i++) {
453 if (data & 0x80)
454 pxa2x0_gpio_set_bit(sc->lz9jg18.txd_pin);
455 else
456 pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
457 delay(10);
458 pxa2x0_gpio_set_bit(sc->lz9jg18.sclk_pin);
459 delay(10);
460 pxa2x0_gpio_clear_bit(sc->lz9jg18.sclk_pin);
461 delay(10);
462 data <<= 1;
463 }
464
465 pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
466 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
467
468 pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, sclk_fn);
469 pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, sfrm_fn);
470 pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, txd_fn);
471 pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, rxd_fn);
472
473 splx(s);
474 }
475