acpi_cpu.h revision 1.37.2.2
1 1.37.2.2 rmind /* $NetBSD: acpi_cpu.h,v 1.37.2.2 2011/03/05 20:53:02 rmind Exp $ */ 2 1.37.2.2 rmind 3 1.37.2.2 rmind /*- 4 1.37.2.2 rmind * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen (at) iki.fi> 5 1.37.2.2 rmind * All rights reserved. 6 1.37.2.2 rmind * 7 1.37.2.2 rmind * Redistribution and use in source and binary forms, with or without 8 1.37.2.2 rmind * modification, are permitted provided that the following conditions 9 1.37.2.2 rmind * are met: 10 1.37.2.2 rmind * 11 1.37.2.2 rmind * 1. Redistributions of source code must retain the above copyright 12 1.37.2.2 rmind * notice, this list of conditions and the following disclaimer. 13 1.37.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 14 1.37.2.2 rmind * notice, this list of conditions and the following disclaimer in the 15 1.37.2.2 rmind * documentation and/or other materials provided with the distribution. 16 1.37.2.2 rmind * 17 1.37.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 1.37.2.2 rmind * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 1.37.2.2 rmind * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 1.37.2.2 rmind * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 1.37.2.2 rmind * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 1.37.2.2 rmind * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 1.37.2.2 rmind * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.37.2.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 1.37.2.2 rmind * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 1.37.2.2 rmind * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 1.37.2.2 rmind * SUCH DAMAGE. 28 1.37.2.2 rmind */ 29 1.37.2.2 rmind 30 1.37.2.2 rmind #ifndef _SYS_DEV_ACPI_ACPI_CPU_H 31 1.37.2.2 rmind #define _SYS_DEV_ACPI_ACPI_CPU_H 32 1.37.2.2 rmind 33 1.37.2.2 rmind /* 34 1.37.2.2 rmind * The following _PDC values are based on: 35 1.37.2.2 rmind * 36 1.37.2.2 rmind * Intel Corporation: Intel Processor-Specific ACPI 37 1.37.2.2 rmind * Interface Specification, September 2006, Revision 005. 38 1.37.2.2 rmind */ 39 1.37.2.2 rmind #define ACPICPU_PDC_REVID 0x1 40 1.37.2.2 rmind #define ACPICPU_PDC_SMP 0xA 41 1.37.2.2 rmind #define ACPICPU_PDC_MSR 0x1 42 1.37.2.2 rmind 43 1.37.2.2 rmind #define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */ 44 1.37.2.2 rmind #define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */ 45 1.37.2.2 rmind #define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */ 46 1.37.2.2 rmind #define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */ 47 1.37.2.2 rmind #define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */ 48 1.37.2.2 rmind #define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */ 49 1.37.2.2 rmind #define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */ 50 1.37.2.2 rmind #define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */ 51 1.37.2.2 rmind #define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */ 52 1.37.2.2 rmind #define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */ 53 1.37.2.2 rmind #define ACPICPU_PDC_P_HWF __BIT(11) /* Px hardware feedback */ 54 1.37.2.2 rmind 55 1.37.2.2 rmind #define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */ 56 1.37.2.2 rmind #define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */ 57 1.37.2.2 rmind 58 1.37.2.2 rmind /* 59 1.37.2.2 rmind * Notify values. 60 1.37.2.2 rmind */ 61 1.37.2.2 rmind #define ACPICPU_P_NOTIFY 0x80 /* _PPC */ 62 1.37.2.2 rmind #define ACPICPU_C_NOTIFY 0x81 /* _CST */ 63 1.37.2.2 rmind #define ACPICPU_T_NOTIFY 0x82 /* _TPC */ 64 1.37.2.2 rmind 65 1.37.2.2 rmind /* 66 1.37.2.2 rmind * Dependency coordination. 67 1.37.2.2 rmind */ 68 1.37.2.2 rmind #define ACPICPU_DEP_SW_ALL 0xFC /* All CPUs must set a state */ 69 1.37.2.2 rmind #define ACPICPU_DEP_SW_ANY 0xFD /* Any CPU can set a state */ 70 1.37.2.2 rmind #define ACPICPU_DEP_HW_ALL 0xFE /* HW does the coordination */ 71 1.37.2.2 rmind 72 1.37.2.2 rmind /* 73 1.37.2.2 rmind * C-states. 74 1.37.2.2 rmind */ 75 1.37.2.2 rmind #define ACPICPU_C_C2_LATENCY_MAX 100 /* us */ 76 1.37.2.2 rmind #define ACPICPU_C_C3_LATENCY_MAX 1000 /* us */ 77 1.37.2.2 rmind 78 1.37.2.2 rmind #define ACPICPU_C_STATE_HALT 0x01 79 1.37.2.2 rmind #define ACPICPU_C_STATE_FFH 0x02 80 1.37.2.2 rmind #define ACPICPU_C_STATE_SYSIO 0x03 81 1.37.2.2 rmind 82 1.37.2.2 rmind /* 83 1.37.2.2 rmind * P-states. 84 1.37.2.2 rmind */ 85 1.37.2.2 rmind #define ACPICPU_P_STATE_MAX 255 /* Arbitrary upper limit */ 86 1.37.2.2 rmind #define ACPICPU_P_STATE_RETRY 100 87 1.37.2.2 rmind #define ACPICPU_P_STATE_UNKNOWN 0x0 88 1.37.2.2 rmind 89 1.37.2.2 rmind /* 90 1.37.2.2 rmind * T-states. 91 1.37.2.2 rmind */ 92 1.37.2.2 rmind #define ACPICPU_T_STATE_MAX 0x8 93 1.37.2.2 rmind #define ACPICPU_T_STATE_RETRY 0xA 94 1.37.2.2 rmind #define ACPICPU_T_STATE_UNKNOWN 255 95 1.37.2.2 rmind 96 1.37.2.2 rmind /* 97 1.37.2.2 rmind * Flags. 98 1.37.2.2 rmind */ 99 1.37.2.2 rmind #define ACPICPU_FLAG_C __BIT(0) /* C-states supported */ 100 1.37.2.2 rmind #define ACPICPU_FLAG_P __BIT(1) /* P-states supported */ 101 1.37.2.2 rmind #define ACPICPU_FLAG_T __BIT(2) /* T-states supported */ 102 1.37.2.2 rmind 103 1.37.2.2 rmind #define ACPICPU_FLAG_PIIX4 __BIT(3) /* Broken (quirk) */ 104 1.37.2.2 rmind 105 1.37.2.2 rmind #define ACPICPU_FLAG_C_FFH __BIT(4) /* Native C-states */ 106 1.37.2.2 rmind #define ACPICPU_FLAG_C_FADT __BIT(5) /* C-states with FADT */ 107 1.37.2.2 rmind #define ACPICPU_FLAG_C_DEP __BIT(6) /* C-state CPU coordination */ 108 1.37.2.2 rmind #define ACPICPU_FLAG_C_BM __BIT(7) /* Bus master control */ 109 1.37.2.2 rmind #define ACPICPU_FLAG_C_BM_STS __BIT(8) /* Bus master check required */ 110 1.37.2.2 rmind #define ACPICPU_FLAG_C_ARB __BIT(9) /* Bus master arbitration */ 111 1.37.2.2 rmind #define ACPICPU_FLAG_C_TSC __BIT(10) /* TSC broken, > C1, Px, Tx */ 112 1.37.2.2 rmind #define ACPICPU_FLAG_C_APIC __BIT(11) /* APIC timer broken, > C1 */ 113 1.37.2.2 rmind #define ACPICPU_FLAG_C_C1E __BIT(12) /* AMD C1E detected */ 114 1.37.2.2 rmind 115 1.37.2.2 rmind #define ACPICPU_FLAG_P_FFH __BIT(13) /* Native P-states */ 116 1.37.2.2 rmind #define ACPICPU_FLAG_P_DEP __BIT(14) /* P-state CPU coordination */ 117 1.37.2.2 rmind #define ACPICPU_FLAG_P_HWF __BIT(15) /* HW feedback supported */ 118 1.37.2.2 rmind #define ACPICPU_FLAG_P_XPSS __BIT(16) /* Microsoft XPSS in use */ 119 1.37.2.2 rmind #define ACPICPU_FLAG_P_TURBO __BIT(17) /* Turbo Boost / Turbo Core */ 120 1.37.2.2 rmind #define ACPICPU_FLAG_P_FIDVID __BIT(18) /* AMD "FID/VID algorithm" */ 121 1.37.2.2 rmind 122 1.37.2.2 rmind #define ACPICPU_FLAG_T_FFH __BIT(19) /* Native throttling */ 123 1.37.2.2 rmind #define ACPICPU_FLAG_T_FADT __BIT(20) /* Throttling with FADT */ 124 1.37.2.2 rmind #define ACPICPU_FLAG_T_DEP __BIT(21) /* T-state CPU coordination */ 125 1.37.2.2 rmind 126 1.37.2.2 rmind /* 127 1.37.2.2 rmind * This is AML_RESOURCE_GENERIC_REGISTER, 128 1.37.2.2 rmind * included here separately for convenience. 129 1.37.2.2 rmind */ 130 1.37.2.2 rmind struct acpicpu_reg { 131 1.37.2.2 rmind uint8_t reg_desc; 132 1.37.2.2 rmind uint16_t reg_reslen; 133 1.37.2.2 rmind uint8_t reg_spaceid; 134 1.37.2.2 rmind uint8_t reg_bitwidth; 135 1.37.2.2 rmind uint8_t reg_bitoffset; 136 1.37.2.2 rmind uint8_t reg_accesssize; 137 1.37.2.2 rmind uint64_t reg_addr; 138 1.37.2.2 rmind } __packed; 139 1.37.2.2 rmind 140 1.37.2.2 rmind struct acpicpu_dep { 141 1.37.2.2 rmind uint32_t dep_domain; 142 1.37.2.2 rmind uint32_t dep_type; 143 1.37.2.2 rmind uint32_t dep_ncpus; 144 1.37.2.2 rmind uint32_t dep_index; 145 1.37.2.2 rmind }; 146 1.37.2.2 rmind 147 1.37.2.2 rmind struct acpicpu_cstate { 148 1.37.2.2 rmind struct evcnt cs_evcnt; 149 1.37.2.2 rmind char cs_name[EVCNT_STRING_MAX]; 150 1.37.2.2 rmind uint64_t cs_addr; 151 1.37.2.2 rmind uint32_t cs_power; 152 1.37.2.2 rmind uint32_t cs_latency; 153 1.37.2.2 rmind int cs_method; 154 1.37.2.2 rmind int cs_flags; 155 1.37.2.2 rmind }; 156 1.37.2.2 rmind 157 1.37.2.2 rmind /* 158 1.37.2.2 rmind * This structure supports both the conventional _PSS and the 159 1.37.2.2 rmind * so-called extended _PSS (XPSS). For the latter, refer to: 160 1.37.2.2 rmind * 161 1.37.2.2 rmind * Microsoft Corporation: Extended PSS ACPI 162 1.37.2.2 rmind * Method Specification, April 2, 2007. 163 1.37.2.2 rmind */ 164 1.37.2.2 rmind struct acpicpu_pstate { 165 1.37.2.2 rmind struct evcnt ps_evcnt; 166 1.37.2.2 rmind char ps_name[EVCNT_STRING_MAX]; 167 1.37.2.2 rmind uint32_t ps_freq; 168 1.37.2.2 rmind uint32_t ps_power; 169 1.37.2.2 rmind uint32_t ps_latency; 170 1.37.2.2 rmind uint32_t ps_latency_bm; 171 1.37.2.2 rmind uint64_t ps_control; 172 1.37.2.2 rmind uint64_t ps_control_addr; 173 1.37.2.2 rmind uint64_t ps_control_mask; 174 1.37.2.2 rmind uint64_t ps_status; 175 1.37.2.2 rmind uint64_t ps_status_addr; 176 1.37.2.2 rmind uint64_t ps_status_mask; 177 1.37.2.2 rmind int ps_flags; 178 1.37.2.2 rmind }; 179 1.37.2.2 rmind 180 1.37.2.2 rmind struct acpicpu_tstate { 181 1.37.2.2 rmind struct evcnt ts_evcnt; 182 1.37.2.2 rmind char ts_name[EVCNT_STRING_MAX]; 183 1.37.2.2 rmind uint32_t ts_percent; 184 1.37.2.2 rmind uint32_t ts_power; 185 1.37.2.2 rmind uint32_t ts_latency; 186 1.37.2.2 rmind uint32_t ts_control; 187 1.37.2.2 rmind uint32_t ts_status; 188 1.37.2.2 rmind }; 189 1.37.2.2 rmind 190 1.37.2.2 rmind struct acpicpu_object { 191 1.37.2.2 rmind uint32_t ao_procid; 192 1.37.2.2 rmind uint32_t ao_pblklen; 193 1.37.2.2 rmind uint32_t ao_pblkaddr; 194 1.37.2.2 rmind }; 195 1.37.2.2 rmind 196 1.37.2.2 rmind struct acpicpu_softc { 197 1.37.2.2 rmind device_t sc_dev; 198 1.37.2.2 rmind struct cpu_info *sc_ci; 199 1.37.2.2 rmind struct acpi_devnode *sc_node; 200 1.37.2.2 rmind struct acpicpu_object sc_object; 201 1.37.2.2 rmind 202 1.37.2.2 rmind struct acpicpu_cstate sc_cstate[ACPI_C_STATE_COUNT]; 203 1.37.2.2 rmind struct acpicpu_dep sc_cstate_dep; 204 1.37.2.2 rmind uint32_t sc_cstate_sleep; 205 1.37.2.2 rmind 206 1.37.2.2 rmind struct acpicpu_pstate *sc_pstate; 207 1.37.2.2 rmind struct acpicpu_dep sc_pstate_dep; 208 1.37.2.2 rmind struct acpicpu_reg sc_pstate_control; 209 1.37.2.2 rmind struct acpicpu_reg sc_pstate_status; 210 1.37.2.2 rmind uint64_t sc_pstate_aperf; /* ACPICPU_FLAG_P_HW */ 211 1.37.2.2 rmind uint64_t sc_pstate_mperf; /* ACPICPU_FLAG_P_HW*/ 212 1.37.2.2 rmind uint32_t sc_pstate_current; 213 1.37.2.2 rmind uint32_t sc_pstate_count; 214 1.37.2.2 rmind uint32_t sc_pstate_max; 215 1.37.2.2 rmind uint32_t sc_pstate_min; 216 1.37.2.2 rmind 217 1.37.2.2 rmind struct acpicpu_tstate *sc_tstate; 218 1.37.2.2 rmind struct acpicpu_dep sc_tstate_dep; 219 1.37.2.2 rmind struct acpicpu_reg sc_tstate_control; 220 1.37.2.2 rmind struct acpicpu_reg sc_tstate_status; 221 1.37.2.2 rmind uint32_t sc_tstate_current; 222 1.37.2.2 rmind uint32_t sc_tstate_count; 223 1.37.2.2 rmind uint32_t sc_tstate_max; 224 1.37.2.2 rmind uint32_t sc_tstate_min; 225 1.37.2.2 rmind 226 1.37.2.2 rmind kmutex_t sc_mtx; 227 1.37.2.2 rmind uint32_t sc_cap; 228 1.37.2.2 rmind uint32_t sc_ncpus; 229 1.37.2.2 rmind uint32_t sc_flags; 230 1.37.2.2 rmind bool sc_cold; 231 1.37.2.2 rmind }; 232 1.37.2.2 rmind 233 1.37.2.2 rmind void acpicpu_cstate_attach(device_t); 234 1.37.2.2 rmind int acpicpu_cstate_detach(device_t); 235 1.37.2.2 rmind void acpicpu_cstate_start(device_t); 236 1.37.2.2 rmind bool acpicpu_cstate_suspend(device_t); 237 1.37.2.2 rmind bool acpicpu_cstate_resume(device_t); 238 1.37.2.2 rmind void acpicpu_cstate_callback(void *); 239 1.37.2.2 rmind void acpicpu_cstate_idle(void); 240 1.37.2.2 rmind 241 1.37.2.2 rmind void acpicpu_pstate_attach(device_t); 242 1.37.2.2 rmind int acpicpu_pstate_detach(device_t); 243 1.37.2.2 rmind void acpicpu_pstate_start(device_t); 244 1.37.2.2 rmind bool acpicpu_pstate_suspend(device_t); 245 1.37.2.2 rmind bool acpicpu_pstate_resume(device_t); 246 1.37.2.2 rmind void acpicpu_pstate_callback(void *); 247 1.37.2.2 rmind int acpicpu_pstate_get(struct cpu_info *, uint32_t *); 248 1.37.2.2 rmind void acpicpu_pstate_set(struct cpu_info *, uint32_t); 249 1.37.2.2 rmind 250 1.37.2.2 rmind void acpicpu_tstate_attach(device_t); 251 1.37.2.2 rmind int acpicpu_tstate_detach(device_t); 252 1.37.2.2 rmind void acpicpu_tstate_start(device_t); 253 1.37.2.2 rmind bool acpicpu_tstate_suspend(device_t); 254 1.37.2.2 rmind bool acpicpu_tstate_resume(device_t); 255 1.37.2.2 rmind void acpicpu_tstate_callback(void *); 256 1.37.2.2 rmind int acpicpu_tstate_get(struct cpu_info *, uint32_t *); 257 1.37.2.2 rmind void acpicpu_tstate_set(struct cpu_info *, uint32_t); 258 1.37.2.2 rmind 259 1.37.2.2 rmind struct cpu_info *acpicpu_md_match(device_t, cfdata_t, void *); 260 1.37.2.2 rmind struct cpu_info *acpicpu_md_attach(device_t, device_t, void *); 261 1.37.2.2 rmind 262 1.37.2.2 rmind uint32_t acpicpu_md_cap(void); 263 1.37.2.2 rmind uint32_t acpicpu_md_flags(void); 264 1.37.2.2 rmind void acpicpu_md_quirk_c1e(void); 265 1.37.2.2 rmind int acpicpu_md_cstate_start(struct acpicpu_softc *); 266 1.37.2.2 rmind int acpicpu_md_cstate_stop(void); 267 1.37.2.2 rmind void acpicpu_md_cstate_enter(int, int); 268 1.37.2.2 rmind int acpicpu_md_pstate_start(struct acpicpu_softc *); 269 1.37.2.2 rmind int acpicpu_md_pstate_stop(void); 270 1.37.2.2 rmind int acpicpu_md_pstate_pss(struct acpicpu_softc *); 271 1.37.2.2 rmind uint8_t acpicpu_md_pstate_percent(struct acpicpu_softc *); 272 1.37.2.2 rmind int acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *); 273 1.37.2.2 rmind int acpicpu_md_pstate_set(struct acpicpu_pstate *); 274 1.37.2.2 rmind int acpicpu_md_tstate_get(struct acpicpu_softc *, uint32_t *); 275 1.37.2.2 rmind int acpicpu_md_tstate_set(struct acpicpu_tstate *); 276 1.37.2.2 rmind 277 1.37.2.2 rmind #endif /* !_SYS_DEV_ACPI_ACPI_CPU_H */ 278
Indexes created Thu Oct 02 14:10:14 GMT 2025