acpi_cpu.h revision 1.29
1 /* $NetBSD: acpi_cpu.h,v 1.29 2011/02/25 06:18:02 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _SYS_DEV_ACPI_ACPI_CPU_H 31 #define _SYS_DEV_ACPI_ACPI_CPU_H 32 33 /* 34 * The following _PDC values are based on: 35 * 36 * Intel Corporation: Intel Processor-Specific ACPI 37 * Interface Specification, September 2006, Revision 005. 38 */ 39 #define ACPICPU_PDC_REVID 0x1 40 #define ACPICPU_PDC_SMP 0xA 41 #define ACPICPU_PDC_MSR 0x1 42 43 #define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */ 44 #define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */ 45 #define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */ 46 #define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */ 47 #define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */ 48 #define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */ 49 #define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */ 50 #define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */ 51 #define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */ 52 #define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */ 53 #define ACPICPU_PDC_P_HW __BIT(11) /* Px hardware coordination */ 54 55 #define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */ 56 #define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */ 57 58 /* 59 * Notify values. 60 */ 61 #define ACPICPU_P_NOTIFY 0x80 /* _PPC */ 62 #define ACPICPU_C_NOTIFY 0x81 /* _CST */ 63 #define ACPICPU_T_NOTIFY 0x82 /* _TPC */ 64 65 /* 66 * C-states. 67 */ 68 #define ACPICPU_C_C2_LATENCY_MAX 100 /* us */ 69 #define ACPICPU_C_C3_LATENCY_MAX 1000 /* us */ 70 71 #define ACPICPU_C_STATE_HALT 0x01 72 #define ACPICPU_C_STATE_FFH 0x02 73 #define ACPICPU_C_STATE_SYSIO 0x03 74 75 /* 76 * P-states. 77 */ 78 #define ACPICPU_P_STATE_MAX 255 /* Arbitrary upper limit */ 79 #define ACPICPU_P_STATE_RETRY 100 80 #define ACPICPU_P_STATE_UNKNOWN 0x0 81 82 /* 83 * T-states. 84 */ 85 #define ACPICPU_T_STATE_MAX 0x8 86 #define ACPICPU_T_STATE_RETRY 0xA 87 #define ACPICPU_T_STATE_UNKNOWN 255 88 89 /* 90 * Flags. 91 */ 92 #define ACPICPU_FLAG_C __BIT(0) /* C-states supported */ 93 #define ACPICPU_FLAG_P __BIT(1) /* P-states supported */ 94 #define ACPICPU_FLAG_T __BIT(2) /* T-states supported */ 95 96 #define ACPICPU_FLAG_PIIX4 __BIT(3) /* Broken (quirk) */ 97 98 #define ACPICPU_FLAG_C_FFH __BIT(4) /* Native C-states */ 99 #define ACPICPU_FLAG_C_FADT __BIT(5) /* C-states with FADT */ 100 #define ACPICPU_FLAG_C_BM __BIT(6) /* Bus master control */ 101 #define ACPICPU_FLAG_C_BM_STS __BIT(7) /* Bus master check required */ 102 #define ACPICPU_FLAG_C_ARB __BIT(8) /* Bus master arbitration */ 103 #define ACPICPU_FLAG_C_TSC __BIT(9) /* TSC broken, > C1, Px, Tx */ 104 #define ACPICPU_FLAG_C_APIC __BIT(10) /* APIC timer broken, > C1 */ 105 #define ACPICPU_FLAG_C_C1E __BIT(11) /* AMD C1E detected */ 106 107 #define ACPICPU_FLAG_P_FFH __BIT(12) /* Native P-states */ 108 #define ACPICPU_FLAG_P_HW __BIT(13) /* HW coordination supported */ 109 #define ACPICPU_FLAG_P_XPSS __BIT(14) /* Microsoft XPSS in use */ 110 #define ACPICPU_FLAG_P_TURBO __BIT(15) /* Turbo Boost / Turbo Core */ 111 #define ACPICPU_FLAG_P_FIDVID __BIT(16) /* AMD "FID/VID algorithm" */ 112 113 #define ACPICPU_FLAG_T_FFH __BIT(17) /* Native throttling */ 114 #define ACPICPU_FLAG_T_FADT __BIT(18) /* Throttling with FADT */ 115 116 /* 117 * This is AML_RESOURCE_GENERIC_REGISTER, 118 * included here separately for convenience. 119 */ 120 struct acpicpu_reg { 121 uint8_t reg_desc; 122 uint16_t reg_reslen; 123 uint8_t reg_spaceid; 124 uint8_t reg_bitwidth; 125 uint8_t reg_bitoffset; 126 uint8_t reg_accesssize; 127 uint64_t reg_addr; 128 } __packed; 129 130 struct acpicpu_cstate { 131 struct evcnt cs_evcnt; 132 char cs_name[EVCNT_STRING_MAX]; 133 uint64_t cs_addr; 134 uint32_t cs_power; 135 uint32_t cs_latency; 136 int cs_method; 137 int cs_flags; 138 }; 139 140 /* 141 * This structure supports both the conventional _PSS and the 142 * so-called extended _PSS (XPSS). For the latter, refer to: 143 * 144 * Microsoft Corporation: Extended PSS ACPI 145 * Method Specification, April 2, 2007. 146 */ 147 struct acpicpu_pstate { 148 struct evcnt ps_evcnt; 149 char ps_name[EVCNT_STRING_MAX]; 150 uint32_t ps_freq; 151 uint32_t ps_power; 152 uint32_t ps_latency; 153 uint32_t ps_latency_bm; 154 uint64_t ps_control; 155 uint64_t ps_control_addr; 156 uint64_t ps_control_mask; 157 uint64_t ps_status; 158 uint64_t ps_status_addr; 159 uint64_t ps_status_mask; 160 int ps_flags; 161 }; 162 163 struct acpicpu_tstate { 164 struct evcnt ts_evcnt; 165 char ts_name[EVCNT_STRING_MAX]; 166 uint32_t ts_percent; 167 uint32_t ts_power; 168 uint32_t ts_latency; 169 uint32_t ts_control; 170 uint32_t ts_status; 171 }; 172 173 struct acpicpu_object { 174 uint32_t ao_procid; 175 uint32_t ao_pblklen; 176 uint32_t ao_pblkaddr; 177 }; 178 179 struct acpicpu_softc { 180 device_t sc_dev; 181 struct cpu_info *sc_ci; 182 struct acpi_devnode *sc_node; 183 struct acpicpu_object sc_object; 184 185 struct acpicpu_cstate sc_cstate[ACPI_C_STATE_COUNT]; 186 uint32_t sc_cstate_sleep; 187 188 struct acpicpu_pstate *sc_pstate; 189 struct acpicpu_reg sc_pstate_control; 190 struct acpicpu_reg sc_pstate_status; 191 uint32_t sc_pstate_current; 192 uint32_t sc_pstate_count; 193 uint32_t sc_pstate_max; 194 uint32_t sc_pstate_min; 195 196 struct acpicpu_tstate *sc_tstate; 197 struct acpicpu_reg sc_tstate_control; 198 struct acpicpu_reg sc_tstate_status; 199 uint32_t sc_tstate_current; 200 uint32_t sc_tstate_count; 201 uint32_t sc_tstate_max; 202 uint32_t sc_tstate_min; 203 204 kmutex_t sc_mtx; 205 uint32_t sc_cap; 206 uint32_t sc_flags; 207 bool sc_cold; 208 }; 209 210 void acpicpu_cstate_attach(device_t); 211 int acpicpu_cstate_detach(device_t); 212 void acpicpu_cstate_start(device_t); 213 bool acpicpu_cstate_suspend(device_t); 214 bool acpicpu_cstate_resume(device_t); 215 void acpicpu_cstate_callback(void *); 216 void acpicpu_cstate_idle(void); 217 218 void acpicpu_pstate_attach(device_t); 219 int acpicpu_pstate_detach(device_t); 220 void acpicpu_pstate_start(device_t); 221 bool acpicpu_pstate_suspend(device_t); 222 bool acpicpu_pstate_resume(device_t); 223 void acpicpu_pstate_callback(void *); 224 int acpicpu_pstate_get(struct acpicpu_softc *, uint32_t *); 225 int acpicpu_pstate_set(struct acpicpu_softc *, uint32_t); 226 227 void acpicpu_tstate_attach(device_t); 228 int acpicpu_tstate_detach(device_t); 229 void acpicpu_tstate_start(device_t); 230 bool acpicpu_tstate_suspend(device_t); 231 bool acpicpu_tstate_resume(device_t); 232 void acpicpu_tstate_callback(void *); 233 int acpicpu_tstate_get(struct acpicpu_softc *, uint32_t *); 234 int acpicpu_tstate_set(struct acpicpu_softc *, uint32_t); 235 236 uint32_t acpicpu_md_cap(void); 237 uint32_t acpicpu_md_quirks(void); 238 void acpicpu_md_quirks_c1e(void); 239 int acpicpu_md_idle_start(struct acpicpu_softc *); 240 int acpicpu_md_idle_stop(void); 241 void acpicpu_md_idle_enter(int, int); 242 int acpicpu_md_pstate_start(void); 243 int acpicpu_md_pstate_stop(void); 244 int acpicpu_md_pstate_pss(struct acpicpu_softc *); 245 int acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *); 246 int acpicpu_md_pstate_set(struct acpicpu_pstate *); 247 int acpicpu_md_tstate_get(struct acpicpu_softc *, uint32_t *); 248 int acpicpu_md_tstate_set(struct acpicpu_tstate *); 249 250 #endif /* !_SYS_DEV_ACPI_ACPI_CPU_H */ 251
Indexes created Tue Sep 23 14:10:03 GMT 2025