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qcomiic.c revision 1.1 
      1 /* $NetBSD: qcomiic.c,v 1.1 2024/12/08 20:49:14 jmcneill Exp $ */
      2 
      3 /*	$OpenBSD: qciic.c,v 1.7 2024/10/02 21:21:32 kettenis Exp $	*/
      4 /*
      5  * Copyright (c) 2022 Mark Kettenis <kettenis (at) openbsd.org>
      6  *
      7  * Permission to use, copy, modify, and distribute this software for any
      8  * purpose with or without fee is hereby granted, provided that the above
      9  * copyright notice and this permission notice appear in all copies.
     10  *
     11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18  */
     19 
     20 #include <sys/param.h>
     21 #include <sys/bus.h>
     22 #include <sys/cpu.h>
     23 #include <sys/device.h>
     24 
     25 #include <dev/acpi/acpireg.h>
     26 #include <dev/acpi/acpivar.h>
     27 #include <dev/acpi/acpi_intr.h>
     28 #include <dev/acpi/acpi_i2c.h>
     29 
     30 #include <dev/i2c/i2cvar.h>
     31 
     32 /* Registers */
     33 #define GENI_I2C_TX_TRANS_LEN		0x26c
     34 #define GENI_I2C_RX_TRANS_LEN		0x270
     35 #define GENI_M_CMD0			0x600
     36 #define  GENI_M_CMD0_OPCODE_I2C_WRITE	(0x1 << 27)
     37 #define  GENI_M_CMD0_OPCODE_I2C_READ	(0x2 << 27)
     38 #define  GENI_M_CMD0_SLV_ADDR_SHIFT	9
     39 #define  GENI_M_CMD0_STOP_STRETCH	(1 << 2)
     40 #define GENI_M_IRQ_STATUS		0x610
     41 #define GENI_M_IRQ_CLEAR		0x618
     42 #define  GENI_M_IRQ_CMD_DONE		(1 << 0)
     43 #define GENI_TX_FIFO			0x700
     44 #define GENI_RX_FIFO			0x780
     45 #define GENI_TX_FIFO_STATUS		0x800
     46 #define GENI_RX_FIFO_STATUS		0x804
     47 #define  GENI_RX_FIFO_STATUS_WC(val)	((val) & 0xffffff)
     48 
     49 #define HREAD4(sc, reg)							\
     50 	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
     51 #define HWRITE4(sc, reg, val)						\
     52 	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
     53 
     54 struct qciic_softc {
     55 	device_t		sc_dev;
     56 	struct acpi_devnode	*sc_acpi;
     57 	bus_space_tag_t		sc_iot;
     58 	bus_space_handle_t	sc_ioh;
     59 
     60 	device_t		sc_iic;
     61 
     62 	struct i2c_controller	sc_ic;
     63 };
     64 
     65 static int	qciic_acpi_match(device_t, cfdata_t, void *);
     66 static void	qciic_acpi_attach(device_t, device_t, void *);
     67 static void	qciic_acpi_attach_late(device_t);
     68 static int	qciic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
     69 		    void *, size_t, int);
     70 
     71 CFATTACH_DECL_NEW(qcomiic, sizeof(struct qciic_softc),
     72     qciic_acpi_match, qciic_acpi_attach, NULL, NULL);
     73 
     74 static const struct device_compatible_entry compat_data[] = {
     75 	{ .compat = "QCOM0610" },
     76 	{ .compat = "QCOM0811" },
     77 	{ .compat = "QCOM0C10" },
     78 	DEVICE_COMPAT_EOL
     79 };
     80 
     81 static int
     82 qciic_acpi_match(device_t parent, cfdata_t cf, void *aux)
     83 {
     84 	struct acpi_attach_args *aa = aux;
     85 
     86 	return acpi_compatible_match(aa, compat_data);
     87 }
     88 
     89 static void
     90 qciic_acpi_attach(device_t parent, device_t self, void *aux)
     91 {
     92 	struct qciic_softc * const sc = device_private(self);
     93 	struct acpi_attach_args *aa = aux;
     94 	struct acpi_resources res;
     95 	struct acpi_mem *mem;
     96 	struct acpi_irq *irq;
     97 	ACPI_STATUS rv;
     98 	int error;
     99 
    100 	sc->sc_dev = self;
    101 	sc->sc_acpi = aa->aa_node;
    102 	sc->sc_iot = aa->aa_memt;
    103 
    104 	rv = acpi_resource_parse(sc->sc_dev, aa->aa_node->ad_handle, "_CRS",
    105 	    &res, &acpi_resource_parse_ops_default);
    106 	if (ACPI_FAILURE(rv)) {
    107 		return;
    108 	}
    109 
    110 	mem = acpi_res_mem(&res, 0);
    111 	if (mem == NULL) {
    112 		aprint_error_dev(self, "couldn't find mem resource\n");
    113 		goto done;
    114 	}
    115 
    116 	irq = acpi_res_irq(&res, 0);
    117 	if (irq == NULL) {
    118 		aprint_error_dev(self, "couldn't find irq resource\n");
    119 		goto done;
    120 	}
    121 
    122 	error = bus_space_map(sc->sc_iot, mem->ar_base, mem->ar_length, 0,
    123 	    &sc->sc_ioh);
    124 	if (error != 0) {
    125 		aprint_error_dev(self, "couldn't map registers\n");
    126 		return;
    127 	}
    128 
    129 	iic_tag_init(&sc->sc_ic);
    130 	sc->sc_ic.ic_cookie = sc;
    131 	sc->sc_ic.ic_exec = qciic_exec;
    132 
    133 	/*
    134 	 * Defer the attachment of I2C bus until all ACPI devices have been
    135 	 * enumerated, as other devices may provide resources for devices
    136 	 * attached to the I2C bus.
    137 	 */
    138 	config_defer(self, qciic_acpi_attach_late);
    139 
    140 done:
    141 	acpi_resource_cleanup(&res);
    142 }
    143 
    144 static void
    145 qciic_acpi_attach_late(device_t self)
    146 {
    147 	struct i2cbus_attach_args iba;
    148 	struct qciic_softc * const sc = device_private(self);
    149 
    150 	memset(&iba, 0, sizeof(iba));
    151 	iba.iba_tag = &sc->sc_ic;
    152 	iba.iba_child_devices = acpi_enter_i2c_devs(self, sc->sc_acpi);
    153 
    154 	config_found(self, &iba, iicbus_print, CFARGS_NONE);
    155 }
    156 
    157 static int
    158 qciic_wait(struct qciic_softc *sc, uint32_t bits)
    159 {
    160 	uint32_t stat;
    161 	int timo;
    162 
    163 	for (timo = 50000; timo > 0; timo--) {
    164 		stat = HREAD4(sc, GENI_M_IRQ_STATUS);
    165 		if (stat & bits)
    166 			break;
    167 		delay(10);
    168 	}
    169 	if (timo == 0)
    170 		return ETIMEDOUT;
    171 
    172 	return 0;
    173 }
    174 
    175 static int
    176 qciic_read(struct qciic_softc *sc, uint8_t *buf, size_t len)
    177 {
    178 	uint32_t stat, word;
    179 	int timo, i;
    180 
    181 	word = 0;
    182 	for (i = 0; i < len; i++) {
    183 		if ((i % 4) == 0) {
    184 			for (timo = 50000; timo > 0; timo--) {
    185 				stat = HREAD4(sc, GENI_RX_FIFO_STATUS);
    186 				if (GENI_RX_FIFO_STATUS_WC(stat) > 0)
    187 					break;
    188 				delay(10);
    189 			}
    190 			if (timo == 0)
    191 				return ETIMEDOUT;
    192 			word = HREAD4(sc, GENI_RX_FIFO);
    193 		}
    194 		buf[i] = word >> ((i % 4) * 8);
    195 	}
    196 
    197 	return 0;
    198 }
    199 
    200 static int
    201 qciic_write(struct qciic_softc *sc, const uint8_t *buf, size_t len)
    202 {
    203 	uint32_t stat, word;
    204 	int timo, i;
    205 
    206 	word = 0;
    207 	for (i = 0; i < len; i++) {
    208 		word |= buf[i] << ((i % 4) * 8);
    209 		if ((i % 4) == 3 || i == (len - 1)) {
    210 			for (timo = 50000; timo > 0; timo--) {
    211 				stat = HREAD4(sc, GENI_TX_FIFO_STATUS);
    212 				if (stat < 16)
    213 					break;
    214 				delay(10);
    215 			}
    216 			if (timo == 0)
    217 				return ETIMEDOUT;
    218 			HWRITE4(sc, GENI_TX_FIFO, word);
    219 			word = 0;
    220 		}
    221 	}
    222 
    223 	return 0;
    224 }
    225 
    226 static int
    227 qciic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd,
    228     size_t cmdlen, void *buf, size_t buflen, int flags)
    229 {
    230 	struct qciic_softc *sc = cookie;
    231 	uint32_t m_cmd, m_param, stat;
    232 	int error;
    233 
    234 	m_param = addr << GENI_M_CMD0_SLV_ADDR_SHIFT;
    235 	m_param |= GENI_M_CMD0_STOP_STRETCH;
    236 
    237 	if (buflen == 0 && I2C_OP_STOP_P(op))
    238 		m_param &= ~GENI_M_CMD0_STOP_STRETCH;
    239 
    240 	if (cmdlen > 0) {
    241 		stat = HREAD4(sc, GENI_M_IRQ_STATUS);
    242 		HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
    243 		HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen);
    244 		m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param;
    245 		HWRITE4(sc, GENI_M_CMD0, m_cmd);
    246 
    247 		error = qciic_write(sc, cmd, cmdlen);
    248 		if (error)
    249 			return error;
    250 
    251 		error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE);
    252 		if (error)
    253 			return error;
    254 	}
    255 
    256 	if (buflen == 0)
    257 		return 0;
    258 
    259 	if (I2C_OP_STOP_P(op))
    260 		m_param &= ~GENI_M_CMD0_STOP_STRETCH;
    261 
    262 	if (I2C_OP_READ_P(op)) {
    263 		stat = HREAD4(sc, GENI_M_IRQ_STATUS);
    264 		HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
    265 		HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen);
    266 		m_cmd = GENI_M_CMD0_OPCODE_I2C_READ | m_param;
    267 		HWRITE4(sc, GENI_M_CMD0, m_cmd);
    268 
    269 		error = qciic_read(sc, buf, buflen);
    270 		if (error)
    271 			return error;
    272 
    273 		error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE);
    274 		if (error)
    275 			return error;
    276 	} else {
    277 		stat = HREAD4(sc, GENI_M_IRQ_STATUS);
    278 		HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
    279 		HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen);
    280 		m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param;
    281 		HWRITE4(sc, GENI_M_CMD0, m_cmd);
    282 
    283 		error = qciic_write(sc, buf, buflen);
    284 		if (error)
    285 			return error;
    286 
    287 		error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE);
    288 		if (error)
    289 			return error;
    290 	}
    291 
    292 	return 0;
    293 }
    294