qcomiic.c revision 1.4
1 /* $NetBSD: qcomiic.c,v 1.4 2025/09/15 15:18:42 thorpej Exp $ */ 2 3 /* $OpenBSD: qciic.c,v 1.7 2024/10/02 21:21:32 kettenis Exp $ */ 4 /* 5 * Copyright (c) 2022 Mark Kettenis <kettenis (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/param.h> 21 #include <sys/bus.h> 22 #include <sys/cpu.h> 23 #include <sys/device.h> 24 25 #include <dev/acpi/acpireg.h> 26 #include <dev/acpi/acpivar.h> 27 #include <dev/acpi/acpi_intr.h> 28 #include <dev/acpi/acpi_i2c.h> 29 30 #include <dev/i2c/i2cvar.h> 31 32 /* Registers */ 33 #define GENI_I2C_TX_TRANS_LEN 0x26c 34 #define GENI_I2C_RX_TRANS_LEN 0x270 35 #define GENI_M_CMD0 0x600 36 #define GENI_M_CMD0_OPCODE_I2C_WRITE (0x1 << 27) 37 #define GENI_M_CMD0_OPCODE_I2C_READ (0x2 << 27) 38 #define GENI_M_CMD0_SLV_ADDR_SHIFT 9 39 #define GENI_M_CMD0_STOP_STRETCH (1 << 2) 40 #define GENI_M_IRQ_STATUS 0x610 41 #define GENI_M_IRQ_CLEAR 0x618 42 #define GENI_M_IRQ_CMD_DONE (1 << 0) 43 #define GENI_TX_FIFO 0x700 44 #define GENI_RX_FIFO 0x780 45 #define GENI_TX_FIFO_STATUS 0x800 46 #define GENI_RX_FIFO_STATUS 0x804 47 #define GENI_RX_FIFO_STATUS_WC(val) ((val) & 0xffffff) 48 49 #define HREAD4(sc, reg) \ 50 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 51 #define HWRITE4(sc, reg, val) \ 52 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 53 54 struct qciic_softc { 55 device_t sc_dev; 56 struct acpi_devnode *sc_acpi; 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 60 device_t sc_iic; 61 62 struct i2c_controller sc_ic; 63 }; 64 65 static int qciic_acpi_match(device_t, cfdata_t, void *); 66 static void qciic_acpi_attach(device_t, device_t, void *); 67 static int qciic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 68 void *, size_t, int); 69 70 CFATTACH_DECL_NEW(qcomiic, sizeof(struct qciic_softc), 71 qciic_acpi_match, qciic_acpi_attach, NULL, NULL); 72 73 static const struct device_compatible_entry compat_data[] = { 74 { .compat = "QCOM0610" }, 75 { .compat = "QCOM0811" }, 76 { .compat = "QCOM0C10" }, 77 DEVICE_COMPAT_EOL 78 }; 79 80 static int 81 qciic_acpi_match(device_t parent, cfdata_t cf, void *aux) 82 { 83 struct acpi_attach_args *aa = aux; 84 85 return acpi_compatible_match(aa, compat_data); 86 } 87 88 static void 89 qciic_acpi_attach(device_t parent, device_t self, void *aux) 90 { 91 struct qciic_softc * const sc = device_private(self); 92 struct acpi_attach_args *aa = aux; 93 struct acpi_resources res; 94 struct acpi_mem *mem; 95 struct acpi_irq *irq; 96 ACPI_STATUS rv; 97 int error; 98 99 sc->sc_dev = self; 100 sc->sc_acpi = aa->aa_node; 101 sc->sc_iot = aa->aa_memt; 102 103 rv = acpi_resource_parse(sc->sc_dev, aa->aa_node->ad_handle, "_CRS", 104 &res, &acpi_resource_parse_ops_default); 105 if (ACPI_FAILURE(rv)) { 106 return; 107 } 108 109 mem = acpi_res_mem(&res, 0); 110 if (mem == NULL) { 111 aprint_error_dev(self, "couldn't find mem resource\n"); 112 goto done; 113 } 114 115 irq = acpi_res_irq(&res, 0); 116 if (irq == NULL) { 117 aprint_error_dev(self, "couldn't find irq resource\n"); 118 goto done; 119 } 120 121 error = bus_space_map(sc->sc_iot, mem->ar_base, mem->ar_length, 0, 122 &sc->sc_ioh); 123 if (error != 0) { 124 aprint_error_dev(self, "couldn't map registers\n"); 125 return; 126 } 127 128 iic_tag_init(&sc->sc_ic); 129 sc->sc_ic.ic_cookie = sc; 130 sc->sc_ic.ic_exec = qciic_exec; 131 132 acpi_i2c_register(aa->aa_node, self, &sc->sc_ic); 133 134 iicbus_attach(self, &sc->sc_ic); 135 136 done: 137 acpi_resource_cleanup(&res); 138 } 139 140 static int 141 qciic_wait(struct qciic_softc *sc, uint32_t bits) 142 { 143 uint32_t stat; 144 int timo; 145 146 for (timo = 50000; timo > 0; timo--) { 147 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 148 if (stat & bits) 149 break; 150 delay(10); 151 } 152 if (timo == 0) 153 return ETIMEDOUT; 154 155 return 0; 156 } 157 158 static int 159 qciic_read(struct qciic_softc *sc, uint8_t *buf, size_t len) 160 { 161 uint32_t stat, word; 162 int timo, i; 163 164 word = 0; 165 for (i = 0; i < len; i++) { 166 if ((i % 4) == 0) { 167 for (timo = 50000; timo > 0; timo--) { 168 stat = HREAD4(sc, GENI_RX_FIFO_STATUS); 169 if (GENI_RX_FIFO_STATUS_WC(stat) > 0) 170 break; 171 delay(10); 172 } 173 if (timo == 0) 174 return ETIMEDOUT; 175 word = HREAD4(sc, GENI_RX_FIFO); 176 } 177 buf[i] = word >> ((i % 4) * 8); 178 } 179 180 return 0; 181 } 182 183 static int 184 qciic_write(struct qciic_softc *sc, const uint8_t *buf, size_t len) 185 { 186 uint32_t stat, word; 187 int timo, i; 188 189 word = 0; 190 for (i = 0; i < len; i++) { 191 word |= buf[i] << ((i % 4) * 8); 192 if ((i % 4) == 3 || i == (len - 1)) { 193 for (timo = 50000; timo > 0; timo--) { 194 stat = HREAD4(sc, GENI_TX_FIFO_STATUS); 195 if (stat < 16) 196 break; 197 delay(10); 198 } 199 if (timo == 0) 200 return ETIMEDOUT; 201 HWRITE4(sc, GENI_TX_FIFO, word); 202 word = 0; 203 } 204 } 205 206 return 0; 207 } 208 209 static int 210 qciic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 211 size_t cmdlen, void *buf, size_t buflen, int flags) 212 { 213 struct qciic_softc *sc = cookie; 214 uint32_t m_cmd, m_param, stat; 215 int error; 216 217 m_param = addr << GENI_M_CMD0_SLV_ADDR_SHIFT; 218 m_param |= GENI_M_CMD0_STOP_STRETCH; 219 220 if (buflen == 0 && I2C_OP_STOP_P(op)) 221 m_param &= ~GENI_M_CMD0_STOP_STRETCH; 222 223 if (cmdlen > 0) { 224 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 225 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat); 226 HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen); 227 m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param; 228 HWRITE4(sc, GENI_M_CMD0, m_cmd); 229 230 error = qciic_write(sc, cmd, cmdlen); 231 if (error) 232 return error; 233 234 error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE); 235 if (error) 236 return error; 237 } 238 239 if (buflen == 0) 240 return 0; 241 242 if (I2C_OP_STOP_P(op)) 243 m_param &= ~GENI_M_CMD0_STOP_STRETCH; 244 245 if (I2C_OP_READ_P(op)) { 246 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 247 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat); 248 HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen); 249 m_cmd = GENI_M_CMD0_OPCODE_I2C_READ | m_param; 250 HWRITE4(sc, GENI_M_CMD0, m_cmd); 251 252 error = qciic_read(sc, buf, buflen); 253 if (error) 254 return error; 255 256 error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE); 257 if (error) 258 return error; 259 } else { 260 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 261 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat); 262 HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen); 263 m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param; 264 HWRITE4(sc, GENI_M_CMD0, m_cmd); 265 266 error = qciic_write(sc, buf, buflen); 267 if (error) 268 return error; 269 270 error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE); 271 if (error) 272 return error; 273 } 274 275 return 0; 276 } 277
Indexes created Wed Sep 24 05:09:52 GMT 2025