qcomiic.c revision 1.5
1 /* $NetBSD: qcomiic.c,v 1.5 2025/09/15 15:28:48 thorpej Exp $ */ 2 3 /* $OpenBSD: qciic.c,v 1.7 2024/10/02 21:21:32 kettenis Exp $ */ 4 /* 5 * Copyright (c) 2022 Mark Kettenis <kettenis (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/param.h> 21 #include <sys/bus.h> 22 #include <sys/cpu.h> 23 #include <sys/device.h> 24 25 #include <dev/acpi/acpireg.h> 26 #include <dev/acpi/acpivar.h> 27 #include <dev/acpi/acpi_intr.h> 28 #include <dev/acpi/acpi_i2c.h> 29 30 #include <dev/i2c/i2cvar.h> 31 32 /* Registers */ 33 #define GENI_I2C_TX_TRANS_LEN 0x26c 34 #define GENI_I2C_RX_TRANS_LEN 0x270 35 #define GENI_M_CMD0 0x600 36 #define GENI_M_CMD0_OPCODE_I2C_WRITE (0x1 << 27) 37 #define GENI_M_CMD0_OPCODE_I2C_READ (0x2 << 27) 38 #define GENI_M_CMD0_SLV_ADDR_SHIFT 9 39 #define GENI_M_CMD0_STOP_STRETCH (1 << 2) 40 #define GENI_M_IRQ_STATUS 0x610 41 #define GENI_M_IRQ_CLEAR 0x618 42 #define GENI_M_IRQ_CMD_DONE (1 << 0) 43 #define GENI_TX_FIFO 0x700 44 #define GENI_RX_FIFO 0x780 45 #define GENI_TX_FIFO_STATUS 0x800 46 #define GENI_RX_FIFO_STATUS 0x804 47 #define GENI_RX_FIFO_STATUS_WC(val) ((val) & 0xffffff) 48 49 #define HREAD4(sc, reg) \ 50 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 51 #define HWRITE4(sc, reg, val) \ 52 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 53 54 struct qciic_softc { 55 device_t sc_dev; 56 struct acpi_devnode *sc_acpi; 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 60 device_t sc_iic; 61 62 struct i2c_controller sc_ic; 63 }; 64 65 static int qciic_acpi_match(device_t, cfdata_t, void *); 66 static void qciic_acpi_attach(device_t, device_t, void *); 67 static int qciic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 68 void *, size_t, int); 69 70 CFATTACH_DECL_NEW(qcomiic, sizeof(struct qciic_softc), 71 qciic_acpi_match, qciic_acpi_attach, NULL, NULL); 72 73 static const struct device_compatible_entry compat_data[] = { 74 { .compat = "QCOM0610" }, 75 { .compat = "QCOM0811" }, 76 { .compat = "QCOM0C10" }, 77 DEVICE_COMPAT_EOL 78 }; 79 80 static int 81 qciic_acpi_match(device_t parent, cfdata_t cf, void *aux) 82 { 83 struct acpi_attach_args *aa = aux; 84 85 return acpi_compatible_match(aa, compat_data); 86 } 87 88 static void 89 qciic_acpi_attach(device_t parent, device_t self, void *aux) 90 { 91 struct qciic_softc * const sc = device_private(self); 92 struct acpi_attach_args *aa = aux; 93 struct acpi_resources res; 94 struct acpi_mem *mem; 95 struct acpi_irq *irq; 96 ACPI_STATUS rv; 97 int error; 98 99 sc->sc_dev = self; 100 sc->sc_acpi = aa->aa_node; 101 sc->sc_iot = aa->aa_memt; 102 103 rv = acpi_resource_parse(sc->sc_dev, aa->aa_node->ad_handle, "_CRS", 104 &res, &acpi_resource_parse_ops_default); 105 if (ACPI_FAILURE(rv)) { 106 return; 107 } 108 109 mem = acpi_res_mem(&res, 0); 110 if (mem == NULL) { 111 aprint_error_dev(self, "couldn't find mem resource\n"); 112 goto done; 113 } 114 115 irq = acpi_res_irq(&res, 0); 116 if (irq == NULL) { 117 aprint_error_dev(self, "couldn't find irq resource\n"); 118 goto done; 119 } 120 121 error = bus_space_map(sc->sc_iot, mem->ar_base, mem->ar_length, 0, 122 &sc->sc_ioh); 123 if (error != 0) { 124 aprint_error_dev(self, "couldn't map registers\n"); 125 return; 126 } 127 128 iic_tag_init(&sc->sc_ic); 129 sc->sc_ic.ic_cookie = sc; 130 sc->sc_ic.ic_exec = qciic_exec; 131 132 iicbus_attach(self, &sc->sc_ic); 133 134 done: 135 acpi_resource_cleanup(&res); 136 } 137 138 static int 139 qciic_wait(struct qciic_softc *sc, uint32_t bits) 140 { 141 uint32_t stat; 142 int timo; 143 144 for (timo = 50000; timo > 0; timo--) { 145 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 146 if (stat & bits) 147 break; 148 delay(10); 149 } 150 if (timo == 0) 151 return ETIMEDOUT; 152 153 return 0; 154 } 155 156 static int 157 qciic_read(struct qciic_softc *sc, uint8_t *buf, size_t len) 158 { 159 uint32_t stat, word; 160 int timo, i; 161 162 word = 0; 163 for (i = 0; i < len; i++) { 164 if ((i % 4) == 0) { 165 for (timo = 50000; timo > 0; timo--) { 166 stat = HREAD4(sc, GENI_RX_FIFO_STATUS); 167 if (GENI_RX_FIFO_STATUS_WC(stat) > 0) 168 break; 169 delay(10); 170 } 171 if (timo == 0) 172 return ETIMEDOUT; 173 word = HREAD4(sc, GENI_RX_FIFO); 174 } 175 buf[i] = word >> ((i % 4) * 8); 176 } 177 178 return 0; 179 } 180 181 static int 182 qciic_write(struct qciic_softc *sc, const uint8_t *buf, size_t len) 183 { 184 uint32_t stat, word; 185 int timo, i; 186 187 word = 0; 188 for (i = 0; i < len; i++) { 189 word |= buf[i] << ((i % 4) * 8); 190 if ((i % 4) == 3 || i == (len - 1)) { 191 for (timo = 50000; timo > 0; timo--) { 192 stat = HREAD4(sc, GENI_TX_FIFO_STATUS); 193 if (stat < 16) 194 break; 195 delay(10); 196 } 197 if (timo == 0) 198 return ETIMEDOUT; 199 HWRITE4(sc, GENI_TX_FIFO, word); 200 word = 0; 201 } 202 } 203 204 return 0; 205 } 206 207 static int 208 qciic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 209 size_t cmdlen, void *buf, size_t buflen, int flags) 210 { 211 struct qciic_softc *sc = cookie; 212 uint32_t m_cmd, m_param, stat; 213 int error; 214 215 m_param = addr << GENI_M_CMD0_SLV_ADDR_SHIFT; 216 m_param |= GENI_M_CMD0_STOP_STRETCH; 217 218 if (buflen == 0 && I2C_OP_STOP_P(op)) 219 m_param &= ~GENI_M_CMD0_STOP_STRETCH; 220 221 if (cmdlen > 0) { 222 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 223 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat); 224 HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen); 225 m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param; 226 HWRITE4(sc, GENI_M_CMD0, m_cmd); 227 228 error = qciic_write(sc, cmd, cmdlen); 229 if (error) 230 return error; 231 232 error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE); 233 if (error) 234 return error; 235 } 236 237 if (buflen == 0) 238 return 0; 239 240 if (I2C_OP_STOP_P(op)) 241 m_param &= ~GENI_M_CMD0_STOP_STRETCH; 242 243 if (I2C_OP_READ_P(op)) { 244 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 245 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat); 246 HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen); 247 m_cmd = GENI_M_CMD0_OPCODE_I2C_READ | m_param; 248 HWRITE4(sc, GENI_M_CMD0, m_cmd); 249 250 error = qciic_read(sc, buf, buflen); 251 if (error) 252 return error; 253 254 error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE); 255 if (error) 256 return error; 257 } else { 258 stat = HREAD4(sc, GENI_M_IRQ_STATUS); 259 HWRITE4(sc, GENI_M_IRQ_CLEAR, stat); 260 HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen); 261 m_cmd = GENI_M_CMD0_OPCODE_I2C_WRITE | m_param; 262 HWRITE4(sc, GENI_M_CMD0, m_cmd); 263 264 error = qciic_write(sc, buf, buflen); 265 if (error) 266 return error; 267 268 error = qciic_wait(sc, GENI_M_IRQ_CMD_DONE); 269 if (error) 270 return error; 271 } 272 273 return 0; 274 } 275
Indexes created Tue Oct 07 21:09:53 GMT 2025