ata.c revision 1.114
1 /* $NetBSD: ata.c,v 1.114 2011/04/18 01:47:28 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.114 2011/04/18 01:47:28 rmind Exp $"); 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/fcntl.h> 39 #include <sys/proc.h> 40 #include <sys/pool.h> 41 #include <sys/kthread.h> 42 #include <sys/errno.h> 43 #include <sys/ataio.h> 44 #include <sys/kmem.h> 45 #include <sys/intr.h> 46 #include <sys/bus.h> 47 #include <sys/once.h> 48 49 #include <dev/ata/ataconf.h> 50 #include <dev/ata/atareg.h> 51 #include <dev/ata/atavar.h> 52 #include <dev/ic/wdcvar.h> /* for PIOBM */ 53 54 #include "locators.h" 55 56 #include "atapibus.h" 57 #include "ataraid.h" 58 59 #if NATARAID > 0 60 #include <dev/ata/ata_raidvar.h> 61 #endif 62 63 #define DEBUG_FUNCS 0x08 64 #define DEBUG_PROBE 0x10 65 #define DEBUG_DETACH 0x20 66 #define DEBUG_XFERS 0x40 67 #ifdef ATADEBUG 68 int atadebug_mask = 0; 69 #define ATADEBUG_PRINT(args, level) \ 70 if (atadebug_mask & (level)) \ 71 printf args 72 #else 73 #define ATADEBUG_PRINT(args, level) 74 #endif 75 76 static ONCE_DECL(ata_init_ctrl); 77 static struct pool ata_xfer_pool; 78 79 /* 80 * A queue of atabus instances, used to ensure the same bus probe order 81 * for a given hardware configuration at each boot. Kthread probing 82 * devices on a atabus. Only one probing at once. 83 */ 84 static TAILQ_HEAD(, atabus_initq) atabus_initq_head; 85 static kmutex_t atabus_qlock; 86 static kcondvar_t atabus_qcv; 87 static lwp_t * atabus_cfg_lwp; 88 89 /***************************************************************************** 90 * ATA bus layer. 91 * 92 * ATA controllers attach an atabus instance, which handles probing the bus 93 * for drives, etc. 94 *****************************************************************************/ 95 96 dev_type_open(atabusopen); 97 dev_type_close(atabusclose); 98 dev_type_ioctl(atabusioctl); 99 100 const struct cdevsw atabus_cdevsw = { 101 atabusopen, atabusclose, noread, nowrite, atabusioctl, 102 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 103 }; 104 105 extern struct cfdriver atabus_cd; 106 107 static void atabus_childdetached(device_t, device_t); 108 static bool atabus_resume(device_t, const pmf_qual_t *); 109 static bool atabus_suspend(device_t, const pmf_qual_t *); 110 static void atabusconfig_thread(void *); 111 112 /* 113 * atabus_init: 114 * 115 * Initialize ATA subsystem structures. 116 */ 117 static int 118 atabus_init(void) 119 { 120 121 pool_init(&ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, 122 "ataspl", NULL, IPL_BIO); 123 TAILQ_INIT(&atabus_initq_head); 124 mutex_init(&atabus_qlock, MUTEX_DEFAULT, IPL_NONE); 125 cv_init(&atabus_qcv, "atainitq"); 126 return 0; 127 } 128 129 /* 130 * atabusprint: 131 * 132 * Autoconfiguration print routine used by ATA controllers when 133 * attaching an atabus instance. 134 */ 135 int 136 atabusprint(void *aux, const char *pnp) 137 { 138 struct ata_channel *chan = aux; 139 140 if (pnp) 141 aprint_normal("atabus at %s", pnp); 142 aprint_normal(" channel %d", chan->ch_channel); 143 144 return (UNCONF); 145 } 146 147 /* 148 * ataprint: 149 * 150 * Autoconfiguration print routine. 151 */ 152 int 153 ataprint(void *aux, const char *pnp) 154 { 155 struct ata_device *adev = aux; 156 157 if (pnp) 158 aprint_normal("wd at %s", pnp); 159 aprint_normal(" drive %d", adev->adev_drv_data->drive); 160 161 return (UNCONF); 162 } 163 164 /* 165 * ata_channel_attach: 166 * 167 * Common parts of attaching an atabus to an ATA controller channel. 168 */ 169 void 170 ata_channel_attach(struct ata_channel *chp) 171 { 172 173 if (chp->ch_flags & ATACH_DISABLED) 174 return; 175 176 /* XXX callout_destroy */ 177 callout_init(&chp->ch_callout, 0); 178 179 TAILQ_INIT(&chp->ch_queue->queue_xfer); 180 chp->ch_queue->queue_freeze = 0; 181 chp->ch_queue->queue_flags = 0; 182 chp->ch_queue->active_xfer = NULL; 183 184 chp->atabus = config_found_ia(chp->ch_atac->atac_dev, "ata", chp, 185 atabusprint); 186 } 187 188 static void 189 atabusconfig(struct atabus_softc *atabus_sc) 190 { 191 struct ata_channel *chp = atabus_sc->sc_chan; 192 struct atac_softc *atac = chp->ch_atac; 193 struct atabus_initq *atabus_initq = NULL; 194 int i, s, error; 195 196 /* we are in the atabus's thread context */ 197 s = splbio(); 198 chp->ch_flags |= ATACH_TH_RUN; 199 splx(s); 200 201 /* Probe for the drives. */ 202 /* XXX for SATA devices we will power up all drives at once */ 203 (*atac->atac_probe)(chp); 204 205 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 206 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 207 DEBUG_PROBE); 208 209 /* next operations will occurs in a separate thread */ 210 s = splbio(); 211 chp->ch_flags &= ~ATACH_TH_RUN; 212 splx(s); 213 214 /* Make sure the devices probe in atabus order to avoid jitter. */ 215 mutex_enter(&atabus_qlock); 216 for (;;) { 217 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 218 if (atabus_initq->atabus_sc == atabus_sc) 219 break; 220 cv_wait(&atabus_qcv, &atabus_qlock); 221 } 222 mutex_exit(&atabus_qlock); 223 224 /* If no drives, abort here */ 225 for (i = 0; i < chp->ch_ndrive; i++) 226 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 227 break; 228 if (i == chp->ch_ndrive) 229 goto out; 230 231 /* Shortcut in case we've been shutdown */ 232 if (chp->ch_flags & ATACH_SHUTDOWN) 233 goto out; 234 235 236 if ((error = kthread_create(PRI_NONE, 0, NULL, atabusconfig_thread, 237 atabus_sc, &atabus_cfg_lwp, 238 "%scnf", device_xname(atac->atac_dev))) != 0) 239 aprint_error_dev(atac->atac_dev, 240 "unable to create config thread: error %d\n", error); 241 return; 242 243 out: 244 mutex_enter(&atabus_qlock); 245 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 246 cv_broadcast(&atabus_qcv); 247 mutex_exit(&atabus_qlock); 248 249 free(atabus_initq, M_DEVBUF); 250 251 ata_delref(chp); 252 253 config_pending_decr(); 254 } 255 256 /* 257 * atabus_configthread: finish attach of atabus's childrens, in a separate 258 * kernel thread. 259 */ 260 static void 261 atabusconfig_thread(void *arg) 262 { 263 struct atabus_softc *atabus_sc = arg; 264 struct ata_channel *chp = atabus_sc->sc_chan; 265 struct atac_softc *atac = chp->ch_atac; 266 struct atabus_initq *atabus_initq = NULL; 267 int i, s; 268 269 /* XXX seems wrong */ 270 mutex_enter(&atabus_qlock); 271 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 272 KASSERT(atabus_initq->atabus_sc == atabus_sc); 273 mutex_exit(&atabus_qlock); 274 275 /* 276 * Attach an ATAPI bus, if needed. 277 */ 278 for (i = 0; i < chp->ch_ndrive; i++) { 279 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 280 #if NATAPIBUS > 0 281 (*atac->atac_atapibus_attach)(atabus_sc); 282 #else 283 /* 284 * Fake the autoconfig "not configured" message 285 */ 286 aprint_normal("atapibus at %s not configured\n", 287 device_xname(atac->atac_dev)); 288 chp->atapibus = NULL; 289 s = splbio(); 290 for (i = 0; i < chp->ch_ndrive; i++) 291 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 292 splx(s); 293 #endif 294 break; 295 } 296 } 297 298 for (i = 0; i < chp->ch_ndrive; i++) { 299 struct ata_device adev; 300 if ((chp->ch_drive[i].drive_flags & 301 (DRIVE_ATA | DRIVE_OLD)) == 0) { 302 continue; 303 } 304 memset(&adev, 0, sizeof(struct ata_device)); 305 adev.adev_bustype = atac->atac_bustype_ata; 306 adev.adev_channel = chp->ch_channel; 307 adev.adev_openings = 1; 308 adev.adev_drv_data = &chp->ch_drive[i]; 309 chp->ata_drives[i] = config_found_ia(atabus_sc->sc_dev, 310 "ata_hl", &adev, ataprint); 311 if (chp->ata_drives[i] != NULL) 312 ata_probe_caps(&chp->ch_drive[i]); 313 else { 314 s = splbio(); 315 chp->ch_drive[i].drive_flags &= 316 ~(DRIVE_ATA | DRIVE_OLD); 317 splx(s); 318 } 319 } 320 321 /* now that we know the drives, the controller can set its modes */ 322 if (atac->atac_set_modes) { 323 (*atac->atac_set_modes)(chp); 324 ata_print_modes(chp); 325 } 326 #if NATARAID > 0 327 if (atac->atac_cap & ATAC_CAP_RAID) 328 for (i = 0; i < chp->ch_ndrive; i++) 329 if (chp->ata_drives[i] != NULL) 330 ata_raid_check_component(chp->ata_drives[i]); 331 #endif /* NATARAID > 0 */ 332 333 /* 334 * reset drive_flags for unattached devices, reset state for attached 335 * ones 336 */ 337 s = splbio(); 338 for (i = 0; i < chp->ch_ndrive; i++) { 339 if (chp->ch_drive[i].drv_softc == NULL) 340 chp->ch_drive[i].drive_flags = 0; 341 else 342 chp->ch_drive[i].state = 0; 343 } 344 splx(s); 345 346 mutex_enter(&atabus_qlock); 347 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 348 cv_broadcast(&atabus_qcv); 349 mutex_exit(&atabus_qlock); 350 351 free(atabus_initq, M_DEVBUF); 352 353 ata_delref(chp); 354 355 config_pending_decr(); 356 kthread_exit(0); 357 } 358 359 /* 360 * atabus_thread: 361 * 362 * Worker thread for the ATA bus. 363 */ 364 static void 365 atabus_thread(void *arg) 366 { 367 struct atabus_softc *sc = arg; 368 struct ata_channel *chp = sc->sc_chan; 369 struct ata_xfer *xfer; 370 int i, s; 371 372 s = splbio(); 373 chp->ch_flags |= ATACH_TH_RUN; 374 375 /* 376 * Probe the drives. Reset all flags to 0 to indicate to controllers 377 * that can re-probe that all drives must be probed.. 378 * 379 * Note: ch_ndrive may be changed during the probe. 380 */ 381 for (i = 0; i < ATA_MAXDRIVES; i++) 382 chp->ch_drive[i].drive_flags = 0; 383 splx(s); 384 385 atabusconfig(sc); 386 387 s = splbio(); 388 for (;;) { 389 if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 && 390 (chp->ch_queue->active_xfer == NULL || 391 chp->ch_queue->queue_freeze == 0)) { 392 chp->ch_flags &= ~ATACH_TH_RUN; 393 (void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0); 394 chp->ch_flags |= ATACH_TH_RUN; 395 } 396 if (chp->ch_flags & ATACH_SHUTDOWN) { 397 break; 398 } 399 if (chp->ch_flags & ATACH_TH_RESET) { 400 /* 401 * ata_reset_channel() will freeze 2 times, so 402 * unfreeze one time. Not a problem as we're at splbio 403 */ 404 chp->ch_queue->queue_freeze--; 405 ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags); 406 } else if (chp->ch_queue->active_xfer != NULL && 407 chp->ch_queue->queue_freeze == 1) { 408 /* 409 * Caller has bumped queue_freeze, decrease it. 410 */ 411 chp->ch_queue->queue_freeze--; 412 xfer = chp->ch_queue->active_xfer; 413 KASSERT(xfer != NULL); 414 (*xfer->c_start)(xfer->c_chp, xfer); 415 } else if (chp->ch_queue->queue_freeze > 1) 416 panic("ata_thread: queue_freeze"); 417 } 418 splx(s); 419 chp->ch_thread = NULL; 420 wakeup(&chp->ch_flags); 421 kthread_exit(0); 422 } 423 424 /* 425 * atabus_match: 426 * 427 * Autoconfiguration match routine. 428 */ 429 static int 430 atabus_match(device_t parent, cfdata_t cf, void *aux) 431 { 432 struct ata_channel *chp = aux; 433 434 if (chp == NULL) 435 return (0); 436 437 if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel && 438 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 439 return (0); 440 441 return (1); 442 } 443 444 /* 445 * atabus_attach: 446 * 447 * Autoconfiguration attach routine. 448 */ 449 static void 450 atabus_attach(device_t parent, device_t self, void *aux) 451 { 452 struct atabus_softc *sc = device_private(self); 453 struct ata_channel *chp = aux; 454 struct atabus_initq *initq; 455 int error; 456 457 sc->sc_chan = chp; 458 459 aprint_normal("\n"); 460 aprint_naive("\n"); 461 462 sc->sc_dev = self; 463 464 if (ata_addref(chp)) 465 return; 466 467 RUN_ONCE(&ata_init_ctrl, atabus_init); 468 469 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 470 initq->atabus_sc = sc; 471 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 472 config_pending_incr(); 473 474 if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc, 475 &chp->ch_thread, "%s", device_xname(self))) != 0) 476 aprint_error_dev(self, 477 "unable to create kernel thread: error %d\n", error); 478 479 if (!pmf_device_register(self, atabus_suspend, atabus_resume)) 480 aprint_error_dev(self, "couldn't establish power handler\n"); 481 } 482 483 /* 484 * atabus_detach: 485 * 486 * Autoconfiguration detach routine. 487 */ 488 static int 489 atabus_detach(device_t self, int flags) 490 { 491 struct atabus_softc *sc = device_private(self); 492 struct ata_channel *chp = sc->sc_chan; 493 device_t dev = NULL; 494 int s, i, error = 0; 495 496 /* Shutdown the channel. */ 497 s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */ 498 chp->ch_flags |= ATACH_SHUTDOWN; 499 splx(s); 500 501 wakeup(&chp->ch_thread); 502 503 while (chp->ch_thread != NULL) 504 (void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 505 506 507 /* 508 * Detach atapibus and its children. 509 */ 510 if ((dev = chp->atapibus) != NULL) { 511 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 512 device_xname(self), device_xname(dev)), DEBUG_DETACH); 513 514 error = config_detach(dev, flags); 515 if (error) 516 goto out; 517 KASSERT(chp->atapibus == NULL); 518 } 519 520 /* 521 * Detach our other children. 522 */ 523 for (i = 0; i < chp->ch_ndrive; i++) { 524 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 525 continue; 526 if ((dev = chp->ata_drives[i]) != NULL) { 527 ATADEBUG_PRINT(("%s.%d: %s: detaching %s\n", __func__, 528 __LINE__, device_xname(self), device_xname(dev)), 529 DEBUG_DETACH); 530 KASSERT(chp->ch_drive[i].drv_softc == 531 chp->ata_drives[i]); 532 error = config_detach(dev, flags); 533 if (error) 534 goto out; 535 KASSERT(chp->ata_drives[i] == NULL); 536 } 537 } 538 539 out: 540 #ifdef ATADEBUG 541 if (dev != NULL && error != 0) 542 ATADEBUG_PRINT(("%s: %s: error %d detaching %s\n", __func__, 543 device_xname(self), error, device_xname(dev)), 544 DEBUG_DETACH); 545 #endif /* ATADEBUG */ 546 547 return (error); 548 } 549 550 void 551 atabus_childdetached(device_t self, device_t child) 552 { 553 bool found = false; 554 struct atabus_softc *sc = device_private(self); 555 struct ata_channel *chp = sc->sc_chan; 556 int i; 557 558 /* 559 * atapibus detached. 560 */ 561 if (child == chp->atapibus) { 562 chp->atapibus = NULL; 563 found = true; 564 } 565 566 /* 567 * Detach our other children. 568 */ 569 for (i = 0; i < chp->ch_ndrive; i++) { 570 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 571 continue; 572 if (child == chp->ata_drives[i]) { 573 KASSERT(chp->ata_drives[i] == 574 chp->ch_drive[i].drv_softc); 575 chp->ata_drives[i] = NULL; 576 chp->ch_drive[i].drv_softc = NULL; 577 chp->ch_drive[i].drive_flags = 0; 578 found = true; 579 } 580 } 581 582 if (!found) 583 panic("%s: unknown child %p", device_xname(self), 584 (const void *)child); 585 } 586 587 CFATTACH_DECL3_NEW(atabus, sizeof(struct atabus_softc), 588 atabus_match, atabus_attach, atabus_detach, NULL, NULL, 589 atabus_childdetached, DVF_DETACH_SHUTDOWN); 590 591 /***************************************************************************** 592 * Common ATA bus operations. 593 *****************************************************************************/ 594 595 /* Get the disk's parameters */ 596 int 597 ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags, 598 struct ataparams *prms) 599 { 600 struct ata_command ata_c; 601 struct ata_channel *chp = drvp->chnl_softc; 602 struct atac_softc *atac = chp->ch_atac; 603 char *tb; 604 int i, rv; 605 u_int16_t *p; 606 607 ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS); 608 609 tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP); 610 memset(prms, 0, sizeof(struct ataparams)); 611 memset(&ata_c, 0, sizeof(struct ata_command)); 612 613 if (drvp->drive_flags & DRIVE_ATA) { 614 ata_c.r_command = WDCC_IDENTIFY; 615 ata_c.r_st_bmask = WDCS_DRDY; 616 ata_c.r_st_pmask = WDCS_DRQ; 617 ata_c.timeout = 3000; /* 3s */ 618 } else if (drvp->drive_flags & DRIVE_ATAPI) { 619 ata_c.r_command = ATAPI_IDENTIFY_DEVICE; 620 ata_c.r_st_bmask = 0; 621 ata_c.r_st_pmask = WDCS_DRQ; 622 ata_c.timeout = 10000; /* 10s */ 623 } else { 624 ATADEBUG_PRINT(("ata_get_parms: no disks\n"), 625 DEBUG_FUNCS|DEBUG_PROBE); 626 rv = CMD_ERR; 627 goto out; 628 } 629 ata_c.flags = AT_READ | flags; 630 ata_c.data = tb; 631 ata_c.bcount = DEV_BSIZE; 632 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 633 &ata_c) != ATACMD_COMPLETE) { 634 ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"), 635 DEBUG_FUNCS|DEBUG_PROBE); 636 rv = CMD_AGAIN; 637 goto out; 638 } 639 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 640 ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n", 641 ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE); 642 rv = CMD_ERR; 643 goto out; 644 } 645 /* if we didn't read any data something is wrong */ 646 if ((ata_c.flags & AT_XFDONE) == 0) { 647 rv = CMD_ERR; 648 goto out; 649 } 650 651 /* Read in parameter block. */ 652 memcpy(prms, tb, sizeof(struct ataparams)); 653 654 /* 655 * Shuffle string byte order. 656 * ATAPI NEC, Mitsumi and Pioneer drives and 657 * old ATA TDK CompactFlash cards 658 * have different byte order. 659 */ 660 #if BYTE_ORDER == BIG_ENDIAN 661 # define M(n) prms->atap_model[(n) ^ 1] 662 #else 663 # define M(n) prms->atap_model[n] 664 #endif 665 if ( 666 #if BYTE_ORDER == BIG_ENDIAN 667 ! 668 #endif 669 ((drvp->drive_flags & DRIVE_ATAPI) ? 670 ((M(0) == 'N' && M(1) == 'E') || 671 (M(0) == 'F' && M(1) == 'X') || 672 (M(0) == 'P' && M(1) == 'i')) : 673 ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) { 674 rv = CMD_OK; 675 goto out; 676 } 677 #undef M 678 for (i = 0; i < sizeof(prms->atap_model); i += 2) { 679 p = (u_int16_t *)(prms->atap_model + i); 680 *p = bswap16(*p); 681 } 682 for (i = 0; i < sizeof(prms->atap_serial); i += 2) { 683 p = (u_int16_t *)(prms->atap_serial + i); 684 *p = bswap16(*p); 685 } 686 for (i = 0; i < sizeof(prms->atap_revision); i += 2) { 687 p = (u_int16_t *)(prms->atap_revision + i); 688 *p = bswap16(*p); 689 } 690 691 rv = CMD_OK; 692 out: 693 kmem_free(tb, DEV_BSIZE); 694 return rv; 695 } 696 697 int 698 ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags) 699 { 700 struct ata_command ata_c; 701 struct ata_channel *chp = drvp->chnl_softc; 702 struct atac_softc *atac = chp->ch_atac; 703 704 ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS); 705 memset(&ata_c, 0, sizeof(struct ata_command)); 706 707 ata_c.r_command = SET_FEATURES; 708 ata_c.r_st_bmask = 0; 709 ata_c.r_st_pmask = 0; 710 ata_c.r_features = WDSF_SET_MODE; 711 ata_c.r_count = mode; 712 ata_c.flags = flags; 713 ata_c.timeout = 1000; /* 1s */ 714 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 715 &ata_c) != ATACMD_COMPLETE) 716 return CMD_AGAIN; 717 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 718 return CMD_ERR; 719 } 720 return CMD_OK; 721 } 722 723 #if NATA_DMA 724 void 725 ata_dmaerr(struct ata_drive_datas *drvp, int flags) 726 { 727 /* 728 * Downgrade decision: if we get NERRS_MAX in NXFER. 729 * We start with n_dmaerrs set to NERRS_MAX-1 so that the 730 * first error within the first NXFER ops will immediatly trigger 731 * a downgrade. 732 * If we got an error and n_xfers is bigger than NXFER reset counters. 733 */ 734 drvp->n_dmaerrs++; 735 if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) { 736 ata_downgrade_mode(drvp, flags); 737 drvp->n_dmaerrs = NERRS_MAX-1; 738 drvp->n_xfers = 0; 739 return; 740 } 741 if (drvp->n_xfers > NXFER) { 742 drvp->n_dmaerrs = 1; /* just got an error */ 743 drvp->n_xfers = 1; /* restart counting from this error */ 744 } 745 } 746 #endif /* NATA_DMA */ 747 748 /* 749 * freeze the queue and wait for the controller to be idle. Caller has to 750 * unfreeze/restart the queue 751 */ 752 void 753 ata_queue_idle(struct ata_queue *queue) 754 { 755 int s = splbio(); 756 queue->queue_freeze++; 757 while (queue->active_xfer != NULL) { 758 queue->queue_flags |= QF_IDLE_WAIT; 759 tsleep(&queue->queue_flags, PRIBIO, "qidl", 0); 760 } 761 splx(s); 762 } 763 764 /* 765 * Add a command to the queue and start controller. 766 * 767 * MUST BE CALLED AT splbio()! 768 */ 769 void 770 ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 771 { 772 773 ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer, 774 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 775 776 /* complete xfer setup */ 777 xfer->c_chp = chp; 778 779 /* insert at the end of command list */ 780 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 781 ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n", 782 chp->ch_flags), DEBUG_XFERS); 783 /* 784 * if polling and can sleep, wait for the xfer to be at head of queue 785 */ 786 if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) { 787 while (chp->ch_queue->active_xfer != NULL || 788 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) { 789 xfer->c_flags |= C_WAITACT; 790 tsleep(xfer, PRIBIO, "ataact", 0); 791 xfer->c_flags &= ~C_WAITACT; 792 if (xfer->c_flags & C_FREE) { 793 ata_free_xfer(chp, xfer); 794 return; 795 } 796 } 797 } 798 atastart(chp); 799 } 800 801 /* 802 * Start I/O on a controller, for the given channel. 803 * The first xfer may be not for our channel if the channel queues 804 * are shared. 805 * 806 * MUST BE CALLED AT splbio()! 807 */ 808 void 809 atastart(struct ata_channel *chp) 810 { 811 struct atac_softc *atac = chp->ch_atac; 812 struct ata_xfer *xfer; 813 814 #ifdef ATA_DEBUG 815 int spl1, spl2; 816 817 spl1 = splbio(); 818 spl2 = splbio(); 819 if (spl2 != spl1) { 820 printf("atastart: not at splbio()\n"); 821 panic("atastart"); 822 } 823 splx(spl2); 824 splx(spl1); 825 #endif /* ATA_DEBUG */ 826 827 /* is there a xfer ? */ 828 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 829 return; 830 831 /* adjust chp, in case we have a shared queue */ 832 chp = xfer->c_chp; 833 834 if (chp->ch_queue->active_xfer != NULL) { 835 return; /* channel aleady active */ 836 } 837 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 838 if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) { 839 chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT; 840 wakeup(&chp->ch_queue->queue_flags); 841 } 842 return; /* queue frozen */ 843 } 844 /* 845 * if someone is waiting for the command to be active, wake it up 846 * and let it process the command 847 */ 848 if (xfer->c_flags & C_WAITACT) { 849 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d " 850 "wait active\n", xfer, chp->ch_channel, xfer->c_drive), 851 DEBUG_XFERS); 852 wakeup(xfer); 853 return; 854 } 855 #ifdef DIAGNOSTIC 856 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) 857 panic("atastart: channel waiting for irq"); 858 #endif 859 if (atac->atac_claim_hw) 860 if (!(*atac->atac_claim_hw)(chp, 0)) 861 return; 862 863 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer, 864 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 865 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 866 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 867 chp->ch_drive[xfer->c_drive].state = 0; 868 } 869 chp->ch_queue->active_xfer = xfer; 870 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 871 872 if (atac->atac_cap & ATAC_CAP_NOIRQ) 873 KASSERT(xfer->c_flags & C_POLL); 874 875 xfer->c_start(chp, xfer); 876 } 877 878 struct ata_xfer * 879 ata_get_xfer(int flags) 880 { 881 struct ata_xfer *xfer; 882 int s; 883 884 s = splbio(); 885 xfer = pool_get(&ata_xfer_pool, 886 ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 887 splx(s); 888 if (xfer != NULL) { 889 memset(xfer, 0, sizeof(struct ata_xfer)); 890 } 891 return xfer; 892 } 893 894 void 895 ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 896 { 897 struct atac_softc *atac = chp->ch_atac; 898 int s; 899 900 if (xfer->c_flags & C_WAITACT) { 901 /* Someone is waiting for this xfer, so we can't free now */ 902 xfer->c_flags |= C_FREE; 903 wakeup(xfer); 904 return; 905 } 906 907 #if NATA_PIOBM /* XXX wdc dependent code */ 908 if (xfer->c_flags & C_PIOBM) { 909 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 910 911 /* finish the busmastering PIO */ 912 (*wdc->piobm_done)(wdc->dma_arg, 913 chp->ch_channel, xfer->c_drive); 914 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT); 915 } 916 #endif 917 918 if (atac->atac_free_hw) 919 (*atac->atac_free_hw)(chp); 920 s = splbio(); 921 pool_put(&ata_xfer_pool, xfer); 922 splx(s); 923 } 924 925 /* 926 * Kill off all pending xfers for a ata_channel. 927 * 928 * Must be called at splbio(). 929 */ 930 void 931 ata_kill_pending(struct ata_drive_datas *drvp) 932 { 933 struct ata_channel *chp = drvp->chnl_softc; 934 struct ata_xfer *xfer, *next_xfer; 935 int s = splbio(); 936 937 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 938 xfer != NULL; xfer = next_xfer) { 939 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 940 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 941 continue; 942 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 943 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 944 } 945 946 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 947 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 948 drvp->drive_flags |= DRIVE_WAITDRAIN; 949 (void) tsleep(&chp->ch_queue->active_xfer, 950 PRIBIO, "atdrn", 0); 951 } else { 952 /* no more xfer for us */ 953 break; 954 } 955 } 956 splx(s); 957 } 958 959 /* 960 * ata_reset_channel: 961 * 962 * Reset and ATA channel. 963 * 964 * MUST BE CALLED AT splbio()! 965 */ 966 void 967 ata_reset_channel(struct ata_channel *chp, int flags) 968 { 969 struct atac_softc *atac = chp->ch_atac; 970 int drive; 971 972 #ifdef ATA_DEBUG 973 int spl1, spl2; 974 975 spl1 = splbio(); 976 spl2 = splbio(); 977 if (spl2 != spl1) { 978 printf("ata_reset_channel: not at splbio()\n"); 979 panic("ata_reset_channel"); 980 } 981 splx(spl2); 982 splx(spl1); 983 #endif /* ATA_DEBUG */ 984 985 chp->ch_queue->queue_freeze++; 986 987 /* 988 * If we can poll or wait it's OK, otherwise wake up the 989 * kernel thread to do it for us. 990 */ 991 ATADEBUG_PRINT(("ata_reset_channel flags 0x%x ch_flags 0x%x\n", 992 flags, chp->ch_flags), DEBUG_FUNCS | DEBUG_XFERS); 993 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 994 if (chp->ch_flags & ATACH_TH_RESET) { 995 /* No need to schedule a reset more than one time. */ 996 chp->ch_queue->queue_freeze--; 997 return; 998 } 999 chp->ch_flags |= ATACH_TH_RESET; 1000 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 1001 wakeup(&chp->ch_thread); 1002 return; 1003 } 1004 1005 (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags); 1006 1007 for (drive = 0; drive < chp->ch_ndrive; drive++) 1008 chp->ch_drive[drive].state = 0; 1009 1010 chp->ch_flags &= ~ATACH_TH_RESET; 1011 if ((flags & AT_RST_EMERG) == 0) { 1012 chp->ch_queue->queue_freeze--; 1013 atastart(chp); 1014 } else { 1015 /* make sure that we can use polled commands */ 1016 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1017 chp->ch_queue->queue_freeze = 0; 1018 chp->ch_queue->active_xfer = NULL; 1019 } 1020 } 1021 1022 int 1023 ata_addref(struct ata_channel *chp) 1024 { 1025 struct atac_softc *atac = chp->ch_atac; 1026 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1027 int s, error = 0; 1028 1029 s = splbio(); 1030 if (adapt->adapt_refcnt++ == 0 && 1031 adapt->adapt_enable != NULL) { 1032 error = (*adapt->adapt_enable)(atac->atac_dev, 1); 1033 if (error) 1034 adapt->adapt_refcnt--; 1035 } 1036 splx(s); 1037 return (error); 1038 } 1039 1040 void 1041 ata_delref(struct ata_channel *chp) 1042 { 1043 struct atac_softc *atac = chp->ch_atac; 1044 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1045 int s; 1046 1047 s = splbio(); 1048 if (adapt->adapt_refcnt-- == 1 && 1049 adapt->adapt_enable != NULL) 1050 (void) (*adapt->adapt_enable)(atac->atac_dev, 0); 1051 splx(s); 1052 } 1053 1054 void 1055 ata_print_modes(struct ata_channel *chp) 1056 { 1057 struct atac_softc *atac = chp->ch_atac; 1058 int drive; 1059 struct ata_drive_datas *drvp; 1060 1061 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1062 drvp = &chp->ch_drive[drive]; 1063 if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL) 1064 continue; 1065 aprint_verbose("%s(%s:%d:%d): using PIO mode %d", 1066 device_xname(drvp->drv_softc), 1067 device_xname(atac->atac_dev), 1068 chp->ch_channel, drvp->drive, drvp->PIO_mode); 1069 #if NATA_DMA 1070 if (drvp->drive_flags & DRIVE_DMA) 1071 aprint_verbose(", DMA mode %d", drvp->DMA_mode); 1072 #if NATA_UDMA 1073 if (drvp->drive_flags & DRIVE_UDMA) { 1074 aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode); 1075 if (drvp->UDMA_mode == 2) 1076 aprint_verbose(" (Ultra/33)"); 1077 else if (drvp->UDMA_mode == 4) 1078 aprint_verbose(" (Ultra/66)"); 1079 else if (drvp->UDMA_mode == 5) 1080 aprint_verbose(" (Ultra/100)"); 1081 else if (drvp->UDMA_mode == 6) 1082 aprint_verbose(" (Ultra/133)"); 1083 } 1084 #endif /* NATA_UDMA */ 1085 #endif /* NATA_DMA */ 1086 #if NATA_DMA || NATA_PIOBM 1087 if (0 1088 #if NATA_DMA 1089 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1090 #endif 1091 #if NATA_PIOBM 1092 /* PIOBM capable controllers use DMA for PIO commands */ 1093 || (atac->atac_cap & ATAC_CAP_PIOBM) 1094 #endif 1095 ) 1096 aprint_verbose(" (using DMA)"); 1097 #endif /* NATA_DMA || NATA_PIOBM */ 1098 aprint_verbose("\n"); 1099 } 1100 } 1101 1102 #if NATA_DMA 1103 /* 1104 * downgrade the transfer mode of a drive after an error. return 1 if 1105 * downgrade was possible, 0 otherwise. 1106 * 1107 * MUST BE CALLED AT splbio()! 1108 */ 1109 int 1110 ata_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1111 { 1112 struct ata_channel *chp = drvp->chnl_softc; 1113 struct atac_softc *atac = chp->ch_atac; 1114 device_t drv_dev = drvp->drv_softc; 1115 int cf_flags = device_cfdata(drv_dev)->cf_flags; 1116 1117 /* if drive or controller don't know its mode, we can't do much */ 1118 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1119 (atac->atac_set_modes == NULL)) 1120 return 0; 1121 /* current drive mode was set by a config flag, let it this way */ 1122 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1123 (cf_flags & ATA_CONFIG_DMA_SET) || 1124 (cf_flags & ATA_CONFIG_UDMA_SET)) 1125 return 0; 1126 1127 #if NATA_UDMA 1128 /* 1129 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1130 */ 1131 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1132 drvp->UDMA_mode--; 1133 aprint_error_dev(drv_dev, 1134 "transfer error, downgrading to Ultra-DMA mode %d\n", 1135 drvp->UDMA_mode); 1136 } 1137 #endif 1138 1139 /* 1140 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1141 */ 1142 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1143 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1144 drvp->PIO_mode = drvp->PIO_cap; 1145 aprint_error_dev(drv_dev, 1146 "transfer error, downgrading to PIO mode %d\n", 1147 drvp->PIO_mode); 1148 } else /* already using PIO, can't downgrade */ 1149 return 0; 1150 1151 (*atac->atac_set_modes)(chp); 1152 ata_print_modes(chp); 1153 /* reset the channel, which will schedule all drives for setup */ 1154 ata_reset_channel(chp, flags | AT_RST_NOCMD); 1155 return 1; 1156 } 1157 #endif /* NATA_DMA */ 1158 1159 /* 1160 * Probe drive's capabilities, for use by the controller later 1161 * Assumes drvp points to an existing drive. 1162 */ 1163 void 1164 ata_probe_caps(struct ata_drive_datas *drvp) 1165 { 1166 struct ataparams params, params2; 1167 struct ata_channel *chp = drvp->chnl_softc; 1168 struct atac_softc *atac = chp->ch_atac; 1169 device_t drv_dev = drvp->drv_softc; 1170 int i, printed, s; 1171 const char *sep = ""; 1172 int cf_flags; 1173 1174 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1175 /* IDENTIFY failed. Can't tell more about the device */ 1176 return; 1177 } 1178 if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == 1179 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 1180 /* 1181 * Controller claims 16 and 32 bit transfers. 1182 * Re-do an IDENTIFY with 32-bit transfers, 1183 * and compare results. 1184 */ 1185 s = splbio(); 1186 drvp->drive_flags |= DRIVE_CAP32; 1187 splx(s); 1188 ata_get_params(drvp, AT_WAIT, ¶ms2); 1189 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1190 /* Not good. fall back to 16bits */ 1191 s = splbio(); 1192 drvp->drive_flags &= ~DRIVE_CAP32; 1193 splx(s); 1194 } else { 1195 aprint_verbose_dev(drv_dev, "32-bit data port\n"); 1196 } 1197 } 1198 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1199 if (params.atap_ata_major > 0x01 && 1200 params.atap_ata_major != 0xffff) { 1201 for (i = 14; i > 0; i--) { 1202 if (params.atap_ata_major & (1 << i)) { 1203 aprint_verbose_dev(drv_dev, 1204 "ATA version %d\n", i); 1205 drvp->ata_vers = i; 1206 break; 1207 } 1208 } 1209 } 1210 #endif 1211 1212 /* An ATAPI device is at last PIO mode 3 */ 1213 if (drvp->drive_flags & DRIVE_ATAPI) 1214 drvp->PIO_mode = 3; 1215 1216 /* 1217 * It's not in the specs, but it seems that some drive 1218 * returns 0xffff in atap_extensions when this field is invalid 1219 */ 1220 if (params.atap_extensions != 0xffff && 1221 (params.atap_extensions & WDC_EXT_MODES)) { 1222 printed = 0; 1223 /* 1224 * XXX some drives report something wrong here (they claim to 1225 * support PIO mode 8 !). As mode is coded on 3 bits in 1226 * SET FEATURE, limit it to 7 (so limit i to 4). 1227 * If higher mode than 7 is found, abort. 1228 */ 1229 for (i = 7; i >= 0; i--) { 1230 if ((params.atap_piomode_supp & (1 << i)) == 0) 1231 continue; 1232 if (i > 4) 1233 return; 1234 /* 1235 * See if mode is accepted. 1236 * If the controller can't set its PIO mode, 1237 * assume the defaults are good, so don't try 1238 * to set it 1239 */ 1240 if (atac->atac_set_modes) 1241 /* 1242 * It's OK to pool here, it's fast enough 1243 * to not bother waiting for interrupt 1244 */ 1245 if (ata_set_mode(drvp, 0x08 | (i + 3), 1246 AT_WAIT) != CMD_OK) 1247 continue; 1248 if (!printed) { 1249 aprint_verbose_dev(drv_dev, 1250 "drive supports PIO mode %d", i + 3); 1251 sep = ","; 1252 printed = 1; 1253 } 1254 /* 1255 * If controller's driver can't set its PIO mode, 1256 * get the highter one for the drive. 1257 */ 1258 if (atac->atac_set_modes == NULL || 1259 atac->atac_pio_cap >= i + 3) { 1260 drvp->PIO_mode = i + 3; 1261 drvp->PIO_cap = i + 3; 1262 break; 1263 } 1264 } 1265 if (!printed) { 1266 /* 1267 * We didn't find a valid PIO mode. 1268 * Assume the values returned for DMA are buggy too 1269 */ 1270 return; 1271 } 1272 s = splbio(); 1273 drvp->drive_flags |= DRIVE_MODE; 1274 splx(s); 1275 printed = 0; 1276 for (i = 7; i >= 0; i--) { 1277 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1278 continue; 1279 #if NATA_DMA 1280 if ((atac->atac_cap & ATAC_CAP_DMA) && 1281 atac->atac_set_modes != NULL) 1282 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1283 != CMD_OK) 1284 continue; 1285 #endif 1286 if (!printed) { 1287 aprint_verbose("%s DMA mode %d", sep, i); 1288 sep = ","; 1289 printed = 1; 1290 } 1291 #if NATA_DMA 1292 if (atac->atac_cap & ATAC_CAP_DMA) { 1293 if (atac->atac_set_modes != NULL && 1294 atac->atac_dma_cap < i) 1295 continue; 1296 drvp->DMA_mode = i; 1297 drvp->DMA_cap = i; 1298 s = splbio(); 1299 drvp->drive_flags |= DRIVE_DMA; 1300 splx(s); 1301 } 1302 #endif 1303 break; 1304 } 1305 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1306 printed = 0; 1307 for (i = 7; i >= 0; i--) { 1308 if ((params.atap_udmamode_supp & (1 << i)) 1309 == 0) 1310 continue; 1311 #if NATA_UDMA 1312 if (atac->atac_set_modes != NULL && 1313 (atac->atac_cap & ATAC_CAP_UDMA)) 1314 if (ata_set_mode(drvp, 0x40 | i, 1315 AT_WAIT) != CMD_OK) 1316 continue; 1317 #endif 1318 if (!printed) { 1319 aprint_verbose("%s Ultra-DMA mode %d", 1320 sep, i); 1321 if (i == 2) 1322 aprint_verbose(" (Ultra/33)"); 1323 else if (i == 4) 1324 aprint_verbose(" (Ultra/66)"); 1325 else if (i == 5) 1326 aprint_verbose(" (Ultra/100)"); 1327 else if (i == 6) 1328 aprint_verbose(" (Ultra/133)"); 1329 sep = ","; 1330 printed = 1; 1331 } 1332 #if NATA_UDMA 1333 if (atac->atac_cap & ATAC_CAP_UDMA) { 1334 if (atac->atac_set_modes != NULL && 1335 atac->atac_udma_cap < i) 1336 continue; 1337 drvp->UDMA_mode = i; 1338 drvp->UDMA_cap = i; 1339 s = splbio(); 1340 drvp->drive_flags |= DRIVE_UDMA; 1341 splx(s); 1342 } 1343 #endif 1344 break; 1345 } 1346 } 1347 aprint_verbose("\n"); 1348 } 1349 1350 s = splbio(); 1351 drvp->drive_flags &= ~DRIVE_NOSTREAM; 1352 if (drvp->drive_flags & DRIVE_ATAPI) { 1353 if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM) 1354 drvp->drive_flags |= DRIVE_NOSTREAM; 1355 } else { 1356 if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM) 1357 drvp->drive_flags |= DRIVE_NOSTREAM; 1358 } 1359 splx(s); 1360 1361 /* Try to guess ATA version here, if it didn't get reported */ 1362 if (drvp->ata_vers == 0) { 1363 #if NATA_UDMA 1364 if (drvp->drive_flags & DRIVE_UDMA) 1365 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1366 else 1367 #endif 1368 if (drvp->PIO_cap > 2) 1369 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1370 } 1371 cf_flags = device_cfdata(drv_dev)->cf_flags; 1372 if (cf_flags & ATA_CONFIG_PIO_SET) { 1373 s = splbio(); 1374 drvp->PIO_mode = 1375 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1376 drvp->drive_flags |= DRIVE_MODE; 1377 splx(s); 1378 } 1379 #if NATA_DMA 1380 if ((atac->atac_cap & ATAC_CAP_DMA) == 0) { 1381 /* don't care about DMA modes */ 1382 return; 1383 } 1384 if (cf_flags & ATA_CONFIG_DMA_SET) { 1385 s = splbio(); 1386 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1387 ATA_CONFIG_DMA_DISABLE) { 1388 drvp->drive_flags &= ~DRIVE_DMA; 1389 } else { 1390 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1391 ATA_CONFIG_DMA_OFF; 1392 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1393 } 1394 splx(s); 1395 } 1396 #if NATA_UDMA 1397 if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) { 1398 /* don't care about UDMA modes */ 1399 return; 1400 } 1401 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1402 s = splbio(); 1403 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1404 ATA_CONFIG_UDMA_DISABLE) { 1405 drvp->drive_flags &= ~DRIVE_UDMA; 1406 } else { 1407 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1408 ATA_CONFIG_UDMA_OFF; 1409 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1410 } 1411 splx(s); 1412 } 1413 #endif /* NATA_UDMA */ 1414 #endif /* NATA_DMA */ 1415 } 1416 1417 /* management of the /dev/atabus* devices */ 1418 int 1419 atabusopen(dev_t dev, int flag, int fmt, struct lwp *l) 1420 { 1421 struct atabus_softc *sc; 1422 int error; 1423 1424 sc = device_lookup_private(&atabus_cd, minor(dev)); 1425 if (sc == NULL) 1426 return (ENXIO); 1427 1428 if (sc->sc_flags & ATABUSCF_OPEN) 1429 return (EBUSY); 1430 1431 if ((error = ata_addref(sc->sc_chan)) != 0) 1432 return (error); 1433 1434 sc->sc_flags |= ATABUSCF_OPEN; 1435 1436 return (0); 1437 } 1438 1439 1440 int 1441 atabusclose(dev_t dev, int flag, int fmt, struct lwp *l) 1442 { 1443 struct atabus_softc *sc = 1444 device_lookup_private(&atabus_cd, minor(dev)); 1445 1446 ata_delref(sc->sc_chan); 1447 1448 sc->sc_flags &= ~ATABUSCF_OPEN; 1449 1450 return (0); 1451 } 1452 1453 int 1454 atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, struct lwp *l) 1455 { 1456 struct atabus_softc *sc = 1457 device_lookup_private(&atabus_cd, minor(dev)); 1458 struct ata_channel *chp = sc->sc_chan; 1459 int min_drive, max_drive, drive; 1460 int error; 1461 int s; 1462 1463 /* 1464 * Enforce write permission for ioctls that change the 1465 * state of the bus. Host adapter specific ioctls must 1466 * be checked by the adapter driver. 1467 */ 1468 switch (cmd) { 1469 case ATABUSIOSCAN: 1470 case ATABUSIODETACH: 1471 case ATABUSIORESET: 1472 if ((flag & FWRITE) == 0) 1473 return (EBADF); 1474 } 1475 1476 switch (cmd) { 1477 case ATABUSIORESET: 1478 s = splbio(); 1479 ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL); 1480 splx(s); 1481 return 0; 1482 case ATABUSIOSCAN: 1483 { 1484 #if 0 1485 struct atabusioscan_args *a= 1486 (struct atabusioscan_args *)addr; 1487 #endif 1488 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1489 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1490 return (EOPNOTSUPP); 1491 return (EOPNOTSUPP); 1492 } 1493 case ATABUSIODETACH: 1494 { 1495 struct atabusioscan_args *a= 1496 (struct atabusioscan_args *)addr; 1497 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1498 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1499 return (EOPNOTSUPP); 1500 switch (a->at_dev) { 1501 case -1: 1502 min_drive = 0; 1503 max_drive = 1; 1504 break; 1505 case 0: 1506 case 1: 1507 min_drive = max_drive = a->at_dev; 1508 break; 1509 default: 1510 return (EINVAL); 1511 } 1512 for (drive = min_drive; drive <= max_drive; drive++) { 1513 if (chp->ch_drive[drive].drv_softc != NULL) { 1514 error = config_detach( 1515 chp->ch_drive[drive].drv_softc, 0); 1516 if (error) 1517 return (error); 1518 KASSERT(chp->ch_drive[drive].drv_softc == NULL); 1519 } 1520 } 1521 return 0; 1522 } 1523 default: 1524 return ENOTTY; 1525 } 1526 } 1527 1528 static bool 1529 atabus_suspend(device_t dv, const pmf_qual_t *qual) 1530 { 1531 struct atabus_softc *sc = device_private(dv); 1532 struct ata_channel *chp = sc->sc_chan; 1533 1534 ata_queue_idle(chp->ch_queue); 1535 1536 return true; 1537 } 1538 1539 static bool 1540 atabus_resume(device_t dv, const pmf_qual_t *qual) 1541 { 1542 struct atabus_softc *sc = device_private(dv); 1543 struct ata_channel *chp = sc->sc_chan; 1544 int s; 1545 1546 /* 1547 * XXX joerg: with wdc, the first channel unfreezes the controler. 1548 * Move this the reset and queue idling into wdc. 1549 */ 1550 s = splbio(); 1551 if (chp->ch_queue->queue_freeze == 0) { 1552 splx(s); 1553 return true; 1554 } 1555 KASSERT(chp->ch_queue->queue_freeze > 0); 1556 /* unfreeze the queue and reset drives */ 1557 chp->ch_queue->queue_freeze--; 1558 ata_reset_channel(chp, AT_WAIT); 1559 splx(s); 1560 1561 return true; 1562 } 1563
Indexes created Mon Sep 29 13:09:55 GMT 2025