ata.c revision 1.122
1 /* $NetBSD: ata.c,v 1.122 2012/07/26 20:49:47 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.122 2012/07/26 20:49:47 jakllsch Exp $"); 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/fcntl.h> 39 #include <sys/proc.h> 40 #include <sys/pool.h> 41 #include <sys/kthread.h> 42 #include <sys/errno.h> 43 #include <sys/ataio.h> 44 #include <sys/kmem.h> 45 #include <sys/intr.h> 46 #include <sys/bus.h> 47 #include <sys/once.h> 48 49 #include <dev/ata/ataconf.h> 50 #include <dev/ata/atareg.h> 51 #include <dev/ata/atavar.h> 52 #include <dev/ic/wdcvar.h> /* for PIOBM */ 53 54 #include "locators.h" 55 56 #include "atapibus.h" 57 #include "ataraid.h" 58 59 #if NATARAID > 0 60 #include <dev/ata/ata_raidvar.h> 61 #endif 62 63 #define DEBUG_FUNCS 0x08 64 #define DEBUG_PROBE 0x10 65 #define DEBUG_DETACH 0x20 66 #define DEBUG_XFERS 0x40 67 #ifdef ATADEBUG 68 int atadebug_mask = 0; 69 #define ATADEBUG_PRINT(args, level) \ 70 if (atadebug_mask & (level)) \ 71 printf args 72 #else 73 #define ATADEBUG_PRINT(args, level) 74 #endif 75 76 static ONCE_DECL(ata_init_ctrl); 77 static struct pool ata_xfer_pool; 78 79 /* 80 * A queue of atabus instances, used to ensure the same bus probe order 81 * for a given hardware configuration at each boot. Kthread probing 82 * devices on a atabus. Only one probing at once. 83 */ 84 static TAILQ_HEAD(, atabus_initq) atabus_initq_head; 85 static kmutex_t atabus_qlock; 86 static kcondvar_t atabus_qcv; 87 static lwp_t * atabus_cfg_lwp; 88 89 /***************************************************************************** 90 * ATA bus layer. 91 * 92 * ATA controllers attach an atabus instance, which handles probing the bus 93 * for drives, etc. 94 *****************************************************************************/ 95 96 dev_type_open(atabusopen); 97 dev_type_close(atabusclose); 98 dev_type_ioctl(atabusioctl); 99 100 const struct cdevsw atabus_cdevsw = { 101 atabusopen, atabusclose, noread, nowrite, atabusioctl, 102 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 103 }; 104 105 extern struct cfdriver atabus_cd; 106 107 static void atabus_childdetached(device_t, device_t); 108 static int atabus_rescan(device_t, const char *, const int *); 109 static bool atabus_resume(device_t, const pmf_qual_t *); 110 static bool atabus_suspend(device_t, const pmf_qual_t *); 111 static void atabusconfig_thread(void *); 112 113 /* 114 * atabus_init: 115 * 116 * Initialize ATA subsystem structures. 117 */ 118 static int 119 atabus_init(void) 120 { 121 122 pool_init(&ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, 123 "ataspl", NULL, IPL_BIO); 124 TAILQ_INIT(&atabus_initq_head); 125 mutex_init(&atabus_qlock, MUTEX_DEFAULT, IPL_NONE); 126 cv_init(&atabus_qcv, "atainitq"); 127 return 0; 128 } 129 130 /* 131 * atabusprint: 132 * 133 * Autoconfiguration print routine used by ATA controllers when 134 * attaching an atabus instance. 135 */ 136 int 137 atabusprint(void *aux, const char *pnp) 138 { 139 struct ata_channel *chan = aux; 140 141 if (pnp) 142 aprint_normal("atabus at %s", pnp); 143 aprint_normal(" channel %d", chan->ch_channel); 144 145 return (UNCONF); 146 } 147 148 /* 149 * ataprint: 150 * 151 * Autoconfiguration print routine. 152 */ 153 int 154 ataprint(void *aux, const char *pnp) 155 { 156 struct ata_device *adev = aux; 157 158 if (pnp) 159 aprint_normal("wd at %s", pnp); 160 aprint_normal(" drive %d", adev->adev_drv_data->drive); 161 162 return (UNCONF); 163 } 164 165 /* 166 * ata_channel_attach: 167 * 168 * Common parts of attaching an atabus to an ATA controller channel. 169 */ 170 void 171 ata_channel_attach(struct ata_channel *chp) 172 { 173 174 if (chp->ch_flags & ATACH_DISABLED) 175 return; 176 177 /* XXX callout_destroy */ 178 callout_init(&chp->ch_callout, 0); 179 180 TAILQ_INIT(&chp->ch_queue->queue_xfer); 181 chp->ch_queue->queue_freeze = 0; 182 chp->ch_queue->queue_flags = 0; 183 chp->ch_queue->active_xfer = NULL; 184 185 chp->atabus = config_found_ia(chp->ch_atac->atac_dev, "ata", chp, 186 atabusprint); 187 } 188 189 static void 190 atabusconfig(struct atabus_softc *atabus_sc) 191 { 192 struct ata_channel *chp = atabus_sc->sc_chan; 193 struct atac_softc *atac = chp->ch_atac; 194 struct atabus_initq *atabus_initq = NULL; 195 int i, s, error; 196 197 /* we are in the atabus's thread context */ 198 s = splbio(); 199 chp->ch_flags |= ATACH_TH_RUN; 200 splx(s); 201 202 /* Probe for the drives. */ 203 /* XXX for SATA devices we will power up all drives at once */ 204 (*atac->atac_probe)(chp); 205 206 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 207 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 208 DEBUG_PROBE); 209 210 /* next operations will occurs in a separate thread */ 211 s = splbio(); 212 chp->ch_flags &= ~ATACH_TH_RUN; 213 splx(s); 214 215 /* Make sure the devices probe in atabus order to avoid jitter. */ 216 mutex_enter(&atabus_qlock); 217 for (;;) { 218 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 219 if (atabus_initq->atabus_sc == atabus_sc) 220 break; 221 cv_wait(&atabus_qcv, &atabus_qlock); 222 } 223 mutex_exit(&atabus_qlock); 224 225 /* If no drives, abort here */ 226 for (i = 0; i < chp->ch_ndrive; i++) 227 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 228 break; 229 if (i == chp->ch_ndrive) 230 goto out; 231 232 /* Shortcut in case we've been shutdown */ 233 if (chp->ch_flags & ATACH_SHUTDOWN) 234 goto out; 235 236 237 if ((error = kthread_create(PRI_NONE, 0, NULL, atabusconfig_thread, 238 atabus_sc, &atabus_cfg_lwp, 239 "%scnf", device_xname(atac->atac_dev))) != 0) 240 aprint_error_dev(atac->atac_dev, 241 "unable to create config thread: error %d\n", error); 242 return; 243 244 out: 245 mutex_enter(&atabus_qlock); 246 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 247 cv_broadcast(&atabus_qcv); 248 mutex_exit(&atabus_qlock); 249 250 free(atabus_initq, M_DEVBUF); 251 252 ata_delref(chp); 253 254 config_pending_decr(); 255 } 256 257 /* 258 * atabus_configthread: finish attach of atabus's childrens, in a separate 259 * kernel thread. 260 */ 261 static void 262 atabusconfig_thread(void *arg) 263 { 264 struct atabus_softc *atabus_sc = arg; 265 struct ata_channel *chp = atabus_sc->sc_chan; 266 struct atac_softc *atac = chp->ch_atac; 267 struct atabus_initq *atabus_initq = NULL; 268 int i, s; 269 270 /* XXX seems wrong */ 271 mutex_enter(&atabus_qlock); 272 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 273 KASSERT(atabus_initq->atabus_sc == atabus_sc); 274 mutex_exit(&atabus_qlock); 275 276 /* 277 * Attach an ATAPI bus, if needed. 278 */ 279 for (i = 0; i < chp->ch_ndrive; i++) { 280 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 281 #if NATAPIBUS > 0 282 (*atac->atac_atapibus_attach)(atabus_sc); 283 #else 284 /* 285 * Fake the autoconfig "not configured" message 286 */ 287 aprint_normal("atapibus at %s not configured\n", 288 device_xname(atac->atac_dev)); 289 chp->atapibus = NULL; 290 s = splbio(); 291 for (i = 0; i < chp->ch_ndrive; i++) 292 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 293 splx(s); 294 #endif 295 break; 296 } 297 } 298 299 for (i = 0; i < chp->ch_ndrive; i++) { 300 struct ata_device adev; 301 if ((chp->ch_drive[i].drive_flags & 302 (DRIVE_ATA | DRIVE_OLD)) == 0) { 303 continue; 304 } 305 memset(&adev, 0, sizeof(struct ata_device)); 306 adev.adev_bustype = atac->atac_bustype_ata; 307 adev.adev_channel = chp->ch_channel; 308 adev.adev_openings = 1; 309 adev.adev_drv_data = &chp->ch_drive[i]; 310 chp->ata_drives[i] = config_found_ia(atabus_sc->sc_dev, 311 "ata_hl", &adev, ataprint); 312 if (chp->ata_drives[i] != NULL) 313 ata_probe_caps(&chp->ch_drive[i]); 314 else { 315 s = splbio(); 316 chp->ch_drive[i].drive_flags &= 317 ~(DRIVE_ATA | DRIVE_OLD); 318 splx(s); 319 } 320 } 321 322 /* now that we know the drives, the controller can set its modes */ 323 if (atac->atac_set_modes) { 324 (*atac->atac_set_modes)(chp); 325 ata_print_modes(chp); 326 } 327 #if NATARAID > 0 328 if (atac->atac_cap & ATAC_CAP_RAID) 329 for (i = 0; i < chp->ch_ndrive; i++) 330 if (chp->ata_drives[i] != NULL) 331 ata_raid_check_component(chp->ata_drives[i]); 332 #endif /* NATARAID > 0 */ 333 334 /* 335 * reset drive_flags for unattached devices, reset state for attached 336 * ones 337 */ 338 s = splbio(); 339 for (i = 0; i < chp->ch_ndrive; i++) { 340 if (chp->ch_drive[i].drv_softc == NULL) 341 chp->ch_drive[i].drive_flags = 0; 342 else 343 chp->ch_drive[i].state = 0; 344 } 345 splx(s); 346 347 mutex_enter(&atabus_qlock); 348 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 349 cv_broadcast(&atabus_qcv); 350 mutex_exit(&atabus_qlock); 351 352 free(atabus_initq, M_DEVBUF); 353 354 ata_delref(chp); 355 356 config_pending_decr(); 357 kthread_exit(0); 358 } 359 360 /* 361 * atabus_thread: 362 * 363 * Worker thread for the ATA bus. 364 */ 365 static void 366 atabus_thread(void *arg) 367 { 368 struct atabus_softc *sc = arg; 369 struct ata_channel *chp = sc->sc_chan; 370 struct ata_xfer *xfer; 371 int i, s; 372 373 s = splbio(); 374 chp->ch_flags |= ATACH_TH_RUN; 375 376 /* 377 * Probe the drives. Reset all flags to 0 to indicate to controllers 378 * that can re-probe that all drives must be probed.. 379 * 380 * Note: ch_ndrive may be changed during the probe. 381 */ 382 for (i = 0; i < ATA_MAXDRIVES; i++) 383 chp->ch_drive[i].drive_flags = 0; 384 splx(s); 385 386 atabusconfig(sc); 387 388 s = splbio(); 389 for (;;) { 390 if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 && 391 (chp->ch_queue->active_xfer == NULL || 392 chp->ch_queue->queue_freeze == 0)) { 393 chp->ch_flags &= ~ATACH_TH_RUN; 394 (void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0); 395 chp->ch_flags |= ATACH_TH_RUN; 396 } 397 if (chp->ch_flags & ATACH_SHUTDOWN) { 398 break; 399 } 400 if (chp->ch_flags & ATACH_TH_RESCAN) { 401 atabusconfig(sc); 402 chp->ch_flags &= ~ATACH_TH_RESCAN; 403 } 404 if (chp->ch_flags & ATACH_TH_RESET) { 405 /* 406 * ata_reset_channel() will freeze 2 times, so 407 * unfreeze one time. Not a problem as we're at splbio 408 */ 409 chp->ch_queue->queue_freeze--; 410 ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags); 411 } else if (chp->ch_queue->active_xfer != NULL && 412 chp->ch_queue->queue_freeze == 1) { 413 /* 414 * Caller has bumped queue_freeze, decrease it. 415 */ 416 chp->ch_queue->queue_freeze--; 417 xfer = chp->ch_queue->active_xfer; 418 KASSERT(xfer != NULL); 419 (*xfer->c_start)(xfer->c_chp, xfer); 420 } else if (chp->ch_queue->queue_freeze > 1) 421 panic("ata_thread: queue_freeze"); 422 } 423 splx(s); 424 chp->ch_thread = NULL; 425 wakeup(&chp->ch_flags); 426 kthread_exit(0); 427 } 428 429 /* 430 * atabus_match: 431 * 432 * Autoconfiguration match routine. 433 */ 434 static int 435 atabus_match(device_t parent, cfdata_t cf, void *aux) 436 { 437 struct ata_channel *chp = aux; 438 439 if (chp == NULL) 440 return (0); 441 442 if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel && 443 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 444 return (0); 445 446 return (1); 447 } 448 449 /* 450 * atabus_attach: 451 * 452 * Autoconfiguration attach routine. 453 */ 454 static void 455 atabus_attach(device_t parent, device_t self, void *aux) 456 { 457 struct atabus_softc *sc = device_private(self); 458 struct ata_channel *chp = aux; 459 struct atabus_initq *initq; 460 int error; 461 462 sc->sc_chan = chp; 463 464 aprint_normal("\n"); 465 aprint_naive("\n"); 466 467 sc->sc_dev = self; 468 469 if (ata_addref(chp)) 470 return; 471 472 RUN_ONCE(&ata_init_ctrl, atabus_init); 473 474 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 475 initq->atabus_sc = sc; 476 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 477 config_pending_incr(); 478 479 if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc, 480 &chp->ch_thread, "%s", device_xname(self))) != 0) 481 aprint_error_dev(self, 482 "unable to create kernel thread: error %d\n", error); 483 484 if (!pmf_device_register(self, atabus_suspend, atabus_resume)) 485 aprint_error_dev(self, "couldn't establish power handler\n"); 486 } 487 488 /* 489 * atabus_detach: 490 * 491 * Autoconfiguration detach routine. 492 */ 493 static int 494 atabus_detach(device_t self, int flags) 495 { 496 struct atabus_softc *sc = device_private(self); 497 struct ata_channel *chp = sc->sc_chan; 498 device_t dev = NULL; 499 int s, i, error = 0; 500 501 /* Shutdown the channel. */ 502 s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */ 503 chp->ch_flags |= ATACH_SHUTDOWN; 504 splx(s); 505 506 wakeup(&chp->ch_thread); 507 508 while (chp->ch_thread != NULL) 509 (void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 510 511 512 /* 513 * Detach atapibus and its children. 514 */ 515 if ((dev = chp->atapibus) != NULL) { 516 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 517 device_xname(self), device_xname(dev)), DEBUG_DETACH); 518 519 error = config_detach(dev, flags); 520 if (error) 521 goto out; 522 KASSERT(chp->atapibus == NULL); 523 } 524 525 /* 526 * Detach our other children. 527 */ 528 for (i = 0; i < chp->ch_ndrive; i++) { 529 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 530 continue; 531 if ((dev = chp->ata_drives[i]) != NULL) { 532 ATADEBUG_PRINT(("%s.%d: %s: detaching %s\n", __func__, 533 __LINE__, device_xname(self), device_xname(dev)), 534 DEBUG_DETACH); 535 KASSERT(chp->ch_drive[i].drv_softc == 536 chp->ata_drives[i]); 537 error = config_detach(dev, flags); 538 if (error) 539 goto out; 540 KASSERT(chp->ata_drives[i] == NULL); 541 } 542 } 543 544 out: 545 #ifdef ATADEBUG 546 if (dev != NULL && error != 0) 547 ATADEBUG_PRINT(("%s: %s: error %d detaching %s\n", __func__, 548 device_xname(self), error, device_xname(dev)), 549 DEBUG_DETACH); 550 #endif /* ATADEBUG */ 551 552 return (error); 553 } 554 555 void 556 atabus_childdetached(device_t self, device_t child) 557 { 558 bool found = false; 559 struct atabus_softc *sc = device_private(self); 560 struct ata_channel *chp = sc->sc_chan; 561 int i; 562 563 /* 564 * atapibus detached. 565 */ 566 if (child == chp->atapibus) { 567 chp->atapibus = NULL; 568 found = true; 569 } 570 571 /* 572 * Detach our other children. 573 */ 574 for (i = 0; i < chp->ch_ndrive; i++) { 575 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 576 continue; 577 if (child == chp->ata_drives[i]) { 578 KASSERT(chp->ata_drives[i] == 579 chp->ch_drive[i].drv_softc); 580 chp->ata_drives[i] = NULL; 581 chp->ch_drive[i].drv_softc = NULL; 582 chp->ch_drive[i].drive_flags = 0; 583 found = true; 584 } 585 } 586 587 if (!found) 588 panic("%s: unknown child %p", device_xname(self), 589 (const void *)child); 590 } 591 592 CFATTACH_DECL3_NEW(atabus, sizeof(struct atabus_softc), 593 atabus_match, atabus_attach, atabus_detach, NULL, atabus_rescan, 594 atabus_childdetached, DVF_DETACH_SHUTDOWN); 595 596 /***************************************************************************** 597 * Common ATA bus operations. 598 *****************************************************************************/ 599 600 /* Get the disk's parameters */ 601 int 602 ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags, 603 struct ataparams *prms) 604 { 605 struct ata_command ata_c; 606 struct ata_channel *chp = drvp->chnl_softc; 607 struct atac_softc *atac = chp->ch_atac; 608 char *tb; 609 int i, rv; 610 u_int16_t *p; 611 612 ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS); 613 614 tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP); 615 memset(prms, 0, sizeof(struct ataparams)); 616 memset(&ata_c, 0, sizeof(struct ata_command)); 617 618 if (drvp->drive_flags & DRIVE_ATA) { 619 ata_c.r_command = WDCC_IDENTIFY; 620 ata_c.r_st_bmask = WDCS_DRDY; 621 ata_c.r_st_pmask = WDCS_DRQ; 622 ata_c.timeout = 3000; /* 3s */ 623 } else if (drvp->drive_flags & DRIVE_ATAPI) { 624 ata_c.r_command = ATAPI_IDENTIFY_DEVICE; 625 ata_c.r_st_bmask = 0; 626 ata_c.r_st_pmask = WDCS_DRQ; 627 ata_c.timeout = 10000; /* 10s */ 628 } else { 629 ATADEBUG_PRINT(("ata_get_parms: no disks\n"), 630 DEBUG_FUNCS|DEBUG_PROBE); 631 rv = CMD_ERR; 632 goto out; 633 } 634 ata_c.flags = AT_READ | flags; 635 ata_c.data = tb; 636 ata_c.bcount = DEV_BSIZE; 637 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 638 &ata_c) != ATACMD_COMPLETE) { 639 ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"), 640 DEBUG_FUNCS|DEBUG_PROBE); 641 rv = CMD_AGAIN; 642 goto out; 643 } 644 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 645 ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n", 646 ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE); 647 rv = CMD_ERR; 648 goto out; 649 } 650 /* if we didn't read any data something is wrong */ 651 if ((ata_c.flags & AT_XFDONE) == 0) { 652 rv = CMD_ERR; 653 goto out; 654 } 655 656 /* Read in parameter block. */ 657 memcpy(prms, tb, sizeof(struct ataparams)); 658 659 /* 660 * Shuffle string byte order. 661 * ATAPI NEC, Mitsumi and Pioneer drives and 662 * old ATA TDK CompactFlash cards 663 * have different byte order. 664 */ 665 #if BYTE_ORDER == BIG_ENDIAN 666 # define M(n) prms->atap_model[(n) ^ 1] 667 #else 668 # define M(n) prms->atap_model[n] 669 #endif 670 if ( 671 #if BYTE_ORDER == BIG_ENDIAN 672 ! 673 #endif 674 ((drvp->drive_flags & DRIVE_ATAPI) ? 675 ((M(0) == 'N' && M(1) == 'E') || 676 (M(0) == 'F' && M(1) == 'X') || 677 (M(0) == 'P' && M(1) == 'i')) : 678 ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) { 679 rv = CMD_OK; 680 goto out; 681 } 682 #undef M 683 for (i = 0; i < sizeof(prms->atap_model); i += 2) { 684 p = (u_int16_t *)(prms->atap_model + i); 685 *p = bswap16(*p); 686 } 687 for (i = 0; i < sizeof(prms->atap_serial); i += 2) { 688 p = (u_int16_t *)(prms->atap_serial + i); 689 *p = bswap16(*p); 690 } 691 for (i = 0; i < sizeof(prms->atap_revision); i += 2) { 692 p = (u_int16_t *)(prms->atap_revision + i); 693 *p = bswap16(*p); 694 } 695 696 rv = CMD_OK; 697 out: 698 kmem_free(tb, DEV_BSIZE); 699 return rv; 700 } 701 702 int 703 ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags) 704 { 705 struct ata_command ata_c; 706 struct ata_channel *chp = drvp->chnl_softc; 707 struct atac_softc *atac = chp->ch_atac; 708 709 ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS); 710 memset(&ata_c, 0, sizeof(struct ata_command)); 711 712 ata_c.r_command = SET_FEATURES; 713 ata_c.r_st_bmask = 0; 714 ata_c.r_st_pmask = 0; 715 ata_c.r_features = WDSF_SET_MODE; 716 ata_c.r_count = mode; 717 ata_c.flags = flags; 718 ata_c.timeout = 1000; /* 1s */ 719 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 720 &ata_c) != ATACMD_COMPLETE) 721 return CMD_AGAIN; 722 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 723 return CMD_ERR; 724 } 725 return CMD_OK; 726 } 727 728 #if NATA_DMA 729 void 730 ata_dmaerr(struct ata_drive_datas *drvp, int flags) 731 { 732 /* 733 * Downgrade decision: if we get NERRS_MAX in NXFER. 734 * We start with n_dmaerrs set to NERRS_MAX-1 so that the 735 * first error within the first NXFER ops will immediatly trigger 736 * a downgrade. 737 * If we got an error and n_xfers is bigger than NXFER reset counters. 738 */ 739 drvp->n_dmaerrs++; 740 if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) { 741 ata_downgrade_mode(drvp, flags); 742 drvp->n_dmaerrs = NERRS_MAX-1; 743 drvp->n_xfers = 0; 744 return; 745 } 746 if (drvp->n_xfers > NXFER) { 747 drvp->n_dmaerrs = 1; /* just got an error */ 748 drvp->n_xfers = 1; /* restart counting from this error */ 749 } 750 } 751 #endif /* NATA_DMA */ 752 753 /* 754 * freeze the queue and wait for the controller to be idle. Caller has to 755 * unfreeze/restart the queue 756 */ 757 void 758 ata_queue_idle(struct ata_queue *queue) 759 { 760 int s = splbio(); 761 queue->queue_freeze++; 762 while (queue->active_xfer != NULL) { 763 queue->queue_flags |= QF_IDLE_WAIT; 764 tsleep(&queue->queue_flags, PRIBIO, "qidl", 0); 765 } 766 splx(s); 767 } 768 769 /* 770 * Add a command to the queue and start controller. 771 * 772 * MUST BE CALLED AT splbio()! 773 */ 774 void 775 ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 776 { 777 778 ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer, 779 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 780 781 /* complete xfer setup */ 782 xfer->c_chp = chp; 783 784 /* insert at the end of command list */ 785 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 786 ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n", 787 chp->ch_flags), DEBUG_XFERS); 788 /* 789 * if polling and can sleep, wait for the xfer to be at head of queue 790 */ 791 if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) { 792 while (chp->ch_queue->active_xfer != NULL || 793 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) { 794 xfer->c_flags |= C_WAITACT; 795 tsleep(xfer, PRIBIO, "ataact", 0); 796 xfer->c_flags &= ~C_WAITACT; 797 if (xfer->c_flags & C_FREE) { 798 ata_free_xfer(chp, xfer); 799 return; 800 } 801 } 802 } 803 atastart(chp); 804 } 805 806 /* 807 * Start I/O on a controller, for the given channel. 808 * The first xfer may be not for our channel if the channel queues 809 * are shared. 810 * 811 * MUST BE CALLED AT splbio()! 812 */ 813 void 814 atastart(struct ata_channel *chp) 815 { 816 struct atac_softc *atac = chp->ch_atac; 817 struct ata_xfer *xfer; 818 819 #ifdef ATA_DEBUG 820 int spl1, spl2; 821 822 spl1 = splbio(); 823 spl2 = splbio(); 824 if (spl2 != spl1) { 825 printf("atastart: not at splbio()\n"); 826 panic("atastart"); 827 } 828 splx(spl2); 829 splx(spl1); 830 #endif /* ATA_DEBUG */ 831 832 /* is there a xfer ? */ 833 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 834 return; 835 836 /* adjust chp, in case we have a shared queue */ 837 chp = xfer->c_chp; 838 839 if (chp->ch_queue->active_xfer != NULL) { 840 return; /* channel aleady active */ 841 } 842 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 843 if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) { 844 chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT; 845 wakeup(&chp->ch_queue->queue_flags); 846 } 847 return; /* queue frozen */ 848 } 849 /* 850 * if someone is waiting for the command to be active, wake it up 851 * and let it process the command 852 */ 853 if (xfer->c_flags & C_WAITACT) { 854 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d " 855 "wait active\n", xfer, chp->ch_channel, xfer->c_drive), 856 DEBUG_XFERS); 857 wakeup(xfer); 858 return; 859 } 860 #ifdef DIAGNOSTIC 861 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) 862 panic("atastart: channel waiting for irq"); 863 #endif 864 if (atac->atac_claim_hw) 865 if (!(*atac->atac_claim_hw)(chp, 0)) 866 return; 867 868 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer, 869 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 870 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 871 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 872 chp->ch_drive[xfer->c_drive].state = 0; 873 } 874 chp->ch_queue->active_xfer = xfer; 875 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 876 877 if (atac->atac_cap & ATAC_CAP_NOIRQ) 878 KASSERT(xfer->c_flags & C_POLL); 879 880 xfer->c_start(chp, xfer); 881 } 882 883 struct ata_xfer * 884 ata_get_xfer(int flags) 885 { 886 struct ata_xfer *xfer; 887 int s; 888 889 s = splbio(); 890 xfer = pool_get(&ata_xfer_pool, 891 ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 892 splx(s); 893 if (xfer != NULL) { 894 memset(xfer, 0, sizeof(struct ata_xfer)); 895 } 896 return xfer; 897 } 898 899 void 900 ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 901 { 902 struct atac_softc *atac = chp->ch_atac; 903 int s; 904 905 if (xfer->c_flags & C_WAITACT) { 906 /* Someone is waiting for this xfer, so we can't free now */ 907 xfer->c_flags |= C_FREE; 908 wakeup(xfer); 909 return; 910 } 911 912 #if NATA_PIOBM /* XXX wdc dependent code */ 913 if (xfer->c_flags & C_PIOBM) { 914 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 915 916 /* finish the busmastering PIO */ 917 (*wdc->piobm_done)(wdc->dma_arg, 918 chp->ch_channel, xfer->c_drive); 919 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT); 920 } 921 #endif 922 923 if (atac->atac_free_hw) 924 (*atac->atac_free_hw)(chp); 925 s = splbio(); 926 pool_put(&ata_xfer_pool, xfer); 927 splx(s); 928 } 929 930 /* 931 * Kill off all pending xfers for a ata_channel. 932 * 933 * Must be called at splbio(). 934 */ 935 void 936 ata_kill_pending(struct ata_drive_datas *drvp) 937 { 938 struct ata_channel *chp = drvp->chnl_softc; 939 struct ata_xfer *xfer, *next_xfer; 940 int s = splbio(); 941 942 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 943 xfer != NULL; xfer = next_xfer) { 944 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 945 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 946 continue; 947 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 948 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 949 } 950 951 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 952 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 953 drvp->drive_flags |= DRIVE_WAITDRAIN; 954 (void) tsleep(&chp->ch_queue->active_xfer, 955 PRIBIO, "atdrn", 0); 956 } else { 957 /* no more xfer for us */ 958 break; 959 } 960 } 961 splx(s); 962 } 963 964 /* 965 * ata_reset_channel: 966 * 967 * Reset and ATA channel. 968 * 969 * MUST BE CALLED AT splbio()! 970 */ 971 void 972 ata_reset_channel(struct ata_channel *chp, int flags) 973 { 974 struct atac_softc *atac = chp->ch_atac; 975 int drive; 976 977 #ifdef ATA_DEBUG 978 int spl1, spl2; 979 980 spl1 = splbio(); 981 spl2 = splbio(); 982 if (spl2 != spl1) { 983 printf("ata_reset_channel: not at splbio()\n"); 984 panic("ata_reset_channel"); 985 } 986 splx(spl2); 987 splx(spl1); 988 #endif /* ATA_DEBUG */ 989 990 chp->ch_queue->queue_freeze++; 991 992 /* 993 * If we can poll or wait it's OK, otherwise wake up the 994 * kernel thread to do it for us. 995 */ 996 ATADEBUG_PRINT(("ata_reset_channel flags 0x%x ch_flags 0x%x\n", 997 flags, chp->ch_flags), DEBUG_FUNCS | DEBUG_XFERS); 998 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 999 if (chp->ch_flags & ATACH_TH_RESET) { 1000 /* No need to schedule a reset more than one time. */ 1001 chp->ch_queue->queue_freeze--; 1002 return; 1003 } 1004 chp->ch_flags |= ATACH_TH_RESET; 1005 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 1006 wakeup(&chp->ch_thread); 1007 return; 1008 } 1009 1010 (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags); 1011 1012 for (drive = 0; drive < chp->ch_ndrive; drive++) 1013 chp->ch_drive[drive].state = 0; 1014 1015 chp->ch_flags &= ~ATACH_TH_RESET; 1016 if ((flags & AT_RST_EMERG) == 0) { 1017 chp->ch_queue->queue_freeze--; 1018 atastart(chp); 1019 } else { 1020 /* make sure that we can use polled commands */ 1021 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1022 chp->ch_queue->queue_freeze = 0; 1023 chp->ch_queue->active_xfer = NULL; 1024 } 1025 } 1026 1027 int 1028 ata_addref(struct ata_channel *chp) 1029 { 1030 struct atac_softc *atac = chp->ch_atac; 1031 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1032 int s, error = 0; 1033 1034 s = splbio(); 1035 if (adapt->adapt_refcnt++ == 0 && 1036 adapt->adapt_enable != NULL) { 1037 error = (*adapt->adapt_enable)(atac->atac_dev, 1); 1038 if (error) 1039 adapt->adapt_refcnt--; 1040 } 1041 splx(s); 1042 return (error); 1043 } 1044 1045 void 1046 ata_delref(struct ata_channel *chp) 1047 { 1048 struct atac_softc *atac = chp->ch_atac; 1049 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1050 int s; 1051 1052 s = splbio(); 1053 if (adapt->adapt_refcnt-- == 1 && 1054 adapt->adapt_enable != NULL) 1055 (void) (*adapt->adapt_enable)(atac->atac_dev, 0); 1056 splx(s); 1057 } 1058 1059 void 1060 ata_print_modes(struct ata_channel *chp) 1061 { 1062 struct atac_softc *atac = chp->ch_atac; 1063 int drive; 1064 struct ata_drive_datas *drvp; 1065 1066 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1067 drvp = &chp->ch_drive[drive]; 1068 if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL) 1069 continue; 1070 aprint_verbose("%s(%s:%d:%d): using PIO mode %d", 1071 device_xname(drvp->drv_softc), 1072 device_xname(atac->atac_dev), 1073 chp->ch_channel, drvp->drive, drvp->PIO_mode); 1074 #if NATA_DMA 1075 if (drvp->drive_flags & DRIVE_DMA) 1076 aprint_verbose(", DMA mode %d", drvp->DMA_mode); 1077 #if NATA_UDMA 1078 if (drvp->drive_flags & DRIVE_UDMA) { 1079 aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode); 1080 if (drvp->UDMA_mode == 2) 1081 aprint_verbose(" (Ultra/33)"); 1082 else if (drvp->UDMA_mode == 4) 1083 aprint_verbose(" (Ultra/66)"); 1084 else if (drvp->UDMA_mode == 5) 1085 aprint_verbose(" (Ultra/100)"); 1086 else if (drvp->UDMA_mode == 6) 1087 aprint_verbose(" (Ultra/133)"); 1088 } 1089 #endif /* NATA_UDMA */ 1090 #endif /* NATA_DMA */ 1091 #if NATA_DMA || NATA_PIOBM 1092 if (0 1093 #if NATA_DMA 1094 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1095 #endif 1096 #if NATA_PIOBM 1097 /* PIOBM capable controllers use DMA for PIO commands */ 1098 || (atac->atac_cap & ATAC_CAP_PIOBM) 1099 #endif 1100 ) 1101 aprint_verbose(" (using DMA)"); 1102 #endif /* NATA_DMA || NATA_PIOBM */ 1103 aprint_verbose("\n"); 1104 } 1105 } 1106 1107 #if NATA_DMA 1108 /* 1109 * downgrade the transfer mode of a drive after an error. return 1 if 1110 * downgrade was possible, 0 otherwise. 1111 * 1112 * MUST BE CALLED AT splbio()! 1113 */ 1114 int 1115 ata_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1116 { 1117 struct ata_channel *chp = drvp->chnl_softc; 1118 struct atac_softc *atac = chp->ch_atac; 1119 device_t drv_dev = drvp->drv_softc; 1120 int cf_flags = device_cfdata(drv_dev)->cf_flags; 1121 1122 /* if drive or controller don't know its mode, we can't do much */ 1123 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1124 (atac->atac_set_modes == NULL)) 1125 return 0; 1126 /* current drive mode was set by a config flag, let it this way */ 1127 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1128 (cf_flags & ATA_CONFIG_DMA_SET) || 1129 (cf_flags & ATA_CONFIG_UDMA_SET)) 1130 return 0; 1131 1132 #if NATA_UDMA 1133 /* 1134 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1135 */ 1136 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1137 drvp->UDMA_mode--; 1138 aprint_error_dev(drv_dev, 1139 "transfer error, downgrading to Ultra-DMA mode %d\n", 1140 drvp->UDMA_mode); 1141 } 1142 #endif 1143 1144 /* 1145 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1146 */ 1147 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1148 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1149 drvp->PIO_mode = drvp->PIO_cap; 1150 aprint_error_dev(drv_dev, 1151 "transfer error, downgrading to PIO mode %d\n", 1152 drvp->PIO_mode); 1153 } else /* already using PIO, can't downgrade */ 1154 return 0; 1155 1156 (*atac->atac_set_modes)(chp); 1157 ata_print_modes(chp); 1158 /* reset the channel, which will schedule all drives for setup */ 1159 ata_reset_channel(chp, flags | AT_RST_NOCMD); 1160 return 1; 1161 } 1162 #endif /* NATA_DMA */ 1163 1164 /* 1165 * Probe drive's capabilities, for use by the controller later 1166 * Assumes drvp points to an existing drive. 1167 */ 1168 void 1169 ata_probe_caps(struct ata_drive_datas *drvp) 1170 { 1171 struct ataparams params, params2; 1172 struct ata_channel *chp = drvp->chnl_softc; 1173 struct atac_softc *atac = chp->ch_atac; 1174 device_t drv_dev = drvp->drv_softc; 1175 int i, printed, s; 1176 const char *sep = ""; 1177 int cf_flags; 1178 1179 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1180 /* IDENTIFY failed. Can't tell more about the device */ 1181 return; 1182 } 1183 if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == 1184 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 1185 /* 1186 * Controller claims 16 and 32 bit transfers. 1187 * Re-do an IDENTIFY with 32-bit transfers, 1188 * and compare results. 1189 */ 1190 s = splbio(); 1191 drvp->drive_flags |= DRIVE_CAP32; 1192 splx(s); 1193 ata_get_params(drvp, AT_WAIT, ¶ms2); 1194 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1195 /* Not good. fall back to 16bits */ 1196 s = splbio(); 1197 drvp->drive_flags &= ~DRIVE_CAP32; 1198 splx(s); 1199 } else { 1200 aprint_verbose_dev(drv_dev, "32-bit data port\n"); 1201 } 1202 } 1203 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1204 if (params.atap_ata_major > 0x01 && 1205 params.atap_ata_major != 0xffff) { 1206 for (i = 14; i > 0; i--) { 1207 if (params.atap_ata_major & (1 << i)) { 1208 aprint_verbose_dev(drv_dev, 1209 "ATA version %d\n", i); 1210 drvp->ata_vers = i; 1211 break; 1212 } 1213 } 1214 } 1215 #endif 1216 1217 /* An ATAPI device is at last PIO mode 3 */ 1218 if (drvp->drive_flags & DRIVE_ATAPI) 1219 drvp->PIO_mode = 3; 1220 1221 /* 1222 * It's not in the specs, but it seems that some drive 1223 * returns 0xffff in atap_extensions when this field is invalid 1224 */ 1225 if (params.atap_extensions != 0xffff && 1226 (params.atap_extensions & WDC_EXT_MODES)) { 1227 printed = 0; 1228 /* 1229 * XXX some drives report something wrong here (they claim to 1230 * support PIO mode 8 !). As mode is coded on 3 bits in 1231 * SET FEATURE, limit it to 7 (so limit i to 4). 1232 * If higher mode than 7 is found, abort. 1233 */ 1234 for (i = 7; i >= 0; i--) { 1235 if ((params.atap_piomode_supp & (1 << i)) == 0) 1236 continue; 1237 if (i > 4) 1238 return; 1239 /* 1240 * See if mode is accepted. 1241 * If the controller can't set its PIO mode, 1242 * assume the defaults are good, so don't try 1243 * to set it 1244 */ 1245 if (atac->atac_set_modes) 1246 /* 1247 * It's OK to pool here, it's fast enough 1248 * to not bother waiting for interrupt 1249 */ 1250 if (ata_set_mode(drvp, 0x08 | (i + 3), 1251 AT_WAIT) != CMD_OK) 1252 continue; 1253 if (!printed) { 1254 aprint_verbose_dev(drv_dev, 1255 "drive supports PIO mode %d", i + 3); 1256 sep = ","; 1257 printed = 1; 1258 } 1259 /* 1260 * If controller's driver can't set its PIO mode, 1261 * get the highter one for the drive. 1262 */ 1263 if (atac->atac_set_modes == NULL || 1264 atac->atac_pio_cap >= i + 3) { 1265 drvp->PIO_mode = i + 3; 1266 drvp->PIO_cap = i + 3; 1267 break; 1268 } 1269 } 1270 if (!printed) { 1271 /* 1272 * We didn't find a valid PIO mode. 1273 * Assume the values returned for DMA are buggy too 1274 */ 1275 return; 1276 } 1277 s = splbio(); 1278 drvp->drive_flags |= DRIVE_MODE; 1279 splx(s); 1280 printed = 0; 1281 for (i = 7; i >= 0; i--) { 1282 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1283 continue; 1284 #if NATA_DMA 1285 if ((atac->atac_cap & ATAC_CAP_DMA) && 1286 atac->atac_set_modes != NULL) 1287 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1288 != CMD_OK) 1289 continue; 1290 #endif 1291 if (!printed) { 1292 aprint_verbose("%s DMA mode %d", sep, i); 1293 sep = ","; 1294 printed = 1; 1295 } 1296 #if NATA_DMA 1297 if (atac->atac_cap & ATAC_CAP_DMA) { 1298 if (atac->atac_set_modes != NULL && 1299 atac->atac_dma_cap < i) 1300 continue; 1301 drvp->DMA_mode = i; 1302 drvp->DMA_cap = i; 1303 s = splbio(); 1304 drvp->drive_flags |= DRIVE_DMA; 1305 splx(s); 1306 } 1307 #endif 1308 break; 1309 } 1310 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1311 printed = 0; 1312 for (i = 7; i >= 0; i--) { 1313 if ((params.atap_udmamode_supp & (1 << i)) 1314 == 0) 1315 continue; 1316 #if NATA_UDMA 1317 if (atac->atac_set_modes != NULL && 1318 (atac->atac_cap & ATAC_CAP_UDMA)) 1319 if (ata_set_mode(drvp, 0x40 | i, 1320 AT_WAIT) != CMD_OK) 1321 continue; 1322 #endif 1323 if (!printed) { 1324 aprint_verbose("%s Ultra-DMA mode %d", 1325 sep, i); 1326 if (i == 2) 1327 aprint_verbose(" (Ultra/33)"); 1328 else if (i == 4) 1329 aprint_verbose(" (Ultra/66)"); 1330 else if (i == 5) 1331 aprint_verbose(" (Ultra/100)"); 1332 else if (i == 6) 1333 aprint_verbose(" (Ultra/133)"); 1334 sep = ","; 1335 printed = 1; 1336 } 1337 #if NATA_UDMA 1338 if (atac->atac_cap & ATAC_CAP_UDMA) { 1339 if (atac->atac_set_modes != NULL && 1340 atac->atac_udma_cap < i) 1341 continue; 1342 drvp->UDMA_mode = i; 1343 drvp->UDMA_cap = i; 1344 s = splbio(); 1345 drvp->drive_flags |= DRIVE_UDMA; 1346 splx(s); 1347 } 1348 #endif 1349 break; 1350 } 1351 } 1352 aprint_verbose("\n"); 1353 } 1354 1355 s = splbio(); 1356 drvp->drive_flags &= ~DRIVE_NOSTREAM; 1357 if (drvp->drive_flags & DRIVE_ATAPI) { 1358 if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM) 1359 drvp->drive_flags |= DRIVE_NOSTREAM; 1360 } else { 1361 if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM) 1362 drvp->drive_flags |= DRIVE_NOSTREAM; 1363 } 1364 splx(s); 1365 1366 /* Try to guess ATA version here, if it didn't get reported */ 1367 if (drvp->ata_vers == 0) { 1368 #if NATA_UDMA 1369 if (drvp->drive_flags & DRIVE_UDMA) 1370 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1371 else 1372 #endif 1373 if (drvp->PIO_cap > 2) 1374 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1375 } 1376 cf_flags = device_cfdata(drv_dev)->cf_flags; 1377 if (cf_flags & ATA_CONFIG_PIO_SET) { 1378 s = splbio(); 1379 drvp->PIO_mode = 1380 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1381 drvp->drive_flags |= DRIVE_MODE; 1382 splx(s); 1383 } 1384 #if NATA_DMA 1385 if ((atac->atac_cap & ATAC_CAP_DMA) == 0) { 1386 /* don't care about DMA modes */ 1387 return; 1388 } 1389 if (cf_flags & ATA_CONFIG_DMA_SET) { 1390 s = splbio(); 1391 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1392 ATA_CONFIG_DMA_DISABLE) { 1393 drvp->drive_flags &= ~DRIVE_DMA; 1394 } else { 1395 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1396 ATA_CONFIG_DMA_OFF; 1397 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1398 } 1399 splx(s); 1400 } 1401 #if NATA_UDMA 1402 if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) { 1403 /* don't care about UDMA modes */ 1404 return; 1405 } 1406 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1407 s = splbio(); 1408 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1409 ATA_CONFIG_UDMA_DISABLE) { 1410 drvp->drive_flags &= ~DRIVE_UDMA; 1411 } else { 1412 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1413 ATA_CONFIG_UDMA_OFF; 1414 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1415 } 1416 splx(s); 1417 } 1418 #endif /* NATA_UDMA */ 1419 #endif /* NATA_DMA */ 1420 } 1421 1422 /* management of the /dev/atabus* devices */ 1423 int 1424 atabusopen(dev_t dev, int flag, int fmt, struct lwp *l) 1425 { 1426 struct atabus_softc *sc; 1427 int error; 1428 1429 sc = device_lookup_private(&atabus_cd, minor(dev)); 1430 if (sc == NULL) 1431 return (ENXIO); 1432 1433 if (sc->sc_flags & ATABUSCF_OPEN) 1434 return (EBUSY); 1435 1436 if ((error = ata_addref(sc->sc_chan)) != 0) 1437 return (error); 1438 1439 sc->sc_flags |= ATABUSCF_OPEN; 1440 1441 return (0); 1442 } 1443 1444 1445 int 1446 atabusclose(dev_t dev, int flag, int fmt, struct lwp *l) 1447 { 1448 struct atabus_softc *sc = 1449 device_lookup_private(&atabus_cd, minor(dev)); 1450 1451 ata_delref(sc->sc_chan); 1452 1453 sc->sc_flags &= ~ATABUSCF_OPEN; 1454 1455 return (0); 1456 } 1457 1458 int 1459 atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, struct lwp *l) 1460 { 1461 struct atabus_softc *sc = 1462 device_lookup_private(&atabus_cd, minor(dev)); 1463 struct ata_channel *chp = sc->sc_chan; 1464 int min_drive, max_drive, drive; 1465 int error; 1466 int s; 1467 1468 /* 1469 * Enforce write permission for ioctls that change the 1470 * state of the bus. Host adapter specific ioctls must 1471 * be checked by the adapter driver. 1472 */ 1473 switch (cmd) { 1474 case ATABUSIOSCAN: 1475 case ATABUSIODETACH: 1476 case ATABUSIORESET: 1477 if ((flag & FWRITE) == 0) 1478 return (EBADF); 1479 } 1480 1481 switch (cmd) { 1482 case ATABUSIORESET: 1483 s = splbio(); 1484 ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL); 1485 splx(s); 1486 return 0; 1487 case ATABUSIOSCAN: 1488 { 1489 #if 0 1490 struct atabusioscan_args *a= 1491 (struct atabusioscan_args *)addr; 1492 #endif 1493 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1494 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1495 return (EOPNOTSUPP); 1496 return (EOPNOTSUPP); 1497 } 1498 case ATABUSIODETACH: 1499 { 1500 struct atabusiodetach_args *a= 1501 (struct atabusiodetach_args *)addr; 1502 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1503 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1504 return (EOPNOTSUPP); 1505 switch (a->at_dev) { 1506 case -1: 1507 min_drive = 0; 1508 max_drive = 1; 1509 break; 1510 case 0: 1511 case 1: 1512 min_drive = max_drive = a->at_dev; 1513 break; 1514 default: 1515 return (EINVAL); 1516 } 1517 for (drive = min_drive; drive <= max_drive; drive++) { 1518 if (chp->ch_drive[drive].drv_softc != NULL) { 1519 error = config_detach( 1520 chp->ch_drive[drive].drv_softc, 0); 1521 if (error) 1522 return (error); 1523 KASSERT(chp->ch_drive[drive].drv_softc == NULL); 1524 } 1525 } 1526 return 0; 1527 } 1528 default: 1529 return ENOTTY; 1530 } 1531 } 1532 1533 static bool 1534 atabus_suspend(device_t dv, const pmf_qual_t *qual) 1535 { 1536 struct atabus_softc *sc = device_private(dv); 1537 struct ata_channel *chp = sc->sc_chan; 1538 1539 ata_queue_idle(chp->ch_queue); 1540 1541 return true; 1542 } 1543 1544 static bool 1545 atabus_resume(device_t dv, const pmf_qual_t *qual) 1546 { 1547 struct atabus_softc *sc = device_private(dv); 1548 struct ata_channel *chp = sc->sc_chan; 1549 int s; 1550 1551 /* 1552 * XXX joerg: with wdc, the first channel unfreezes the controler. 1553 * Move this the reset and queue idling into wdc. 1554 */ 1555 s = splbio(); 1556 if (chp->ch_queue->queue_freeze == 0) { 1557 splx(s); 1558 return true; 1559 } 1560 KASSERT(chp->ch_queue->queue_freeze > 0); 1561 /* unfreeze the queue and reset drives */ 1562 chp->ch_queue->queue_freeze--; 1563 ata_reset_channel(chp, AT_WAIT); 1564 splx(s); 1565 1566 return true; 1567 } 1568 1569 static int 1570 atabus_rescan(device_t self, const char *ifattr, const int *locators) 1571 { 1572 struct atabus_softc *sc = device_private(self); 1573 struct ata_channel *chp = sc->sc_chan; 1574 struct atabus_initq *initq; 1575 int i; 1576 int s; 1577 1578 if (chp->atapibus != NULL) { 1579 return EBUSY; 1580 } 1581 1582 for (i = 0; i < ATA_MAXDRIVES; i++) { 1583 if (chp->ata_drives[i] != NULL) { 1584 return EBUSY; 1585 } 1586 } 1587 1588 s = splbio(); 1589 for (i = 0; i < ATA_MAXDRIVES; i++) { 1590 chp->ch_drive[i].drive_flags = 0; 1591 } 1592 splx(s); 1593 1594 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 1595 initq->atabus_sc = sc; 1596 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 1597 config_pending_incr(); 1598 1599 chp->ch_flags |= ATACH_TH_RESCAN; 1600 wakeup(&chp->ch_thread); 1601 1602 return 0; 1603 } 1604
Indexes created Mon Sep 29 03:10:08 GMT 2025