ata.c revision 1.123
1 /* $NetBSD: ata.c,v 1.123 2012/07/29 21:10:50 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.123 2012/07/29 21:10:50 jakllsch Exp $"); 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/fcntl.h> 39 #include <sys/proc.h> 40 #include <sys/pool.h> 41 #include <sys/kthread.h> 42 #include <sys/errno.h> 43 #include <sys/ataio.h> 44 #include <sys/kmem.h> 45 #include <sys/intr.h> 46 #include <sys/bus.h> 47 #include <sys/once.h> 48 49 #include <dev/ata/ataconf.h> 50 #include <dev/ata/atareg.h> 51 #include <dev/ata/atavar.h> 52 #include <dev/ic/wdcvar.h> /* for PIOBM */ 53 54 #include "locators.h" 55 56 #include "atapibus.h" 57 #include "ataraid.h" 58 59 #if NATARAID > 0 60 #include <dev/ata/ata_raidvar.h> 61 #endif 62 63 #define DEBUG_FUNCS 0x08 64 #define DEBUG_PROBE 0x10 65 #define DEBUG_DETACH 0x20 66 #define DEBUG_XFERS 0x40 67 #ifdef ATADEBUG 68 int atadebug_mask = 0; 69 #define ATADEBUG_PRINT(args, level) \ 70 if (atadebug_mask & (level)) \ 71 printf args 72 #else 73 #define ATADEBUG_PRINT(args, level) 74 #endif 75 76 static ONCE_DECL(ata_init_ctrl); 77 static struct pool ata_xfer_pool; 78 79 /* 80 * A queue of atabus instances, used to ensure the same bus probe order 81 * for a given hardware configuration at each boot. Kthread probing 82 * devices on a atabus. Only one probing at once. 83 */ 84 static TAILQ_HEAD(, atabus_initq) atabus_initq_head; 85 static kmutex_t atabus_qlock; 86 static kcondvar_t atabus_qcv; 87 static lwp_t * atabus_cfg_lwp; 88 89 /***************************************************************************** 90 * ATA bus layer. 91 * 92 * ATA controllers attach an atabus instance, which handles probing the bus 93 * for drives, etc. 94 *****************************************************************************/ 95 96 dev_type_open(atabusopen); 97 dev_type_close(atabusclose); 98 dev_type_ioctl(atabusioctl); 99 100 const struct cdevsw atabus_cdevsw = { 101 atabusopen, atabusclose, noread, nowrite, atabusioctl, 102 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 103 }; 104 105 extern struct cfdriver atabus_cd; 106 107 static void atabus_childdetached(device_t, device_t); 108 static int atabus_rescan(device_t, const char *, const int *); 109 static bool atabus_resume(device_t, const pmf_qual_t *); 110 static bool atabus_suspend(device_t, const pmf_qual_t *); 111 static void atabusconfig_thread(void *); 112 113 /* 114 * atabus_init: 115 * 116 * Initialize ATA subsystem structures. 117 */ 118 static int 119 atabus_init(void) 120 { 121 122 pool_init(&ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, 123 "ataspl", NULL, IPL_BIO); 124 TAILQ_INIT(&atabus_initq_head); 125 mutex_init(&atabus_qlock, MUTEX_DEFAULT, IPL_NONE); 126 cv_init(&atabus_qcv, "atainitq"); 127 return 0; 128 } 129 130 /* 131 * atabusprint: 132 * 133 * Autoconfiguration print routine used by ATA controllers when 134 * attaching an atabus instance. 135 */ 136 int 137 atabusprint(void *aux, const char *pnp) 138 { 139 struct ata_channel *chan = aux; 140 141 if (pnp) 142 aprint_normal("atabus at %s", pnp); 143 aprint_normal(" channel %d", chan->ch_channel); 144 145 return (UNCONF); 146 } 147 148 /* 149 * ataprint: 150 * 151 * Autoconfiguration print routine. 152 */ 153 int 154 ataprint(void *aux, const char *pnp) 155 { 156 struct ata_device *adev = aux; 157 158 if (pnp) 159 aprint_normal("wd at %s", pnp); 160 aprint_normal(" drive %d", adev->adev_drv_data->drive); 161 162 return (UNCONF); 163 } 164 165 /* 166 * ata_channel_attach: 167 * 168 * Common parts of attaching an atabus to an ATA controller channel. 169 */ 170 void 171 ata_channel_attach(struct ata_channel *chp) 172 { 173 174 if (chp->ch_flags & ATACH_DISABLED) 175 return; 176 177 /* XXX callout_destroy */ 178 callout_init(&chp->ch_callout, 0); 179 180 TAILQ_INIT(&chp->ch_queue->queue_xfer); 181 chp->ch_queue->queue_freeze = 0; 182 chp->ch_queue->queue_flags = 0; 183 chp->ch_queue->active_xfer = NULL; 184 185 chp->atabus = config_found_ia(chp->ch_atac->atac_dev, "ata", chp, 186 atabusprint); 187 } 188 189 static void 190 atabusconfig(struct atabus_softc *atabus_sc) 191 { 192 struct ata_channel *chp = atabus_sc->sc_chan; 193 struct atac_softc *atac = chp->ch_atac; 194 struct atabus_initq *atabus_initq = NULL; 195 int i, s, error; 196 197 /* we are in the atabus's thread context */ 198 s = splbio(); 199 chp->ch_flags |= ATACH_TH_RUN; 200 splx(s); 201 202 /* Probe for the drives. */ 203 /* XXX for SATA devices we will power up all drives at once */ 204 (*atac->atac_probe)(chp); 205 206 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 207 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 208 DEBUG_PROBE); 209 210 /* next operations will occurs in a separate thread */ 211 s = splbio(); 212 chp->ch_flags &= ~ATACH_TH_RUN; 213 splx(s); 214 215 /* Make sure the devices probe in atabus order to avoid jitter. */ 216 mutex_enter(&atabus_qlock); 217 for (;;) { 218 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 219 if (atabus_initq->atabus_sc == atabus_sc) 220 break; 221 cv_wait(&atabus_qcv, &atabus_qlock); 222 } 223 mutex_exit(&atabus_qlock); 224 225 /* If no drives, abort here */ 226 for (i = 0; i < chp->ch_ndrive; i++) 227 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 228 break; 229 if (i == chp->ch_ndrive) 230 goto out; 231 232 /* Shortcut in case we've been shutdown */ 233 if (chp->ch_flags & ATACH_SHUTDOWN) 234 goto out; 235 236 237 if ((error = kthread_create(PRI_NONE, 0, NULL, atabusconfig_thread, 238 atabus_sc, &atabus_cfg_lwp, 239 "%scnf", device_xname(atac->atac_dev))) != 0) 240 aprint_error_dev(atac->atac_dev, 241 "unable to create config thread: error %d\n", error); 242 return; 243 244 out: 245 mutex_enter(&atabus_qlock); 246 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 247 cv_broadcast(&atabus_qcv); 248 mutex_exit(&atabus_qlock); 249 250 free(atabus_initq, M_DEVBUF); 251 252 ata_delref(chp); 253 254 config_pending_decr(); 255 } 256 257 /* 258 * atabus_configthread: finish attach of atabus's childrens, in a separate 259 * kernel thread. 260 */ 261 static void 262 atabusconfig_thread(void *arg) 263 { 264 struct atabus_softc *atabus_sc = arg; 265 struct ata_channel *chp = atabus_sc->sc_chan; 266 struct atac_softc *atac = chp->ch_atac; 267 struct atabus_initq *atabus_initq = NULL; 268 int i, s; 269 270 /* XXX seems wrong */ 271 mutex_enter(&atabus_qlock); 272 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 273 KASSERT(atabus_initq->atabus_sc == atabus_sc); 274 mutex_exit(&atabus_qlock); 275 276 /* 277 * Attach an ATAPI bus, if needed. 278 */ 279 for (i = 0; i < chp->ch_ndrive; i++) { 280 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 281 #if NATAPIBUS > 0 282 (*atac->atac_atapibus_attach)(atabus_sc); 283 #else 284 /* 285 * Fake the autoconfig "not configured" message 286 */ 287 aprint_normal("atapibus at %s not configured\n", 288 device_xname(atac->atac_dev)); 289 chp->atapibus = NULL; 290 s = splbio(); 291 for (i = 0; i < chp->ch_ndrive; i++) 292 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 293 splx(s); 294 #endif 295 break; 296 } 297 } 298 299 for (i = 0; i < chp->ch_ndrive; i++) { 300 struct ata_device adev; 301 if ((chp->ch_drive[i].drive_flags & 302 (DRIVE_ATA | DRIVE_OLD)) == 0) { 303 continue; 304 } 305 memset(&adev, 0, sizeof(struct ata_device)); 306 adev.adev_bustype = atac->atac_bustype_ata; 307 adev.adev_channel = chp->ch_channel; 308 adev.adev_openings = 1; 309 adev.adev_drv_data = &chp->ch_drive[i]; 310 KASSERT(chp->ch_drive[i].drv_softc == NULL); 311 chp->ch_drive[i].drv_softc = config_found_ia(atabus_sc->sc_dev, 312 "ata_hl", &adev, ataprint); 313 if (chp->ch_drive[i].drv_softc != NULL) 314 ata_probe_caps(&chp->ch_drive[i]); 315 else { 316 s = splbio(); 317 chp->ch_drive[i].drive_flags &= 318 ~(DRIVE_ATA | DRIVE_OLD); 319 splx(s); 320 } 321 } 322 323 /* now that we know the drives, the controller can set its modes */ 324 if (atac->atac_set_modes) { 325 (*atac->atac_set_modes)(chp); 326 ata_print_modes(chp); 327 } 328 #if NATARAID > 0 329 if (atac->atac_cap & ATAC_CAP_RAID) { 330 for (i = 0; i < chp->ch_ndrive; i++) { 331 if ((chp->ch_drive[i].drv_softc != NULL) && 332 (chp->ch_drive[i].drive_flags & DRIVE_ATA)) { 333 ata_raid_check_component( 334 chp->ch_drive[i].drv_softc); 335 } 336 } 337 } 338 #endif /* NATARAID > 0 */ 339 340 /* 341 * reset drive_flags for unattached devices, reset state for attached 342 * ones 343 */ 344 s = splbio(); 345 for (i = 0; i < chp->ch_ndrive; i++) { 346 if (chp->ch_drive[i].drv_softc == NULL) 347 chp->ch_drive[i].drive_flags = 0; 348 else 349 chp->ch_drive[i].state = 0; 350 } 351 splx(s); 352 353 mutex_enter(&atabus_qlock); 354 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 355 cv_broadcast(&atabus_qcv); 356 mutex_exit(&atabus_qlock); 357 358 free(atabus_initq, M_DEVBUF); 359 360 ata_delref(chp); 361 362 config_pending_decr(); 363 kthread_exit(0); 364 } 365 366 /* 367 * atabus_thread: 368 * 369 * Worker thread for the ATA bus. 370 */ 371 static void 372 atabus_thread(void *arg) 373 { 374 struct atabus_softc *sc = arg; 375 struct ata_channel *chp = sc->sc_chan; 376 struct ata_xfer *xfer; 377 int i, s; 378 379 s = splbio(); 380 chp->ch_flags |= ATACH_TH_RUN; 381 382 /* 383 * Probe the drives. Reset all flags to 0 to indicate to controllers 384 * that can re-probe that all drives must be probed.. 385 * 386 * Note: ch_ndrive may be changed during the probe. 387 */ 388 for (i = 0; i < ATA_MAXDRIVES; i++) 389 chp->ch_drive[i].drive_flags = 0; 390 splx(s); 391 392 atabusconfig(sc); 393 394 s = splbio(); 395 for (;;) { 396 if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 && 397 (chp->ch_queue->active_xfer == NULL || 398 chp->ch_queue->queue_freeze == 0)) { 399 chp->ch_flags &= ~ATACH_TH_RUN; 400 (void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0); 401 chp->ch_flags |= ATACH_TH_RUN; 402 } 403 if (chp->ch_flags & ATACH_SHUTDOWN) { 404 break; 405 } 406 if (chp->ch_flags & ATACH_TH_RESCAN) { 407 atabusconfig(sc); 408 chp->ch_flags &= ~ATACH_TH_RESCAN; 409 } 410 if (chp->ch_flags & ATACH_TH_RESET) { 411 /* 412 * ata_reset_channel() will freeze 2 times, so 413 * unfreeze one time. Not a problem as we're at splbio 414 */ 415 chp->ch_queue->queue_freeze--; 416 ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags); 417 } else if (chp->ch_queue->active_xfer != NULL && 418 chp->ch_queue->queue_freeze == 1) { 419 /* 420 * Caller has bumped queue_freeze, decrease it. 421 */ 422 chp->ch_queue->queue_freeze--; 423 xfer = chp->ch_queue->active_xfer; 424 KASSERT(xfer != NULL); 425 (*xfer->c_start)(xfer->c_chp, xfer); 426 } else if (chp->ch_queue->queue_freeze > 1) 427 panic("ata_thread: queue_freeze"); 428 } 429 splx(s); 430 chp->ch_thread = NULL; 431 wakeup(&chp->ch_flags); 432 kthread_exit(0); 433 } 434 435 /* 436 * atabus_match: 437 * 438 * Autoconfiguration match routine. 439 */ 440 static int 441 atabus_match(device_t parent, cfdata_t cf, void *aux) 442 { 443 struct ata_channel *chp = aux; 444 445 if (chp == NULL) 446 return (0); 447 448 if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel && 449 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 450 return (0); 451 452 return (1); 453 } 454 455 /* 456 * atabus_attach: 457 * 458 * Autoconfiguration attach routine. 459 */ 460 static void 461 atabus_attach(device_t parent, device_t self, void *aux) 462 { 463 struct atabus_softc *sc = device_private(self); 464 struct ata_channel *chp = aux; 465 struct atabus_initq *initq; 466 int error; 467 468 sc->sc_chan = chp; 469 470 aprint_normal("\n"); 471 aprint_naive("\n"); 472 473 sc->sc_dev = self; 474 475 if (ata_addref(chp)) 476 return; 477 478 RUN_ONCE(&ata_init_ctrl, atabus_init); 479 480 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 481 initq->atabus_sc = sc; 482 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 483 config_pending_incr(); 484 485 if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc, 486 &chp->ch_thread, "%s", device_xname(self))) != 0) 487 aprint_error_dev(self, 488 "unable to create kernel thread: error %d\n", error); 489 490 if (!pmf_device_register(self, atabus_suspend, atabus_resume)) 491 aprint_error_dev(self, "couldn't establish power handler\n"); 492 } 493 494 /* 495 * atabus_detach: 496 * 497 * Autoconfiguration detach routine. 498 */ 499 static int 500 atabus_detach(device_t self, int flags) 501 { 502 struct atabus_softc *sc = device_private(self); 503 struct ata_channel *chp = sc->sc_chan; 504 device_t dev = NULL; 505 int s, i, error = 0; 506 507 /* Shutdown the channel. */ 508 s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */ 509 chp->ch_flags |= ATACH_SHUTDOWN; 510 splx(s); 511 512 wakeup(&chp->ch_thread); 513 514 while (chp->ch_thread != NULL) 515 (void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 516 517 518 /* 519 * Detach atapibus and its children. 520 */ 521 if ((dev = chp->atapibus) != NULL) { 522 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 523 device_xname(self), device_xname(dev)), DEBUG_DETACH); 524 525 error = config_detach(dev, flags); 526 if (error) 527 goto out; 528 KASSERT(chp->atapibus == NULL); 529 } 530 531 /* 532 * Detach our other children. 533 */ 534 for (i = 0; i < chp->ch_ndrive; i++) { 535 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 536 continue; 537 if ((dev = chp->ch_drive[i].drv_softc) != NULL) { 538 ATADEBUG_PRINT(("%s.%d: %s: detaching %s\n", __func__, 539 __LINE__, device_xname(self), device_xname(dev)), 540 DEBUG_DETACH); 541 error = config_detach(dev, flags); 542 if (error) 543 goto out; 544 KASSERT(chp->ch_drive[i].drv_softc == NULL); 545 KASSERT((chp->ch_drive[i].drive_flags & DRIVE) == 0); 546 } 547 } 548 549 out: 550 #ifdef ATADEBUG 551 if (dev != NULL && error != 0) 552 ATADEBUG_PRINT(("%s: %s: error %d detaching %s\n", __func__, 553 device_xname(self), error, device_xname(dev)), 554 DEBUG_DETACH); 555 #endif /* ATADEBUG */ 556 557 return (error); 558 } 559 560 void 561 atabus_childdetached(device_t self, device_t child) 562 { 563 bool found = false; 564 struct atabus_softc *sc = device_private(self); 565 struct ata_channel *chp = sc->sc_chan; 566 int i; 567 568 /* 569 * atapibus detached. 570 */ 571 if (child == chp->atapibus) { 572 chp->atapibus = NULL; 573 found = true; 574 } 575 576 /* 577 * Detach our other children. 578 */ 579 for (i = 0; i < chp->ch_ndrive; i++) { 580 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 581 continue; 582 if (child == chp->ch_drive[i].drv_softc) { 583 chp->ch_drive[i].drv_softc = NULL; 584 chp->ch_drive[i].drive_flags = 0; 585 found = true; 586 } 587 } 588 589 if (!found) 590 panic("%s: unknown child %p", device_xname(self), 591 (const void *)child); 592 } 593 594 CFATTACH_DECL3_NEW(atabus, sizeof(struct atabus_softc), 595 atabus_match, atabus_attach, atabus_detach, NULL, atabus_rescan, 596 atabus_childdetached, DVF_DETACH_SHUTDOWN); 597 598 /***************************************************************************** 599 * Common ATA bus operations. 600 *****************************************************************************/ 601 602 /* Get the disk's parameters */ 603 int 604 ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags, 605 struct ataparams *prms) 606 { 607 struct ata_command ata_c; 608 struct ata_channel *chp = drvp->chnl_softc; 609 struct atac_softc *atac = chp->ch_atac; 610 char *tb; 611 int i, rv; 612 u_int16_t *p; 613 614 ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS); 615 616 tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP); 617 memset(prms, 0, sizeof(struct ataparams)); 618 memset(&ata_c, 0, sizeof(struct ata_command)); 619 620 if (drvp->drive_flags & DRIVE_ATA) { 621 ata_c.r_command = WDCC_IDENTIFY; 622 ata_c.r_st_bmask = WDCS_DRDY; 623 ata_c.r_st_pmask = WDCS_DRQ; 624 ata_c.timeout = 3000; /* 3s */ 625 } else if (drvp->drive_flags & DRIVE_ATAPI) { 626 ata_c.r_command = ATAPI_IDENTIFY_DEVICE; 627 ata_c.r_st_bmask = 0; 628 ata_c.r_st_pmask = WDCS_DRQ; 629 ata_c.timeout = 10000; /* 10s */ 630 } else { 631 ATADEBUG_PRINT(("ata_get_parms: no disks\n"), 632 DEBUG_FUNCS|DEBUG_PROBE); 633 rv = CMD_ERR; 634 goto out; 635 } 636 ata_c.flags = AT_READ | flags; 637 ata_c.data = tb; 638 ata_c.bcount = DEV_BSIZE; 639 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 640 &ata_c) != ATACMD_COMPLETE) { 641 ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"), 642 DEBUG_FUNCS|DEBUG_PROBE); 643 rv = CMD_AGAIN; 644 goto out; 645 } 646 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 647 ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n", 648 ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE); 649 rv = CMD_ERR; 650 goto out; 651 } 652 /* if we didn't read any data something is wrong */ 653 if ((ata_c.flags & AT_XFDONE) == 0) { 654 rv = CMD_ERR; 655 goto out; 656 } 657 658 /* Read in parameter block. */ 659 memcpy(prms, tb, sizeof(struct ataparams)); 660 661 /* 662 * Shuffle string byte order. 663 * ATAPI NEC, Mitsumi and Pioneer drives and 664 * old ATA TDK CompactFlash cards 665 * have different byte order. 666 */ 667 #if BYTE_ORDER == BIG_ENDIAN 668 # define M(n) prms->atap_model[(n) ^ 1] 669 #else 670 # define M(n) prms->atap_model[n] 671 #endif 672 if ( 673 #if BYTE_ORDER == BIG_ENDIAN 674 ! 675 #endif 676 ((drvp->drive_flags & DRIVE_ATAPI) ? 677 ((M(0) == 'N' && M(1) == 'E') || 678 (M(0) == 'F' && M(1) == 'X') || 679 (M(0) == 'P' && M(1) == 'i')) : 680 ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) { 681 rv = CMD_OK; 682 goto out; 683 } 684 #undef M 685 for (i = 0; i < sizeof(prms->atap_model); i += 2) { 686 p = (u_int16_t *)(prms->atap_model + i); 687 *p = bswap16(*p); 688 } 689 for (i = 0; i < sizeof(prms->atap_serial); i += 2) { 690 p = (u_int16_t *)(prms->atap_serial + i); 691 *p = bswap16(*p); 692 } 693 for (i = 0; i < sizeof(prms->atap_revision); i += 2) { 694 p = (u_int16_t *)(prms->atap_revision + i); 695 *p = bswap16(*p); 696 } 697 698 rv = CMD_OK; 699 out: 700 kmem_free(tb, DEV_BSIZE); 701 return rv; 702 } 703 704 int 705 ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags) 706 { 707 struct ata_command ata_c; 708 struct ata_channel *chp = drvp->chnl_softc; 709 struct atac_softc *atac = chp->ch_atac; 710 711 ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS); 712 memset(&ata_c, 0, sizeof(struct ata_command)); 713 714 ata_c.r_command = SET_FEATURES; 715 ata_c.r_st_bmask = 0; 716 ata_c.r_st_pmask = 0; 717 ata_c.r_features = WDSF_SET_MODE; 718 ata_c.r_count = mode; 719 ata_c.flags = flags; 720 ata_c.timeout = 1000; /* 1s */ 721 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 722 &ata_c) != ATACMD_COMPLETE) 723 return CMD_AGAIN; 724 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 725 return CMD_ERR; 726 } 727 return CMD_OK; 728 } 729 730 #if NATA_DMA 731 void 732 ata_dmaerr(struct ata_drive_datas *drvp, int flags) 733 { 734 /* 735 * Downgrade decision: if we get NERRS_MAX in NXFER. 736 * We start with n_dmaerrs set to NERRS_MAX-1 so that the 737 * first error within the first NXFER ops will immediatly trigger 738 * a downgrade. 739 * If we got an error and n_xfers is bigger than NXFER reset counters. 740 */ 741 drvp->n_dmaerrs++; 742 if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) { 743 ata_downgrade_mode(drvp, flags); 744 drvp->n_dmaerrs = NERRS_MAX-1; 745 drvp->n_xfers = 0; 746 return; 747 } 748 if (drvp->n_xfers > NXFER) { 749 drvp->n_dmaerrs = 1; /* just got an error */ 750 drvp->n_xfers = 1; /* restart counting from this error */ 751 } 752 } 753 #endif /* NATA_DMA */ 754 755 /* 756 * freeze the queue and wait for the controller to be idle. Caller has to 757 * unfreeze/restart the queue 758 */ 759 void 760 ata_queue_idle(struct ata_queue *queue) 761 { 762 int s = splbio(); 763 queue->queue_freeze++; 764 while (queue->active_xfer != NULL) { 765 queue->queue_flags |= QF_IDLE_WAIT; 766 tsleep(&queue->queue_flags, PRIBIO, "qidl", 0); 767 } 768 splx(s); 769 } 770 771 /* 772 * Add a command to the queue and start controller. 773 * 774 * MUST BE CALLED AT splbio()! 775 */ 776 void 777 ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 778 { 779 780 ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer, 781 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 782 783 /* complete xfer setup */ 784 xfer->c_chp = chp; 785 786 /* insert at the end of command list */ 787 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 788 ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n", 789 chp->ch_flags), DEBUG_XFERS); 790 /* 791 * if polling and can sleep, wait for the xfer to be at head of queue 792 */ 793 if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) { 794 while (chp->ch_queue->active_xfer != NULL || 795 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) { 796 xfer->c_flags |= C_WAITACT; 797 tsleep(xfer, PRIBIO, "ataact", 0); 798 xfer->c_flags &= ~C_WAITACT; 799 if (xfer->c_flags & C_FREE) { 800 ata_free_xfer(chp, xfer); 801 return; 802 } 803 } 804 } 805 atastart(chp); 806 } 807 808 /* 809 * Start I/O on a controller, for the given channel. 810 * The first xfer may be not for our channel if the channel queues 811 * are shared. 812 * 813 * MUST BE CALLED AT splbio()! 814 */ 815 void 816 atastart(struct ata_channel *chp) 817 { 818 struct atac_softc *atac = chp->ch_atac; 819 struct ata_xfer *xfer; 820 821 #ifdef ATA_DEBUG 822 int spl1, spl2; 823 824 spl1 = splbio(); 825 spl2 = splbio(); 826 if (spl2 != spl1) { 827 printf("atastart: not at splbio()\n"); 828 panic("atastart"); 829 } 830 splx(spl2); 831 splx(spl1); 832 #endif /* ATA_DEBUG */ 833 834 /* is there a xfer ? */ 835 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 836 return; 837 838 /* adjust chp, in case we have a shared queue */ 839 chp = xfer->c_chp; 840 841 if (chp->ch_queue->active_xfer != NULL) { 842 return; /* channel aleady active */ 843 } 844 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 845 if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) { 846 chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT; 847 wakeup(&chp->ch_queue->queue_flags); 848 } 849 return; /* queue frozen */ 850 } 851 /* 852 * if someone is waiting for the command to be active, wake it up 853 * and let it process the command 854 */ 855 if (xfer->c_flags & C_WAITACT) { 856 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d " 857 "wait active\n", xfer, chp->ch_channel, xfer->c_drive), 858 DEBUG_XFERS); 859 wakeup(xfer); 860 return; 861 } 862 #ifdef DIAGNOSTIC 863 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) 864 panic("atastart: channel waiting for irq"); 865 #endif 866 if (atac->atac_claim_hw) 867 if (!(*atac->atac_claim_hw)(chp, 0)) 868 return; 869 870 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer, 871 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 872 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 873 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 874 chp->ch_drive[xfer->c_drive].state = 0; 875 } 876 chp->ch_queue->active_xfer = xfer; 877 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 878 879 if (atac->atac_cap & ATAC_CAP_NOIRQ) 880 KASSERT(xfer->c_flags & C_POLL); 881 882 xfer->c_start(chp, xfer); 883 } 884 885 struct ata_xfer * 886 ata_get_xfer(int flags) 887 { 888 struct ata_xfer *xfer; 889 int s; 890 891 s = splbio(); 892 xfer = pool_get(&ata_xfer_pool, 893 ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 894 splx(s); 895 if (xfer != NULL) { 896 memset(xfer, 0, sizeof(struct ata_xfer)); 897 } 898 return xfer; 899 } 900 901 void 902 ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 903 { 904 struct atac_softc *atac = chp->ch_atac; 905 int s; 906 907 if (xfer->c_flags & C_WAITACT) { 908 /* Someone is waiting for this xfer, so we can't free now */ 909 xfer->c_flags |= C_FREE; 910 wakeup(xfer); 911 return; 912 } 913 914 #if NATA_PIOBM /* XXX wdc dependent code */ 915 if (xfer->c_flags & C_PIOBM) { 916 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 917 918 /* finish the busmastering PIO */ 919 (*wdc->piobm_done)(wdc->dma_arg, 920 chp->ch_channel, xfer->c_drive); 921 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT); 922 } 923 #endif 924 925 if (atac->atac_free_hw) 926 (*atac->atac_free_hw)(chp); 927 s = splbio(); 928 pool_put(&ata_xfer_pool, xfer); 929 splx(s); 930 } 931 932 /* 933 * Kill off all pending xfers for a ata_channel. 934 * 935 * Must be called at splbio(). 936 */ 937 void 938 ata_kill_pending(struct ata_drive_datas *drvp) 939 { 940 struct ata_channel *chp = drvp->chnl_softc; 941 struct ata_xfer *xfer, *next_xfer; 942 int s = splbio(); 943 944 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 945 xfer != NULL; xfer = next_xfer) { 946 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 947 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 948 continue; 949 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 950 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 951 } 952 953 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 954 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 955 drvp->drive_flags |= DRIVE_WAITDRAIN; 956 (void) tsleep(&chp->ch_queue->active_xfer, 957 PRIBIO, "atdrn", 0); 958 } else { 959 /* no more xfer for us */ 960 break; 961 } 962 } 963 splx(s); 964 } 965 966 /* 967 * ata_reset_channel: 968 * 969 * Reset and ATA channel. 970 * 971 * MUST BE CALLED AT splbio()! 972 */ 973 void 974 ata_reset_channel(struct ata_channel *chp, int flags) 975 { 976 struct atac_softc *atac = chp->ch_atac; 977 int drive; 978 979 #ifdef ATA_DEBUG 980 int spl1, spl2; 981 982 spl1 = splbio(); 983 spl2 = splbio(); 984 if (spl2 != spl1) { 985 printf("ata_reset_channel: not at splbio()\n"); 986 panic("ata_reset_channel"); 987 } 988 splx(spl2); 989 splx(spl1); 990 #endif /* ATA_DEBUG */ 991 992 chp->ch_queue->queue_freeze++; 993 994 /* 995 * If we can poll or wait it's OK, otherwise wake up the 996 * kernel thread to do it for us. 997 */ 998 ATADEBUG_PRINT(("ata_reset_channel flags 0x%x ch_flags 0x%x\n", 999 flags, chp->ch_flags), DEBUG_FUNCS | DEBUG_XFERS); 1000 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 1001 if (chp->ch_flags & ATACH_TH_RESET) { 1002 /* No need to schedule a reset more than one time. */ 1003 chp->ch_queue->queue_freeze--; 1004 return; 1005 } 1006 chp->ch_flags |= ATACH_TH_RESET; 1007 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 1008 wakeup(&chp->ch_thread); 1009 return; 1010 } 1011 1012 (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags); 1013 1014 for (drive = 0; drive < chp->ch_ndrive; drive++) 1015 chp->ch_drive[drive].state = 0; 1016 1017 chp->ch_flags &= ~ATACH_TH_RESET; 1018 if ((flags & AT_RST_EMERG) == 0) { 1019 chp->ch_queue->queue_freeze--; 1020 atastart(chp); 1021 } else { 1022 /* make sure that we can use polled commands */ 1023 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1024 chp->ch_queue->queue_freeze = 0; 1025 chp->ch_queue->active_xfer = NULL; 1026 } 1027 } 1028 1029 int 1030 ata_addref(struct ata_channel *chp) 1031 { 1032 struct atac_softc *atac = chp->ch_atac; 1033 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1034 int s, error = 0; 1035 1036 s = splbio(); 1037 if (adapt->adapt_refcnt++ == 0 && 1038 adapt->adapt_enable != NULL) { 1039 error = (*adapt->adapt_enable)(atac->atac_dev, 1); 1040 if (error) 1041 adapt->adapt_refcnt--; 1042 } 1043 splx(s); 1044 return (error); 1045 } 1046 1047 void 1048 ata_delref(struct ata_channel *chp) 1049 { 1050 struct atac_softc *atac = chp->ch_atac; 1051 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1052 int s; 1053 1054 s = splbio(); 1055 if (adapt->adapt_refcnt-- == 1 && 1056 adapt->adapt_enable != NULL) 1057 (void) (*adapt->adapt_enable)(atac->atac_dev, 0); 1058 splx(s); 1059 } 1060 1061 void 1062 ata_print_modes(struct ata_channel *chp) 1063 { 1064 struct atac_softc *atac = chp->ch_atac; 1065 int drive; 1066 struct ata_drive_datas *drvp; 1067 1068 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1069 drvp = &chp->ch_drive[drive]; 1070 if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL) 1071 continue; 1072 aprint_verbose("%s(%s:%d:%d): using PIO mode %d", 1073 device_xname(drvp->drv_softc), 1074 device_xname(atac->atac_dev), 1075 chp->ch_channel, drvp->drive, drvp->PIO_mode); 1076 #if NATA_DMA 1077 if (drvp->drive_flags & DRIVE_DMA) 1078 aprint_verbose(", DMA mode %d", drvp->DMA_mode); 1079 #if NATA_UDMA 1080 if (drvp->drive_flags & DRIVE_UDMA) { 1081 aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode); 1082 if (drvp->UDMA_mode == 2) 1083 aprint_verbose(" (Ultra/33)"); 1084 else if (drvp->UDMA_mode == 4) 1085 aprint_verbose(" (Ultra/66)"); 1086 else if (drvp->UDMA_mode == 5) 1087 aprint_verbose(" (Ultra/100)"); 1088 else if (drvp->UDMA_mode == 6) 1089 aprint_verbose(" (Ultra/133)"); 1090 } 1091 #endif /* NATA_UDMA */ 1092 #endif /* NATA_DMA */ 1093 #if NATA_DMA || NATA_PIOBM 1094 if (0 1095 #if NATA_DMA 1096 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1097 #endif 1098 #if NATA_PIOBM 1099 /* PIOBM capable controllers use DMA for PIO commands */ 1100 || (atac->atac_cap & ATAC_CAP_PIOBM) 1101 #endif 1102 ) 1103 aprint_verbose(" (using DMA)"); 1104 #endif /* NATA_DMA || NATA_PIOBM */ 1105 aprint_verbose("\n"); 1106 } 1107 } 1108 1109 #if NATA_DMA 1110 /* 1111 * downgrade the transfer mode of a drive after an error. return 1 if 1112 * downgrade was possible, 0 otherwise. 1113 * 1114 * MUST BE CALLED AT splbio()! 1115 */ 1116 int 1117 ata_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1118 { 1119 struct ata_channel *chp = drvp->chnl_softc; 1120 struct atac_softc *atac = chp->ch_atac; 1121 device_t drv_dev = drvp->drv_softc; 1122 int cf_flags = device_cfdata(drv_dev)->cf_flags; 1123 1124 /* if drive or controller don't know its mode, we can't do much */ 1125 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1126 (atac->atac_set_modes == NULL)) 1127 return 0; 1128 /* current drive mode was set by a config flag, let it this way */ 1129 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1130 (cf_flags & ATA_CONFIG_DMA_SET) || 1131 (cf_flags & ATA_CONFIG_UDMA_SET)) 1132 return 0; 1133 1134 #if NATA_UDMA 1135 /* 1136 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1137 */ 1138 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1139 drvp->UDMA_mode--; 1140 aprint_error_dev(drv_dev, 1141 "transfer error, downgrading to Ultra-DMA mode %d\n", 1142 drvp->UDMA_mode); 1143 } 1144 #endif 1145 1146 /* 1147 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1148 */ 1149 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1150 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1151 drvp->PIO_mode = drvp->PIO_cap; 1152 aprint_error_dev(drv_dev, 1153 "transfer error, downgrading to PIO mode %d\n", 1154 drvp->PIO_mode); 1155 } else /* already using PIO, can't downgrade */ 1156 return 0; 1157 1158 (*atac->atac_set_modes)(chp); 1159 ata_print_modes(chp); 1160 /* reset the channel, which will schedule all drives for setup */ 1161 ata_reset_channel(chp, flags | AT_RST_NOCMD); 1162 return 1; 1163 } 1164 #endif /* NATA_DMA */ 1165 1166 /* 1167 * Probe drive's capabilities, for use by the controller later 1168 * Assumes drvp points to an existing drive. 1169 */ 1170 void 1171 ata_probe_caps(struct ata_drive_datas *drvp) 1172 { 1173 struct ataparams params, params2; 1174 struct ata_channel *chp = drvp->chnl_softc; 1175 struct atac_softc *atac = chp->ch_atac; 1176 device_t drv_dev = drvp->drv_softc; 1177 int i, printed, s; 1178 const char *sep = ""; 1179 int cf_flags; 1180 1181 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1182 /* IDENTIFY failed. Can't tell more about the device */ 1183 return; 1184 } 1185 if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == 1186 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 1187 /* 1188 * Controller claims 16 and 32 bit transfers. 1189 * Re-do an IDENTIFY with 32-bit transfers, 1190 * and compare results. 1191 */ 1192 s = splbio(); 1193 drvp->drive_flags |= DRIVE_CAP32; 1194 splx(s); 1195 ata_get_params(drvp, AT_WAIT, ¶ms2); 1196 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1197 /* Not good. fall back to 16bits */ 1198 s = splbio(); 1199 drvp->drive_flags &= ~DRIVE_CAP32; 1200 splx(s); 1201 } else { 1202 aprint_verbose_dev(drv_dev, "32-bit data port\n"); 1203 } 1204 } 1205 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1206 if (params.atap_ata_major > 0x01 && 1207 params.atap_ata_major != 0xffff) { 1208 for (i = 14; i > 0; i--) { 1209 if (params.atap_ata_major & (1 << i)) { 1210 aprint_verbose_dev(drv_dev, 1211 "ATA version %d\n", i); 1212 drvp->ata_vers = i; 1213 break; 1214 } 1215 } 1216 } 1217 #endif 1218 1219 /* An ATAPI device is at last PIO mode 3 */ 1220 if (drvp->drive_flags & DRIVE_ATAPI) 1221 drvp->PIO_mode = 3; 1222 1223 /* 1224 * It's not in the specs, but it seems that some drive 1225 * returns 0xffff in atap_extensions when this field is invalid 1226 */ 1227 if (params.atap_extensions != 0xffff && 1228 (params.atap_extensions & WDC_EXT_MODES)) { 1229 printed = 0; 1230 /* 1231 * XXX some drives report something wrong here (they claim to 1232 * support PIO mode 8 !). As mode is coded on 3 bits in 1233 * SET FEATURE, limit it to 7 (so limit i to 4). 1234 * If higher mode than 7 is found, abort. 1235 */ 1236 for (i = 7; i >= 0; i--) { 1237 if ((params.atap_piomode_supp & (1 << i)) == 0) 1238 continue; 1239 if (i > 4) 1240 return; 1241 /* 1242 * See if mode is accepted. 1243 * If the controller can't set its PIO mode, 1244 * assume the defaults are good, so don't try 1245 * to set it 1246 */ 1247 if (atac->atac_set_modes) 1248 /* 1249 * It's OK to pool here, it's fast enough 1250 * to not bother waiting for interrupt 1251 */ 1252 if (ata_set_mode(drvp, 0x08 | (i + 3), 1253 AT_WAIT) != CMD_OK) 1254 continue; 1255 if (!printed) { 1256 aprint_verbose_dev(drv_dev, 1257 "drive supports PIO mode %d", i + 3); 1258 sep = ","; 1259 printed = 1; 1260 } 1261 /* 1262 * If controller's driver can't set its PIO mode, 1263 * get the highter one for the drive. 1264 */ 1265 if (atac->atac_set_modes == NULL || 1266 atac->atac_pio_cap >= i + 3) { 1267 drvp->PIO_mode = i + 3; 1268 drvp->PIO_cap = i + 3; 1269 break; 1270 } 1271 } 1272 if (!printed) { 1273 /* 1274 * We didn't find a valid PIO mode. 1275 * Assume the values returned for DMA are buggy too 1276 */ 1277 return; 1278 } 1279 s = splbio(); 1280 drvp->drive_flags |= DRIVE_MODE; 1281 splx(s); 1282 printed = 0; 1283 for (i = 7; i >= 0; i--) { 1284 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1285 continue; 1286 #if NATA_DMA 1287 if ((atac->atac_cap & ATAC_CAP_DMA) && 1288 atac->atac_set_modes != NULL) 1289 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1290 != CMD_OK) 1291 continue; 1292 #endif 1293 if (!printed) { 1294 aprint_verbose("%s DMA mode %d", sep, i); 1295 sep = ","; 1296 printed = 1; 1297 } 1298 #if NATA_DMA 1299 if (atac->atac_cap & ATAC_CAP_DMA) { 1300 if (atac->atac_set_modes != NULL && 1301 atac->atac_dma_cap < i) 1302 continue; 1303 drvp->DMA_mode = i; 1304 drvp->DMA_cap = i; 1305 s = splbio(); 1306 drvp->drive_flags |= DRIVE_DMA; 1307 splx(s); 1308 } 1309 #endif 1310 break; 1311 } 1312 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1313 printed = 0; 1314 for (i = 7; i >= 0; i--) { 1315 if ((params.atap_udmamode_supp & (1 << i)) 1316 == 0) 1317 continue; 1318 #if NATA_UDMA 1319 if (atac->atac_set_modes != NULL && 1320 (atac->atac_cap & ATAC_CAP_UDMA)) 1321 if (ata_set_mode(drvp, 0x40 | i, 1322 AT_WAIT) != CMD_OK) 1323 continue; 1324 #endif 1325 if (!printed) { 1326 aprint_verbose("%s Ultra-DMA mode %d", 1327 sep, i); 1328 if (i == 2) 1329 aprint_verbose(" (Ultra/33)"); 1330 else if (i == 4) 1331 aprint_verbose(" (Ultra/66)"); 1332 else if (i == 5) 1333 aprint_verbose(" (Ultra/100)"); 1334 else if (i == 6) 1335 aprint_verbose(" (Ultra/133)"); 1336 sep = ","; 1337 printed = 1; 1338 } 1339 #if NATA_UDMA 1340 if (atac->atac_cap & ATAC_CAP_UDMA) { 1341 if (atac->atac_set_modes != NULL && 1342 atac->atac_udma_cap < i) 1343 continue; 1344 drvp->UDMA_mode = i; 1345 drvp->UDMA_cap = i; 1346 s = splbio(); 1347 drvp->drive_flags |= DRIVE_UDMA; 1348 splx(s); 1349 } 1350 #endif 1351 break; 1352 } 1353 } 1354 aprint_verbose("\n"); 1355 } 1356 1357 s = splbio(); 1358 drvp->drive_flags &= ~DRIVE_NOSTREAM; 1359 if (drvp->drive_flags & DRIVE_ATAPI) { 1360 if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM) 1361 drvp->drive_flags |= DRIVE_NOSTREAM; 1362 } else { 1363 if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM) 1364 drvp->drive_flags |= DRIVE_NOSTREAM; 1365 } 1366 splx(s); 1367 1368 /* Try to guess ATA version here, if it didn't get reported */ 1369 if (drvp->ata_vers == 0) { 1370 #if NATA_UDMA 1371 if (drvp->drive_flags & DRIVE_UDMA) 1372 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1373 else 1374 #endif 1375 if (drvp->PIO_cap > 2) 1376 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1377 } 1378 cf_flags = device_cfdata(drv_dev)->cf_flags; 1379 if (cf_flags & ATA_CONFIG_PIO_SET) { 1380 s = splbio(); 1381 drvp->PIO_mode = 1382 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1383 drvp->drive_flags |= DRIVE_MODE; 1384 splx(s); 1385 } 1386 #if NATA_DMA 1387 if ((atac->atac_cap & ATAC_CAP_DMA) == 0) { 1388 /* don't care about DMA modes */ 1389 return; 1390 } 1391 if (cf_flags & ATA_CONFIG_DMA_SET) { 1392 s = splbio(); 1393 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1394 ATA_CONFIG_DMA_DISABLE) { 1395 drvp->drive_flags &= ~DRIVE_DMA; 1396 } else { 1397 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1398 ATA_CONFIG_DMA_OFF; 1399 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1400 } 1401 splx(s); 1402 } 1403 #if NATA_UDMA 1404 if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) { 1405 /* don't care about UDMA modes */ 1406 return; 1407 } 1408 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1409 s = splbio(); 1410 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1411 ATA_CONFIG_UDMA_DISABLE) { 1412 drvp->drive_flags &= ~DRIVE_UDMA; 1413 } else { 1414 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1415 ATA_CONFIG_UDMA_OFF; 1416 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1417 } 1418 splx(s); 1419 } 1420 #endif /* NATA_UDMA */ 1421 #endif /* NATA_DMA */ 1422 } 1423 1424 /* management of the /dev/atabus* devices */ 1425 int 1426 atabusopen(dev_t dev, int flag, int fmt, struct lwp *l) 1427 { 1428 struct atabus_softc *sc; 1429 int error; 1430 1431 sc = device_lookup_private(&atabus_cd, minor(dev)); 1432 if (sc == NULL) 1433 return (ENXIO); 1434 1435 if (sc->sc_flags & ATABUSCF_OPEN) 1436 return (EBUSY); 1437 1438 if ((error = ata_addref(sc->sc_chan)) != 0) 1439 return (error); 1440 1441 sc->sc_flags |= ATABUSCF_OPEN; 1442 1443 return (0); 1444 } 1445 1446 1447 int 1448 atabusclose(dev_t dev, int flag, int fmt, struct lwp *l) 1449 { 1450 struct atabus_softc *sc = 1451 device_lookup_private(&atabus_cd, minor(dev)); 1452 1453 ata_delref(sc->sc_chan); 1454 1455 sc->sc_flags &= ~ATABUSCF_OPEN; 1456 1457 return (0); 1458 } 1459 1460 int 1461 atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, struct lwp *l) 1462 { 1463 struct atabus_softc *sc = 1464 device_lookup_private(&atabus_cd, minor(dev)); 1465 struct ata_channel *chp = sc->sc_chan; 1466 int min_drive, max_drive, drive; 1467 int error; 1468 int s; 1469 1470 /* 1471 * Enforce write permission for ioctls that change the 1472 * state of the bus. Host adapter specific ioctls must 1473 * be checked by the adapter driver. 1474 */ 1475 switch (cmd) { 1476 case ATABUSIOSCAN: 1477 case ATABUSIODETACH: 1478 case ATABUSIORESET: 1479 if ((flag & FWRITE) == 0) 1480 return (EBADF); 1481 } 1482 1483 switch (cmd) { 1484 case ATABUSIORESET: 1485 s = splbio(); 1486 ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL); 1487 splx(s); 1488 return 0; 1489 case ATABUSIOSCAN: 1490 { 1491 #if 0 1492 struct atabusioscan_args *a= 1493 (struct atabusioscan_args *)addr; 1494 #endif 1495 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1496 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1497 return (EOPNOTSUPP); 1498 return (EOPNOTSUPP); 1499 } 1500 case ATABUSIODETACH: 1501 { 1502 struct atabusiodetach_args *a= 1503 (struct atabusiodetach_args *)addr; 1504 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1505 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1506 return (EOPNOTSUPP); 1507 switch (a->at_dev) { 1508 case -1: 1509 min_drive = 0; 1510 max_drive = 1; 1511 break; 1512 case 0: 1513 case 1: 1514 min_drive = max_drive = a->at_dev; 1515 break; 1516 default: 1517 return (EINVAL); 1518 } 1519 for (drive = min_drive; drive <= max_drive; drive++) { 1520 if (chp->ch_drive[drive].drv_softc != NULL) { 1521 error = config_detach( 1522 chp->ch_drive[drive].drv_softc, 0); 1523 if (error) 1524 return (error); 1525 KASSERT(chp->ch_drive[drive].drv_softc == NULL); 1526 } 1527 } 1528 return 0; 1529 } 1530 default: 1531 return ENOTTY; 1532 } 1533 } 1534 1535 static bool 1536 atabus_suspend(device_t dv, const pmf_qual_t *qual) 1537 { 1538 struct atabus_softc *sc = device_private(dv); 1539 struct ata_channel *chp = sc->sc_chan; 1540 1541 ata_queue_idle(chp->ch_queue); 1542 1543 return true; 1544 } 1545 1546 static bool 1547 atabus_resume(device_t dv, const pmf_qual_t *qual) 1548 { 1549 struct atabus_softc *sc = device_private(dv); 1550 struct ata_channel *chp = sc->sc_chan; 1551 int s; 1552 1553 /* 1554 * XXX joerg: with wdc, the first channel unfreezes the controler. 1555 * Move this the reset and queue idling into wdc. 1556 */ 1557 s = splbio(); 1558 if (chp->ch_queue->queue_freeze == 0) { 1559 splx(s); 1560 return true; 1561 } 1562 KASSERT(chp->ch_queue->queue_freeze > 0); 1563 /* unfreeze the queue and reset drives */ 1564 chp->ch_queue->queue_freeze--; 1565 ata_reset_channel(chp, AT_WAIT); 1566 splx(s); 1567 1568 return true; 1569 } 1570 1571 static int 1572 atabus_rescan(device_t self, const char *ifattr, const int *locators) 1573 { 1574 struct atabus_softc *sc = device_private(self); 1575 struct ata_channel *chp = sc->sc_chan; 1576 struct atabus_initq *initq; 1577 int i; 1578 int s; 1579 1580 if (chp->atapibus != NULL) { 1581 return EBUSY; 1582 } 1583 1584 for (i = 0; i < ATA_MAXDRIVES; i++) { 1585 if (chp->ch_drive[i].drv_softc != NULL) { 1586 return EBUSY; 1587 } 1588 } 1589 1590 s = splbio(); 1591 for (i = 0; i < ATA_MAXDRIVES; i++) { 1592 chp->ch_drive[i].drive_flags = 0; 1593 } 1594 splx(s); 1595 1596 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 1597 initq->atabus_sc = sc; 1598 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 1599 config_pending_incr(); 1600 1601 chp->ch_flags |= ATACH_TH_RESCAN; 1602 wakeup(&chp->ch_thread); 1603 1604 return 0; 1605 } 1606
Indexes created Fri Sep 26 20:09:58 GMT 2025