ata.c revision 1.90
1 /* $NetBSD: ata.c,v 1.90 2007/07/09 21:00:30 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.90 2007/07/09 21:00:30 ad Exp $"); 34 35 #include "opt_ata.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/fcntl.h> 44 #include <sys/proc.h> 45 #include <sys/pool.h> 46 #include <sys/kthread.h> 47 #include <sys/errno.h> 48 #include <sys/ataio.h> 49 50 #include <machine/intr.h> 51 #include <machine/bus.h> 52 53 #include <dev/ata/ataconf.h> 54 #include <dev/ata/atareg.h> 55 #include <dev/ata/atavar.h> 56 #include <dev/ic/wdcvar.h> /* for PIOBM */ 57 58 #include "locators.h" 59 60 #include "atapibus.h" 61 #include "ataraid.h" 62 63 #if NATARAID > 0 64 #include <dev/ata/ata_raidvar.h> 65 #endif 66 67 #define DEBUG_FUNCS 0x08 68 #define DEBUG_PROBE 0x10 69 #define DEBUG_DETACH 0x20 70 #define DEBUG_XFERS 0x40 71 #ifdef ATADEBUG 72 int atadebug_mask = 0; 73 #define ATADEBUG_PRINT(args, level) \ 74 if (atadebug_mask & (level)) \ 75 printf args 76 #else 77 #define ATADEBUG_PRINT(args, level) 78 #endif 79 80 POOL_INIT(ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, "ataspl", NULL, 81 IPL_BIO); 82 83 /* 84 * A queue of atabus instances, used to ensure the same bus probe order 85 * for a given hardware configuration at each boot. 86 */ 87 struct atabus_initq_head atabus_initq_head = 88 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 89 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 90 91 /***************************************************************************** 92 * ATA bus layer. 93 * 94 * ATA controllers attach an atabus instance, which handles probing the bus 95 * for drives, etc. 96 *****************************************************************************/ 97 98 dev_type_open(atabusopen); 99 dev_type_close(atabusclose); 100 dev_type_ioctl(atabusioctl); 101 102 const struct cdevsw atabus_cdevsw = { 103 atabusopen, atabusclose, noread, nowrite, atabusioctl, 104 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 105 }; 106 107 extern struct cfdriver atabus_cd; 108 109 static void atabus_powerhook(int, void *); 110 111 /* 112 * atabusprint: 113 * 114 * Autoconfiguration print routine used by ATA controllers when 115 * attaching an atabus instance. 116 */ 117 int 118 atabusprint(void *aux, const char *pnp) 119 { 120 struct ata_channel *chan = aux; 121 122 if (pnp) 123 aprint_normal("atabus at %s", pnp); 124 aprint_normal(" channel %d", chan->ch_channel); 125 126 return (UNCONF); 127 } 128 129 /* 130 * ataprint: 131 * 132 * Autoconfiguration print routine. 133 */ 134 int 135 ataprint(void *aux, const char *pnp) 136 { 137 struct ata_device *adev = aux; 138 139 if (pnp) 140 aprint_normal("wd at %s", pnp); 141 aprint_normal(" drive %d", adev->adev_drv_data->drive); 142 143 return (UNCONF); 144 } 145 146 /* 147 * ata_channel_attach: 148 * 149 * Common parts of attaching an atabus to an ATA controller channel. 150 */ 151 void 152 ata_channel_attach(struct ata_channel *chp) 153 { 154 155 if (chp->ch_flags & ATACH_DISABLED) 156 return; 157 158 callout_init(&chp->ch_callout, 0); 159 160 TAILQ_INIT(&chp->ch_queue->queue_xfer); 161 chp->ch_queue->queue_freeze = 0; 162 chp->ch_queue->queue_flags = 0; 163 chp->ch_queue->active_xfer = NULL; 164 165 chp->atabus = config_found_ia(&chp->ch_atac->atac_dev, "ata", chp, 166 atabusprint); 167 } 168 169 static void 170 atabusconfig(struct atabus_softc *atabus_sc) 171 { 172 struct ata_channel *chp = atabus_sc->sc_chan; 173 struct atac_softc *atac = chp->ch_atac; 174 int i, s; 175 struct atabus_initq *atabus_initq = NULL; 176 177 /* Probe for the drives. */ 178 /* XXX for SATA devices we will power up all drives at once */ 179 (*atac->atac_probe)(chp); 180 181 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 182 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 183 DEBUG_PROBE); 184 185 /* If no drives, abort here */ 186 for (i = 0; i < chp->ch_ndrive; i++) 187 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 188 break; 189 if (i == chp->ch_ndrive) 190 goto out; 191 192 /* Shortcut in case we've been shutdown */ 193 if (chp->ch_flags & ATACH_SHUTDOWN) 194 goto out; 195 196 /* Make sure the devices probe in atabus order to avoid jitter. */ 197 simple_lock(&atabus_interlock); 198 while(1) { 199 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 200 if (atabus_initq->atabus_sc == atabus_sc) 201 break; 202 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 203 &atabus_interlock); 204 } 205 simple_unlock(&atabus_interlock); 206 207 /* 208 * Attach an ATAPI bus, if needed. 209 */ 210 for (i = 0; i < chp->ch_ndrive; i++) { 211 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 212 #if NATAPIBUS > 0 213 (*atac->atac_atapibus_attach)(atabus_sc); 214 #else 215 /* 216 * Fake the autoconfig "not configured" message 217 */ 218 aprint_normal("atapibus at %s not configured\n", 219 atac->atac_dev.dv_xname); 220 chp->atapibus = NULL; 221 s = splbio(); 222 for (i = 0; i < chp->ch_ndrive; i++) 223 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 224 splx(s); 225 #endif 226 break; 227 } 228 } 229 230 for (i = 0; i < chp->ch_ndrive; i++) { 231 struct ata_device adev; 232 if ((chp->ch_drive[i].drive_flags & 233 (DRIVE_ATA | DRIVE_OLD)) == 0) { 234 continue; 235 } 236 memset(&adev, 0, sizeof(struct ata_device)); 237 adev.adev_bustype = atac->atac_bustype_ata; 238 adev.adev_channel = chp->ch_channel; 239 adev.adev_openings = 1; 240 adev.adev_drv_data = &chp->ch_drive[i]; 241 chp->ata_drives[i] = config_found_ia(&atabus_sc->sc_dev, 242 "ata_hl", &adev, ataprint); 243 if (chp->ata_drives[i] != NULL) 244 ata_probe_caps(&chp->ch_drive[i]); 245 else { 246 s = splbio(); 247 chp->ch_drive[i].drive_flags &= 248 ~(DRIVE_ATA | DRIVE_OLD); 249 splx(s); 250 } 251 } 252 253 /* now that we know the drives, the controller can set its modes */ 254 if (atac->atac_set_modes) { 255 (*atac->atac_set_modes)(chp); 256 ata_print_modes(chp); 257 } 258 #if NATARAID > 0 259 if (atac->atac_cap & ATAC_CAP_RAID) 260 for (i = 0; i < chp->ch_ndrive; i++) 261 if (chp->ata_drives[i] != NULL) 262 ata_raid_check_component(chp->ata_drives[i]); 263 #endif /* NATARAID > 0 */ 264 265 /* 266 * reset drive_flags for unattached devices, reset state for attached 267 * ones 268 */ 269 s = splbio(); 270 for (i = 0; i < chp->ch_ndrive; i++) { 271 if (chp->ch_drive[i].drv_softc == NULL) 272 chp->ch_drive[i].drive_flags = 0; 273 else 274 chp->ch_drive[i].state = 0; 275 } 276 splx(s); 277 278 out: 279 if (atabus_initq == NULL) { 280 simple_lock(&atabus_interlock); 281 while(1) { 282 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 283 if (atabus_initq->atabus_sc == atabus_sc) 284 break; 285 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 286 &atabus_interlock); 287 } 288 simple_unlock(&atabus_interlock); 289 } 290 simple_lock(&atabus_interlock); 291 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 292 simple_unlock(&atabus_interlock); 293 294 free(atabus_initq, M_DEVBUF); 295 wakeup(&atabus_initq_head); 296 297 ata_delref(chp); 298 299 config_pending_decr(); 300 } 301 302 /* 303 * atabus_thread: 304 * 305 * Worker thread for the ATA bus. 306 */ 307 static void 308 atabus_thread(void *arg) 309 { 310 struct atabus_softc *sc = arg; 311 struct ata_channel *chp = sc->sc_chan; 312 struct ata_xfer *xfer; 313 int i, s; 314 315 s = splbio(); 316 chp->ch_flags |= ATACH_TH_RUN; 317 318 /* 319 * Probe the drives. Reset all flags to 0 to indicate to controllers 320 * that can re-probe that all drives must be probed.. 321 * 322 * Note: ch_ndrive may be changed during the probe. 323 */ 324 for (i = 0; i < ATA_MAXDRIVES; i++) 325 chp->ch_drive[i].drive_flags = 0; 326 splx(s); 327 328 /* Configure the devices on the bus. */ 329 atabusconfig(sc); 330 331 s = splbio(); 332 for (;;) { 333 if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 && 334 (chp->ch_queue->active_xfer == NULL || 335 chp->ch_queue->queue_freeze == 0)) { 336 chp->ch_flags &= ~ATACH_TH_RUN; 337 (void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0); 338 chp->ch_flags |= ATACH_TH_RUN; 339 } 340 if (chp->ch_flags & ATACH_SHUTDOWN) { 341 break; 342 } 343 if (chp->ch_flags & ATACH_TH_RESET) { 344 /* 345 * ata_reset_channel() will freeze 2 times, so 346 * unfreeze one time. Not a problem as we're at splbio 347 */ 348 chp->ch_queue->queue_freeze--; 349 ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags); 350 } else if (chp->ch_queue->active_xfer != NULL && 351 chp->ch_queue->queue_freeze == 1) { 352 /* 353 * Caller has bumped queue_freeze, decrease it. 354 */ 355 chp->ch_queue->queue_freeze--; 356 xfer = chp->ch_queue->active_xfer; 357 KASSERT(xfer != NULL); 358 (*xfer->c_start)(xfer->c_chp, xfer); 359 } else if (chp->ch_queue->queue_freeze > 1) 360 panic("ata_thread: queue_freeze"); 361 } 362 splx(s); 363 chp->ch_thread = NULL; 364 wakeup(&chp->ch_flags); 365 kthread_exit(0); 366 } 367 368 /* 369 * atabus_match: 370 * 371 * Autoconfiguration match routine. 372 */ 373 static int 374 atabus_match(struct device *parent, struct cfdata *cf, void *aux) 375 { 376 struct ata_channel *chp = aux; 377 378 if (chp == NULL) 379 return (0); 380 381 if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel && 382 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 383 return (0); 384 385 return (1); 386 } 387 388 /* 389 * atabus_attach: 390 * 391 * Autoconfiguration attach routine. 392 */ 393 static void 394 atabus_attach(struct device *parent, struct device *self, void *aux) 395 { 396 struct atabus_softc *sc = (void *) self; 397 struct ata_channel *chp = aux; 398 struct atabus_initq *initq; 399 int error; 400 401 sc->sc_chan = chp; 402 403 aprint_normal("\n"); 404 aprint_naive("\n"); 405 406 if (ata_addref(chp)) 407 return; 408 409 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 410 initq->atabus_sc = sc; 411 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 412 config_pending_incr(); 413 414 if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc, 415 &chp->ch_thread, "%s", sc->sc_dev.dv_xname)) != 0) 416 aprint_error("%s: unable to create kernel thread: error %d\n", 417 sc->sc_dev.dv_xname, error); 418 419 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 420 atabus_powerhook, sc); 421 if (sc->sc_powerhook == NULL) 422 printf("%s: WARNING: unable to establish power hook\n", 423 sc->sc_dev.dv_xname); 424 } 425 426 /* 427 * atabus_activate: 428 * 429 * Autoconfiguration activation routine. 430 */ 431 static int 432 atabus_activate(struct device *self, enum devact act) 433 { 434 struct atabus_softc *sc = (void *) self; 435 struct ata_channel *chp = sc->sc_chan; 436 struct device *dev = NULL; 437 int s, i, error = 0; 438 439 s = splbio(); 440 switch (act) { 441 case DVACT_ACTIVATE: 442 error = EOPNOTSUPP; 443 break; 444 445 case DVACT_DEACTIVATE: 446 /* 447 * We might deactivate the children of atapibus twice 448 * (once bia atapibus, once directly), but since the 449 * generic autoconfiguration code maintains the DVF_ACTIVE 450 * flag, it's safe. 451 */ 452 if ((dev = chp->atapibus) != NULL) { 453 error = config_deactivate(dev); 454 if (error) 455 goto out; 456 } 457 458 for (i = 0; i < chp->ch_ndrive; i++) { 459 if ((dev = chp->ch_drive[i].drv_softc) != NULL) { 460 ATADEBUG_PRINT(("atabus_activate: %s: " 461 "deactivating %s\n", sc->sc_dev.dv_xname, 462 dev->dv_xname), 463 DEBUG_DETACH); 464 error = config_deactivate(dev); 465 if (error) 466 goto out; 467 } 468 } 469 break; 470 } 471 out: 472 splx(s); 473 474 #ifdef ATADEBUG 475 if (dev != NULL && error != 0) 476 ATADEBUG_PRINT(("atabus_activate: %s: " 477 "error %d deactivating %s\n", sc->sc_dev.dv_xname, 478 error, dev->dv_xname), DEBUG_DETACH); 479 #endif /* ATADEBUG */ 480 481 return (error); 482 } 483 484 /* 485 * atabus_detach: 486 * 487 * Autoconfiguration detach routine. 488 */ 489 static int 490 atabus_detach(struct device *self, int flags) 491 { 492 struct atabus_softc *sc = (void *) self; 493 struct ata_channel *chp = sc->sc_chan; 494 struct device *dev = NULL; 495 int s, i, error = 0; 496 497 /* Shutdown the channel. */ 498 s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */ 499 chp->ch_flags |= ATACH_SHUTDOWN; 500 splx(s); 501 wakeup(&chp->ch_thread); 502 while (chp->ch_thread != NULL) 503 (void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 504 505 /* power hook */ 506 if (sc->sc_powerhook) 507 powerhook_disestablish(sc->sc_powerhook); 508 509 /* 510 * Detach atapibus and its children. 511 */ 512 if ((dev = chp->atapibus) != NULL) { 513 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 514 sc->sc_dev.dv_xname, dev->dv_xname), DEBUG_DETACH); 515 error = config_detach(dev, flags); 516 if (error) 517 goto out; 518 } 519 520 /* 521 * Detach our other children. 522 */ 523 for (i = 0; i < chp->ch_ndrive; i++) { 524 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 525 continue; 526 if ((dev = chp->ch_drive[i].drv_softc) != NULL) { 527 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 528 sc->sc_dev.dv_xname, dev->dv_xname), 529 DEBUG_DETACH); 530 error = config_detach(dev, flags); 531 if (error) 532 goto out; 533 } 534 } 535 536 out: 537 #ifdef ATADEBUG 538 if (dev != NULL && error != 0) 539 ATADEBUG_PRINT(("atabus_detach: %s: error %d detaching %s\n", 540 sc->sc_dev.dv_xname, error, dev->dv_xname), 541 DEBUG_DETACH); 542 #endif /* ATADEBUG */ 543 544 return (error); 545 } 546 547 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 548 atabus_match, atabus_attach, atabus_detach, atabus_activate); 549 550 /***************************************************************************** 551 * Common ATA bus operations. 552 *****************************************************************************/ 553 554 /* Get the disk's parameters */ 555 int 556 ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags, 557 struct ataparams *prms) 558 { 559 char tb[DEV_BSIZE]; 560 struct ata_command ata_c; 561 struct ata_channel *chp = drvp->chnl_softc; 562 struct atac_softc *atac = chp->ch_atac; 563 int i; 564 u_int16_t *p; 565 566 ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS); 567 568 memset(tb, 0, DEV_BSIZE); 569 memset(prms, 0, sizeof(struct ataparams)); 570 memset(&ata_c, 0, sizeof(struct ata_command)); 571 572 if (drvp->drive_flags & DRIVE_ATA) { 573 ata_c.r_command = WDCC_IDENTIFY; 574 ata_c.r_st_bmask = WDCS_DRDY; 575 ata_c.r_st_pmask = WDCS_DRQ; 576 ata_c.timeout = 3000; /* 3s */ 577 } else if (drvp->drive_flags & DRIVE_ATAPI) { 578 ata_c.r_command = ATAPI_IDENTIFY_DEVICE; 579 ata_c.r_st_bmask = 0; 580 ata_c.r_st_pmask = WDCS_DRQ; 581 ata_c.timeout = 10000; /* 10s */ 582 } else { 583 ATADEBUG_PRINT(("ata_get_parms: no disks\n"), 584 DEBUG_FUNCS|DEBUG_PROBE); 585 return CMD_ERR; 586 } 587 ata_c.flags = AT_READ | flags; 588 ata_c.data = tb; 589 ata_c.bcount = DEV_BSIZE; 590 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 591 &ata_c) != ATACMD_COMPLETE) { 592 ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"), 593 DEBUG_FUNCS|DEBUG_PROBE); 594 return CMD_AGAIN; 595 } 596 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 597 ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n", 598 ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE); 599 return CMD_ERR; 600 } 601 /* if we didn't read any data something is wrong */ 602 if ((ata_c.flags & AT_XFDONE) == 0) 603 return CMD_ERR; 604 605 /* Read in parameter block. */ 606 memcpy(prms, tb, sizeof(struct ataparams)); 607 608 /* 609 * Shuffle string byte order. 610 * ATAPI NEC, Mitsumi and Pioneer drives and 611 * old ATA TDK CompactFlash cards 612 * have different byte order. 613 */ 614 #if BYTE_ORDER == BIG_ENDIAN 615 # define M(n) prms->atap_model[(n) ^ 1] 616 #else 617 # define M(n) prms->atap_model[n] 618 #endif 619 if ( 620 #if BYTE_ORDER == BIG_ENDIAN 621 ! 622 #endif 623 ((drvp->drive_flags & DRIVE_ATAPI) ? 624 ((M(0) == 'N' && M(1) == 'E') || 625 (M(0) == 'F' && M(1) == 'X') || 626 (M(0) == 'P' && M(1) == 'i')) : 627 ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) 628 return CMD_OK; 629 #undef M 630 for (i = 0; i < sizeof(prms->atap_model); i += 2) { 631 p = (u_int16_t *)(prms->atap_model + i); 632 *p = bswap16(*p); 633 } 634 for (i = 0; i < sizeof(prms->atap_serial); i += 2) { 635 p = (u_int16_t *)(prms->atap_serial + i); 636 *p = bswap16(*p); 637 } 638 for (i = 0; i < sizeof(prms->atap_revision); i += 2) { 639 p = (u_int16_t *)(prms->atap_revision + i); 640 *p = bswap16(*p); 641 } 642 643 return CMD_OK; 644 } 645 646 int 647 ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags) 648 { 649 struct ata_command ata_c; 650 struct ata_channel *chp = drvp->chnl_softc; 651 struct atac_softc *atac = chp->ch_atac; 652 653 ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS); 654 memset(&ata_c, 0, sizeof(struct ata_command)); 655 656 ata_c.r_command = SET_FEATURES; 657 ata_c.r_st_bmask = 0; 658 ata_c.r_st_pmask = 0; 659 ata_c.r_features = WDSF_SET_MODE; 660 ata_c.r_count = mode; 661 ata_c.flags = flags; 662 ata_c.timeout = 1000; /* 1s */ 663 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 664 &ata_c) != ATACMD_COMPLETE) 665 return CMD_AGAIN; 666 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 667 return CMD_ERR; 668 } 669 return CMD_OK; 670 } 671 672 #if NATA_DMA 673 void 674 ata_dmaerr(struct ata_drive_datas *drvp, int flags) 675 { 676 /* 677 * Downgrade decision: if we get NERRS_MAX in NXFER. 678 * We start with n_dmaerrs set to NERRS_MAX-1 so that the 679 * first error within the first NXFER ops will immediatly trigger 680 * a downgrade. 681 * If we got an error and n_xfers is bigger than NXFER reset counters. 682 */ 683 drvp->n_dmaerrs++; 684 if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) { 685 ata_downgrade_mode(drvp, flags); 686 drvp->n_dmaerrs = NERRS_MAX-1; 687 drvp->n_xfers = 0; 688 return; 689 } 690 if (drvp->n_xfers > NXFER) { 691 drvp->n_dmaerrs = 1; /* just got an error */ 692 drvp->n_xfers = 1; /* restart counting from this error */ 693 } 694 } 695 #endif /* NATA_DMA */ 696 697 /* 698 * freeze the queue and wait for the controller to be idle. Caller has to 699 * unfreeze/restart the queue 700 */ 701 void 702 ata_queue_idle(struct ata_queue *queue) 703 { 704 int s = splbio(); 705 queue->queue_freeze++; 706 while (queue->active_xfer != NULL) { 707 queue->queue_flags |= QF_IDLE_WAIT; 708 tsleep(&queue->queue_flags, PRIBIO, "qidl", 0); 709 } 710 splx(s); 711 } 712 713 /* 714 * Add a command to the queue and start controller. 715 * 716 * MUST BE CALLED AT splbio()! 717 */ 718 void 719 ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 720 { 721 722 ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer, 723 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 724 725 /* complete xfer setup */ 726 xfer->c_chp = chp; 727 728 /* insert at the end of command list */ 729 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 730 ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n", 731 chp->ch_flags), DEBUG_XFERS); 732 /* 733 * if polling and can sleep, wait for the xfer to be at head of queue 734 */ 735 if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) { 736 while (chp->ch_queue->active_xfer != NULL || 737 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) { 738 xfer->c_flags |= C_WAITACT; 739 tsleep(xfer, PRIBIO, "ataact", 0); 740 xfer->c_flags &= ~C_WAITACT; 741 if (xfer->c_flags & C_FREE) { 742 ata_free_xfer(chp, xfer); 743 return; 744 } 745 } 746 } 747 atastart(chp); 748 } 749 750 /* 751 * Start I/O on a controller, for the given channel. 752 * The first xfer may be not for our channel if the channel queues 753 * are shared. 754 * 755 * MUST BE CALLED AT splbio()! 756 */ 757 void 758 atastart(struct ata_channel *chp) 759 { 760 struct atac_softc *atac = chp->ch_atac; 761 struct ata_xfer *xfer; 762 763 #ifdef ATA_DEBUG 764 int spl1, spl2; 765 766 spl1 = splbio(); 767 spl2 = splbio(); 768 if (spl2 != spl1) { 769 printf("atastart: not at splbio()\n"); 770 panic("atastart"); 771 } 772 splx(spl2); 773 splx(spl1); 774 #endif /* ATA_DEBUG */ 775 776 /* is there a xfer ? */ 777 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 778 return; 779 780 /* adjust chp, in case we have a shared queue */ 781 chp = xfer->c_chp; 782 783 if (chp->ch_queue->active_xfer != NULL) { 784 return; /* channel aleady active */ 785 } 786 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 787 if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) { 788 chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT; 789 wakeup(&chp->ch_queue->queue_flags); 790 } 791 return; /* queue frozen */ 792 } 793 /* 794 * if someone is waiting for the command to be active, wake it up 795 * and let it process the command 796 */ 797 if (xfer->c_flags & C_WAITACT) { 798 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d " 799 "wait active\n", xfer, chp->ch_channel, xfer->c_drive), 800 DEBUG_XFERS); 801 wakeup(xfer); 802 return; 803 } 804 #ifdef DIAGNOSTIC 805 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) 806 panic("atastart: channel waiting for irq"); 807 #endif 808 if (atac->atac_claim_hw) 809 if (!(*atac->atac_claim_hw)(chp, 0)) 810 return; 811 812 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer, 813 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 814 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 815 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 816 chp->ch_drive[xfer->c_drive].state = 0; 817 } 818 chp->ch_queue->active_xfer = xfer; 819 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 820 821 if (atac->atac_cap & ATAC_CAP_NOIRQ) 822 KASSERT(xfer->c_flags & C_POLL); 823 824 xfer->c_start(chp, xfer); 825 } 826 827 struct ata_xfer * 828 ata_get_xfer(int flags) 829 { 830 struct ata_xfer *xfer; 831 int s; 832 833 s = splbio(); 834 xfer = pool_get(&ata_xfer_pool, 835 ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 836 splx(s); 837 if (xfer != NULL) { 838 memset(xfer, 0, sizeof(struct ata_xfer)); 839 } 840 return xfer; 841 } 842 843 void 844 ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 845 { 846 struct atac_softc *atac = chp->ch_atac; 847 int s; 848 849 if (xfer->c_flags & C_WAITACT) { 850 /* Someone is waiting for this xfer, so we can't free now */ 851 xfer->c_flags |= C_FREE; 852 wakeup(xfer); 853 return; 854 } 855 856 #if NATA_PIOBM /* XXX wdc dependent code */ 857 if (xfer->c_flags & C_PIOBM) { 858 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 859 860 /* finish the busmastering PIO */ 861 (*wdc->piobm_done)(wdc->dma_arg, 862 chp->ch_channel, xfer->c_drive); 863 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT); 864 } 865 #endif 866 867 if (atac->atac_free_hw) 868 (*atac->atac_free_hw)(chp); 869 s = splbio(); 870 pool_put(&ata_xfer_pool, xfer); 871 splx(s); 872 } 873 874 /* 875 * Kill off all pending xfers for a ata_channel. 876 * 877 * Must be called at splbio(). 878 */ 879 void 880 ata_kill_pending(struct ata_drive_datas *drvp) 881 { 882 struct ata_channel *chp = drvp->chnl_softc; 883 struct ata_xfer *xfer, *next_xfer; 884 int s = splbio(); 885 886 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 887 xfer != NULL; xfer = next_xfer) { 888 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 889 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 890 continue; 891 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 892 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 893 } 894 895 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 896 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 897 drvp->drive_flags |= DRIVE_WAITDRAIN; 898 (void) tsleep(&chp->ch_queue->active_xfer, 899 PRIBIO, "atdrn", 0); 900 } else { 901 /* no more xfer for us */ 902 break; 903 } 904 } 905 splx(s); 906 } 907 908 /* 909 * ata_reset_channel: 910 * 911 * Reset and ATA channel. 912 * 913 * MUST BE CALLED AT splbio()! 914 */ 915 void 916 ata_reset_channel(struct ata_channel *chp, int flags) 917 { 918 struct atac_softc *atac = chp->ch_atac; 919 int drive; 920 921 #ifdef ATA_DEBUG 922 int spl1, spl2; 923 924 spl1 = splbio(); 925 spl2 = splbio(); 926 if (spl2 != spl1) { 927 printf("ata_reset_channel: not at splbio()\n"); 928 panic("ata_reset_channel"); 929 } 930 splx(spl2); 931 splx(spl1); 932 #endif /* ATA_DEBUG */ 933 934 chp->ch_queue->queue_freeze++; 935 936 /* 937 * If we can poll or wait it's OK, otherwise wake up the 938 * kernel thread to do it for us. 939 */ 940 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 941 if (chp->ch_flags & ATACH_TH_RESET) { 942 /* No need to schedule a reset more than one time. */ 943 chp->ch_queue->queue_freeze--; 944 return; 945 } 946 chp->ch_flags |= ATACH_TH_RESET; 947 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 948 wakeup(&chp->ch_thread); 949 return; 950 } 951 952 (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags); 953 954 for (drive = 0; drive < chp->ch_ndrive; drive++) 955 chp->ch_drive[drive].state = 0; 956 957 chp->ch_flags &= ~ATACH_TH_RESET; 958 if ((flags & AT_RST_EMERG) == 0) { 959 chp->ch_queue->queue_freeze--; 960 atastart(chp); 961 } else { 962 /* make sure that we can use polled commands */ 963 TAILQ_INIT(&chp->ch_queue->queue_xfer); 964 chp->ch_queue->queue_freeze = 0; 965 chp->ch_queue->active_xfer = NULL; 966 } 967 } 968 969 int 970 ata_addref(struct ata_channel *chp) 971 { 972 struct atac_softc *atac = chp->ch_atac; 973 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 974 int s, error = 0; 975 976 s = splbio(); 977 if (adapt->adapt_refcnt++ == 0 && 978 adapt->adapt_enable != NULL) { 979 error = (*adapt->adapt_enable)(&atac->atac_dev, 1); 980 if (error) 981 adapt->adapt_refcnt--; 982 } 983 splx(s); 984 return (error); 985 } 986 987 void 988 ata_delref(struct ata_channel *chp) 989 { 990 struct atac_softc *atac = chp->ch_atac; 991 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 992 int s; 993 994 s = splbio(); 995 if (adapt->adapt_refcnt-- == 1 && 996 adapt->adapt_enable != NULL) 997 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 998 splx(s); 999 } 1000 1001 void 1002 ata_print_modes(struct ata_channel *chp) 1003 { 1004 struct atac_softc *atac = chp->ch_atac; 1005 int drive; 1006 struct ata_drive_datas *drvp; 1007 1008 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1009 drvp = &chp->ch_drive[drive]; 1010 if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL) 1011 continue; 1012 aprint_verbose("%s(%s:%d:%d): using PIO mode %d", 1013 drvp->drv_softc->dv_xname, 1014 atac->atac_dev.dv_xname, 1015 chp->ch_channel, drvp->drive, drvp->PIO_mode); 1016 #if NATA_DMA 1017 if (drvp->drive_flags & DRIVE_DMA) 1018 aprint_verbose(", DMA mode %d", drvp->DMA_mode); 1019 #if NATA_UDMA 1020 if (drvp->drive_flags & DRIVE_UDMA) { 1021 aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode); 1022 if (drvp->UDMA_mode == 2) 1023 aprint_verbose(" (Ultra/33)"); 1024 else if (drvp->UDMA_mode == 4) 1025 aprint_verbose(" (Ultra/66)"); 1026 else if (drvp->UDMA_mode == 5) 1027 aprint_verbose(" (Ultra/100)"); 1028 else if (drvp->UDMA_mode == 6) 1029 aprint_verbose(" (Ultra/133)"); 1030 } 1031 #endif /* NATA_UDMA */ 1032 #endif /* NATA_DMA */ 1033 #if NATA_DMA || NATA_PIOBM 1034 if (0 1035 #if NATA_DMA 1036 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1037 #endif 1038 #if NATA_PIOBM 1039 /* PIOBM capable controllers use DMA for PIO commands */ 1040 || (atac->atac_cap & ATAC_CAP_PIOBM) 1041 #endif 1042 ) 1043 aprint_verbose(" (using DMA)"); 1044 #endif /* NATA_DMA || NATA_PIOBM */ 1045 aprint_verbose("\n"); 1046 } 1047 } 1048 1049 #if NATA_DMA 1050 /* 1051 * downgrade the transfer mode of a drive after an error. return 1 if 1052 * downgrade was possible, 0 otherwise. 1053 * 1054 * MUST BE CALLED AT splbio()! 1055 */ 1056 int 1057 ata_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1058 { 1059 struct ata_channel *chp = drvp->chnl_softc; 1060 struct atac_softc *atac = chp->ch_atac; 1061 struct device *drv_dev = drvp->drv_softc; 1062 int cf_flags = device_cfdata(drv_dev)->cf_flags; 1063 1064 /* if drive or controller don't know its mode, we can't do much */ 1065 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1066 (atac->atac_set_modes == NULL)) 1067 return 0; 1068 /* current drive mode was set by a config flag, let it this way */ 1069 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1070 (cf_flags & ATA_CONFIG_DMA_SET) || 1071 (cf_flags & ATA_CONFIG_UDMA_SET)) 1072 return 0; 1073 1074 #if NATA_UDMA 1075 /* 1076 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1077 */ 1078 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1079 drvp->UDMA_mode--; 1080 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1081 drv_dev->dv_xname, drvp->UDMA_mode); 1082 } 1083 #endif 1084 1085 /* 1086 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1087 */ 1088 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1089 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1090 drvp->PIO_mode = drvp->PIO_cap; 1091 printf("%s: transfer error, downgrading to PIO mode %d\n", 1092 drv_dev->dv_xname, drvp->PIO_mode); 1093 } else /* already using PIO, can't downgrade */ 1094 return 0; 1095 1096 (*atac->atac_set_modes)(chp); 1097 ata_print_modes(chp); 1098 /* reset the channel, which will schedule all drives for setup */ 1099 ata_reset_channel(chp, flags | AT_RST_NOCMD); 1100 return 1; 1101 } 1102 #endif /* NATA_DMA */ 1103 1104 /* 1105 * Probe drive's capabilities, for use by the controller later 1106 * Assumes drvp points to an existing drive. 1107 */ 1108 void 1109 ata_probe_caps(struct ata_drive_datas *drvp) 1110 { 1111 struct ataparams params, params2; 1112 struct ata_channel *chp = drvp->chnl_softc; 1113 struct atac_softc *atac = chp->ch_atac; 1114 struct device *drv_dev = drvp->drv_softc; 1115 int i, printed, s; 1116 const char *sep = ""; 1117 int cf_flags; 1118 1119 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1120 /* IDENTIFY failed. Can't tell more about the device */ 1121 return; 1122 } 1123 if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == 1124 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 1125 /* 1126 * Controller claims 16 and 32 bit transfers. 1127 * Re-do an IDENTIFY with 32-bit transfers, 1128 * and compare results. 1129 */ 1130 s = splbio(); 1131 drvp->drive_flags |= DRIVE_CAP32; 1132 splx(s); 1133 ata_get_params(drvp, AT_WAIT, ¶ms2); 1134 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1135 /* Not good. fall back to 16bits */ 1136 s = splbio(); 1137 drvp->drive_flags &= ~DRIVE_CAP32; 1138 splx(s); 1139 } else { 1140 aprint_verbose("%s: 32-bit data port\n", 1141 drv_dev->dv_xname); 1142 } 1143 } 1144 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1145 if (params.atap_ata_major > 0x01 && 1146 params.atap_ata_major != 0xffff) { 1147 for (i = 14; i > 0; i--) { 1148 if (params.atap_ata_major & (1 << i)) { 1149 aprint_verbose("%s: ATA version %d\n", 1150 drv_dev->dv_xname, i); 1151 drvp->ata_vers = i; 1152 break; 1153 } 1154 } 1155 } 1156 #endif 1157 1158 /* An ATAPI device is at last PIO mode 3 */ 1159 if (drvp->drive_flags & DRIVE_ATAPI) 1160 drvp->PIO_mode = 3; 1161 1162 /* 1163 * It's not in the specs, but it seems that some drive 1164 * returns 0xffff in atap_extensions when this field is invalid 1165 */ 1166 if (params.atap_extensions != 0xffff && 1167 (params.atap_extensions & WDC_EXT_MODES)) { 1168 printed = 0; 1169 /* 1170 * XXX some drives report something wrong here (they claim to 1171 * support PIO mode 8 !). As mode is coded on 3 bits in 1172 * SET FEATURE, limit it to 7 (so limit i to 4). 1173 * If higher mode than 7 is found, abort. 1174 */ 1175 for (i = 7; i >= 0; i--) { 1176 if ((params.atap_piomode_supp & (1 << i)) == 0) 1177 continue; 1178 if (i > 4) 1179 return; 1180 /* 1181 * See if mode is accepted. 1182 * If the controller can't set its PIO mode, 1183 * assume the defaults are good, so don't try 1184 * to set it 1185 */ 1186 if (atac->atac_set_modes) 1187 /* 1188 * It's OK to pool here, it's fast enouth 1189 * to not bother waiting for interrupt 1190 */ 1191 if (ata_set_mode(drvp, 0x08 | (i + 3), 1192 AT_WAIT) != CMD_OK) 1193 continue; 1194 if (!printed) { 1195 aprint_verbose("%s: drive supports PIO mode %d", 1196 drv_dev->dv_xname, i + 3); 1197 sep = ","; 1198 printed = 1; 1199 } 1200 /* 1201 * If controller's driver can't set its PIO mode, 1202 * get the highter one for the drive. 1203 */ 1204 if (atac->atac_set_modes == NULL || 1205 atac->atac_pio_cap >= i + 3) { 1206 drvp->PIO_mode = i + 3; 1207 drvp->PIO_cap = i + 3; 1208 break; 1209 } 1210 } 1211 if (!printed) { 1212 /* 1213 * We didn't find a valid PIO mode. 1214 * Assume the values returned for DMA are buggy too 1215 */ 1216 return; 1217 } 1218 s = splbio(); 1219 drvp->drive_flags |= DRIVE_MODE; 1220 splx(s); 1221 printed = 0; 1222 for (i = 7; i >= 0; i--) { 1223 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1224 continue; 1225 #if NATA_DMA 1226 if ((atac->atac_cap & ATAC_CAP_DMA) && 1227 atac->atac_set_modes != NULL) 1228 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1229 != CMD_OK) 1230 continue; 1231 #endif 1232 if (!printed) { 1233 aprint_verbose("%s DMA mode %d", sep, i); 1234 sep = ","; 1235 printed = 1; 1236 } 1237 #if NATA_DMA 1238 if (atac->atac_cap & ATAC_CAP_DMA) { 1239 if (atac->atac_set_modes != NULL && 1240 atac->atac_dma_cap < i) 1241 continue; 1242 drvp->DMA_mode = i; 1243 drvp->DMA_cap = i; 1244 s = splbio(); 1245 drvp->drive_flags |= DRIVE_DMA; 1246 splx(s); 1247 } 1248 #endif 1249 break; 1250 } 1251 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1252 printed = 0; 1253 for (i = 7; i >= 0; i--) { 1254 if ((params.atap_udmamode_supp & (1 << i)) 1255 == 0) 1256 continue; 1257 #if NATA_UDMA 1258 if (atac->atac_set_modes != NULL && 1259 (atac->atac_cap & ATAC_CAP_UDMA)) 1260 if (ata_set_mode(drvp, 0x40 | i, 1261 AT_WAIT) != CMD_OK) 1262 continue; 1263 #endif 1264 if (!printed) { 1265 aprint_verbose("%s Ultra-DMA mode %d", 1266 sep, i); 1267 if (i == 2) 1268 aprint_verbose(" (Ultra/33)"); 1269 else if (i == 4) 1270 aprint_verbose(" (Ultra/66)"); 1271 else if (i == 5) 1272 aprint_verbose(" (Ultra/100)"); 1273 else if (i == 6) 1274 aprint_verbose(" (Ultra/133)"); 1275 sep = ","; 1276 printed = 1; 1277 } 1278 #if NATA_UDMA 1279 if (atac->atac_cap & ATAC_CAP_UDMA) { 1280 if (atac->atac_set_modes != NULL && 1281 atac->atac_udma_cap < i) 1282 continue; 1283 drvp->UDMA_mode = i; 1284 drvp->UDMA_cap = i; 1285 s = splbio(); 1286 drvp->drive_flags |= DRIVE_UDMA; 1287 splx(s); 1288 } 1289 #endif 1290 break; 1291 } 1292 } 1293 aprint_verbose("\n"); 1294 } 1295 1296 s = splbio(); 1297 drvp->drive_flags &= ~DRIVE_NOSTREAM; 1298 if (drvp->drive_flags & DRIVE_ATAPI) { 1299 if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM) 1300 drvp->drive_flags |= DRIVE_NOSTREAM; 1301 } else { 1302 if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM) 1303 drvp->drive_flags |= DRIVE_NOSTREAM; 1304 } 1305 splx(s); 1306 1307 /* Try to guess ATA version here, if it didn't get reported */ 1308 if (drvp->ata_vers == 0) { 1309 #if NATA_UDMA 1310 if (drvp->drive_flags & DRIVE_UDMA) 1311 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1312 else 1313 #endif 1314 if (drvp->PIO_cap > 2) 1315 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1316 } 1317 cf_flags = device_cfdata(drv_dev)->cf_flags; 1318 if (cf_flags & ATA_CONFIG_PIO_SET) { 1319 s = splbio(); 1320 drvp->PIO_mode = 1321 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1322 drvp->drive_flags |= DRIVE_MODE; 1323 splx(s); 1324 } 1325 #if NATA_DMA 1326 if ((atac->atac_cap & ATAC_CAP_DMA) == 0) { 1327 /* don't care about DMA modes */ 1328 return; 1329 } 1330 if (cf_flags & ATA_CONFIG_DMA_SET) { 1331 s = splbio(); 1332 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1333 ATA_CONFIG_DMA_DISABLE) { 1334 drvp->drive_flags &= ~DRIVE_DMA; 1335 } else { 1336 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1337 ATA_CONFIG_DMA_OFF; 1338 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1339 } 1340 splx(s); 1341 } 1342 #if NATA_UDMA 1343 if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) { 1344 /* don't care about UDMA modes */ 1345 return; 1346 } 1347 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1348 s = splbio(); 1349 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1350 ATA_CONFIG_UDMA_DISABLE) { 1351 drvp->drive_flags &= ~DRIVE_UDMA; 1352 } else { 1353 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1354 ATA_CONFIG_UDMA_OFF; 1355 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1356 } 1357 splx(s); 1358 } 1359 #endif /* NATA_UDMA */ 1360 #endif /* NATA_DMA */ 1361 } 1362 1363 /* management of the /dev/atabus* devices */ 1364 int 1365 atabusopen(dev_t dev, int flag, int fmt, 1366 struct lwp *l) 1367 { 1368 struct atabus_softc *sc; 1369 int error, unit = minor(dev); 1370 1371 if (unit >= atabus_cd.cd_ndevs || 1372 (sc = atabus_cd.cd_devs[unit]) == NULL) 1373 return (ENXIO); 1374 1375 if (sc->sc_flags & ATABUSCF_OPEN) 1376 return (EBUSY); 1377 1378 if ((error = ata_addref(sc->sc_chan)) != 0) 1379 return (error); 1380 1381 sc->sc_flags |= ATABUSCF_OPEN; 1382 1383 return (0); 1384 } 1385 1386 1387 int 1388 atabusclose(dev_t dev, int flag, int fmt, 1389 struct lwp *l) 1390 { 1391 struct atabus_softc *sc = atabus_cd.cd_devs[minor(dev)]; 1392 1393 ata_delref(sc->sc_chan); 1394 1395 sc->sc_flags &= ~ATABUSCF_OPEN; 1396 1397 return (0); 1398 } 1399 1400 int 1401 atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, 1402 struct lwp *l) 1403 { 1404 struct atabus_softc *sc = atabus_cd.cd_devs[minor(dev)]; 1405 struct ata_channel *chp = sc->sc_chan; 1406 int min_drive, max_drive, drive; 1407 int error; 1408 int s; 1409 1410 /* 1411 * Enforce write permission for ioctls that change the 1412 * state of the bus. Host adapter specific ioctls must 1413 * be checked by the adapter driver. 1414 */ 1415 switch (cmd) { 1416 case ATABUSIOSCAN: 1417 case ATABUSIODETACH: 1418 case ATABUSIORESET: 1419 if ((flag & FWRITE) == 0) 1420 return (EBADF); 1421 } 1422 1423 switch (cmd) { 1424 case ATABUSIORESET: 1425 s = splbio(); 1426 ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL); 1427 splx(s); 1428 error = 0; 1429 break; 1430 case ATABUSIOSCAN: 1431 { 1432 #if 0 1433 struct atabusioscan_args *a= 1434 (struct atabusioscan_args *)addr; 1435 #endif 1436 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1437 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1438 return (EOPNOTSUPP); 1439 return (EOPNOTSUPP); 1440 } 1441 case ATABUSIODETACH: 1442 { 1443 struct atabusioscan_args *a= 1444 (struct atabusioscan_args *)addr; 1445 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1446 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1447 return (EOPNOTSUPP); 1448 switch (a->at_dev) { 1449 case -1: 1450 min_drive = 0; 1451 max_drive = 1; 1452 break; 1453 case 0: 1454 case 1: 1455 min_drive = max_drive = a->at_dev; 1456 break; 1457 default: 1458 return (EINVAL); 1459 } 1460 for (drive = min_drive; drive <= max_drive; drive++) { 1461 if (chp->ch_drive[drive].drv_softc != NULL) { 1462 error = config_detach( 1463 chp->ch_drive[drive].drv_softc, 0); 1464 if (error) 1465 return (error); 1466 chp->ch_drive[drive].drv_softc = NULL; 1467 } 1468 } 1469 error = 0; 1470 break; 1471 } 1472 default: 1473 error = ENOTTY; 1474 } 1475 return (error); 1476 }; 1477 1478 static void 1479 atabus_powerhook(int why, void *hdl) 1480 { 1481 struct atabus_softc *sc = (struct atabus_softc *)hdl; 1482 struct ata_channel *chp = sc->sc_chan; 1483 int s; 1484 1485 switch (why) { 1486 case PWR_SOFTSUSPEND: 1487 case PWR_SOFTSTANDBY: 1488 /* freeze the queue and wait for the controller to be idle */ 1489 ata_queue_idle(chp->ch_queue); 1490 break; 1491 case PWR_RESUME: 1492 printf("%s: resuming...\n", sc->sc_dev.dv_xname); 1493 s = splbio(); 1494 KASSERT(chp->ch_queue->queue_freeze > 0); 1495 /* unfreeze the queue and reset drives (to wake them up) */ 1496 chp->ch_queue->queue_freeze--; 1497 ata_reset_channel(chp, AT_WAIT); 1498 splx(s); 1499 break; 1500 case PWR_SUSPEND: 1501 case PWR_STANDBY: 1502 case PWR_SOFTRESUME: 1503 break; 1504 } 1505 1506 return; 1507 } 1508
Indexes created Fri Sep 26 08:10:20 GMT 2025