ata.c revision 1.93
1 /* $NetBSD: ata.c,v 1.93 2007/12/20 20:12:01 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.93 2007/12/20 20:12:01 pooka Exp $"); 34 35 #include "opt_ata.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/fcntl.h> 44 #include <sys/proc.h> 45 #include <sys/pool.h> 46 #include <sys/kthread.h> 47 #include <sys/errno.h> 48 #include <sys/ataio.h> 49 #include <sys/kmem.h> 50 51 #include <sys/intr.h> 52 #include <sys/bus.h> 53 54 #include <dev/ata/ataconf.h> 55 #include <dev/ata/atareg.h> 56 #include <dev/ata/atavar.h> 57 #include <dev/ic/wdcvar.h> /* for PIOBM */ 58 59 #include "locators.h" 60 61 #include "atapibus.h" 62 #include "ataraid.h" 63 64 #if NATARAID > 0 65 #include <dev/ata/ata_raidvar.h> 66 #endif 67 68 #define DEBUG_FUNCS 0x08 69 #define DEBUG_PROBE 0x10 70 #define DEBUG_DETACH 0x20 71 #define DEBUG_XFERS 0x40 72 #ifdef ATADEBUG 73 int atadebug_mask = 0; 74 #define ATADEBUG_PRINT(args, level) \ 75 if (atadebug_mask & (level)) \ 76 printf args 77 #else 78 #define ATADEBUG_PRINT(args, level) 79 #endif 80 81 POOL_INIT(ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, "ataspl", NULL, 82 IPL_BIO); 83 84 /* 85 * A queue of atabus instances, used to ensure the same bus probe order 86 * for a given hardware configuration at each boot. 87 */ 88 struct atabus_initq_head atabus_initq_head = 89 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 90 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 91 92 /***************************************************************************** 93 * ATA bus layer. 94 * 95 * ATA controllers attach an atabus instance, which handles probing the bus 96 * for drives, etc. 97 *****************************************************************************/ 98 99 dev_type_open(atabusopen); 100 dev_type_close(atabusclose); 101 dev_type_ioctl(atabusioctl); 102 103 const struct cdevsw atabus_cdevsw = { 104 atabusopen, atabusclose, noread, nowrite, atabusioctl, 105 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 106 }; 107 108 extern struct cfdriver atabus_cd; 109 110 static bool atabus_resume(device_t); 111 static bool atabus_suspend(device_t); 112 113 /* 114 * atabusprint: 115 * 116 * Autoconfiguration print routine used by ATA controllers when 117 * attaching an atabus instance. 118 */ 119 int 120 atabusprint(void *aux, const char *pnp) 121 { 122 struct ata_channel *chan = aux; 123 124 if (pnp) 125 aprint_normal("atabus at %s", pnp); 126 aprint_normal(" channel %d", chan->ch_channel); 127 128 return (UNCONF); 129 } 130 131 /* 132 * ataprint: 133 * 134 * Autoconfiguration print routine. 135 */ 136 int 137 ataprint(void *aux, const char *pnp) 138 { 139 struct ata_device *adev = aux; 140 141 if (pnp) 142 aprint_normal("wd at %s", pnp); 143 aprint_normal(" drive %d", adev->adev_drv_data->drive); 144 145 return (UNCONF); 146 } 147 148 /* 149 * ata_channel_attach: 150 * 151 * Common parts of attaching an atabus to an ATA controller channel. 152 */ 153 void 154 ata_channel_attach(struct ata_channel *chp) 155 { 156 157 if (chp->ch_flags & ATACH_DISABLED) 158 return; 159 160 callout_init(&chp->ch_callout, 0); 161 162 TAILQ_INIT(&chp->ch_queue->queue_xfer); 163 chp->ch_queue->queue_freeze = 0; 164 chp->ch_queue->queue_flags = 0; 165 chp->ch_queue->active_xfer = NULL; 166 167 chp->atabus = config_found_ia(&chp->ch_atac->atac_dev, "ata", chp, 168 atabusprint); 169 } 170 171 static void 172 atabusconfig(struct atabus_softc *atabus_sc) 173 { 174 struct ata_channel *chp = atabus_sc->sc_chan; 175 struct atac_softc *atac = chp->ch_atac; 176 int i, s; 177 struct atabus_initq *atabus_initq = NULL; 178 179 /* Probe for the drives. */ 180 /* XXX for SATA devices we will power up all drives at once */ 181 (*atac->atac_probe)(chp); 182 183 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 184 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 185 DEBUG_PROBE); 186 187 /* If no drives, abort here */ 188 for (i = 0; i < chp->ch_ndrive; i++) 189 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 190 break; 191 if (i == chp->ch_ndrive) 192 goto out; 193 194 /* Shortcut in case we've been shutdown */ 195 if (chp->ch_flags & ATACH_SHUTDOWN) 196 goto out; 197 198 /* Make sure the devices probe in atabus order to avoid jitter. */ 199 simple_lock(&atabus_interlock); 200 while(1) { 201 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 202 if (atabus_initq->atabus_sc == atabus_sc) 203 break; 204 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 205 &atabus_interlock); 206 } 207 simple_unlock(&atabus_interlock); 208 209 /* 210 * Attach an ATAPI bus, if needed. 211 */ 212 for (i = 0; i < chp->ch_ndrive; i++) { 213 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 214 #if NATAPIBUS > 0 215 (*atac->atac_atapibus_attach)(atabus_sc); 216 #else 217 /* 218 * Fake the autoconfig "not configured" message 219 */ 220 aprint_normal("atapibus at %s not configured\n", 221 atac->atac_dev.dv_xname); 222 chp->atapibus = NULL; 223 s = splbio(); 224 for (i = 0; i < chp->ch_ndrive; i++) 225 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 226 splx(s); 227 #endif 228 break; 229 } 230 } 231 232 for (i = 0; i < chp->ch_ndrive; i++) { 233 struct ata_device adev; 234 if ((chp->ch_drive[i].drive_flags & 235 (DRIVE_ATA | DRIVE_OLD)) == 0) { 236 continue; 237 } 238 memset(&adev, 0, sizeof(struct ata_device)); 239 adev.adev_bustype = atac->atac_bustype_ata; 240 adev.adev_channel = chp->ch_channel; 241 adev.adev_openings = 1; 242 adev.adev_drv_data = &chp->ch_drive[i]; 243 chp->ata_drives[i] = config_found_ia(&atabus_sc->sc_dev, 244 "ata_hl", &adev, ataprint); 245 if (chp->ata_drives[i] != NULL) 246 ata_probe_caps(&chp->ch_drive[i]); 247 else { 248 s = splbio(); 249 chp->ch_drive[i].drive_flags &= 250 ~(DRIVE_ATA | DRIVE_OLD); 251 splx(s); 252 } 253 } 254 255 /* now that we know the drives, the controller can set its modes */ 256 if (atac->atac_set_modes) { 257 (*atac->atac_set_modes)(chp); 258 ata_print_modes(chp); 259 } 260 #if NATARAID > 0 261 if (atac->atac_cap & ATAC_CAP_RAID) 262 for (i = 0; i < chp->ch_ndrive; i++) 263 if (chp->ata_drives[i] != NULL) 264 ata_raid_check_component(chp->ata_drives[i]); 265 #endif /* NATARAID > 0 */ 266 267 /* 268 * reset drive_flags for unattached devices, reset state for attached 269 * ones 270 */ 271 s = splbio(); 272 for (i = 0; i < chp->ch_ndrive; i++) { 273 if (chp->ch_drive[i].drv_softc == NULL) 274 chp->ch_drive[i].drive_flags = 0; 275 else 276 chp->ch_drive[i].state = 0; 277 } 278 splx(s); 279 280 out: 281 if (atabus_initq == NULL) { 282 simple_lock(&atabus_interlock); 283 while(1) { 284 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 285 if (atabus_initq->atabus_sc == atabus_sc) 286 break; 287 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 288 &atabus_interlock); 289 } 290 simple_unlock(&atabus_interlock); 291 } 292 simple_lock(&atabus_interlock); 293 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 294 simple_unlock(&atabus_interlock); 295 296 free(atabus_initq, M_DEVBUF); 297 wakeup(&atabus_initq_head); 298 299 ata_delref(chp); 300 301 config_pending_decr(); 302 } 303 304 /* 305 * atabus_thread: 306 * 307 * Worker thread for the ATA bus. 308 */ 309 static void 310 atabus_thread(void *arg) 311 { 312 struct atabus_softc *sc = arg; 313 struct ata_channel *chp = sc->sc_chan; 314 struct ata_xfer *xfer; 315 int i, s; 316 317 s = splbio(); 318 chp->ch_flags |= ATACH_TH_RUN; 319 320 /* 321 * Probe the drives. Reset all flags to 0 to indicate to controllers 322 * that can re-probe that all drives must be probed.. 323 * 324 * Note: ch_ndrive may be changed during the probe. 325 */ 326 for (i = 0; i < ATA_MAXDRIVES; i++) 327 chp->ch_drive[i].drive_flags = 0; 328 splx(s); 329 330 /* Configure the devices on the bus. */ 331 atabusconfig(sc); 332 333 s = splbio(); 334 for (;;) { 335 if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 && 336 (chp->ch_queue->active_xfer == NULL || 337 chp->ch_queue->queue_freeze == 0)) { 338 chp->ch_flags &= ~ATACH_TH_RUN; 339 (void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0); 340 chp->ch_flags |= ATACH_TH_RUN; 341 } 342 if (chp->ch_flags & ATACH_SHUTDOWN) { 343 break; 344 } 345 if (chp->ch_flags & ATACH_TH_RESET) { 346 /* 347 * ata_reset_channel() will freeze 2 times, so 348 * unfreeze one time. Not a problem as we're at splbio 349 */ 350 chp->ch_queue->queue_freeze--; 351 ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags); 352 } else if (chp->ch_queue->active_xfer != NULL && 353 chp->ch_queue->queue_freeze == 1) { 354 /* 355 * Caller has bumped queue_freeze, decrease it. 356 */ 357 chp->ch_queue->queue_freeze--; 358 xfer = chp->ch_queue->active_xfer; 359 KASSERT(xfer != NULL); 360 (*xfer->c_start)(xfer->c_chp, xfer); 361 } else if (chp->ch_queue->queue_freeze > 1) 362 panic("ata_thread: queue_freeze"); 363 } 364 splx(s); 365 chp->ch_thread = NULL; 366 wakeup(&chp->ch_flags); 367 kthread_exit(0); 368 } 369 370 /* 371 * atabus_match: 372 * 373 * Autoconfiguration match routine. 374 */ 375 static int 376 atabus_match(struct device *parent, struct cfdata *cf, void *aux) 377 { 378 struct ata_channel *chp = aux; 379 380 if (chp == NULL) 381 return (0); 382 383 if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel && 384 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 385 return (0); 386 387 return (1); 388 } 389 390 /* 391 * atabus_attach: 392 * 393 * Autoconfiguration attach routine. 394 */ 395 static void 396 atabus_attach(struct device *parent, struct device *self, void *aux) 397 { 398 struct atabus_softc *sc = (void *) self; 399 struct ata_channel *chp = aux; 400 struct atabus_initq *initq; 401 int error; 402 403 sc->sc_chan = chp; 404 405 aprint_normal("\n"); 406 aprint_naive("\n"); 407 408 if (ata_addref(chp)) 409 return; 410 411 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK); 412 initq->atabus_sc = sc; 413 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq); 414 config_pending_incr(); 415 416 if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc, 417 &chp->ch_thread, "%s", sc->sc_dev.dv_xname)) != 0) 418 aprint_error("%s: unable to create kernel thread: error %d\n", 419 sc->sc_dev.dv_xname, error); 420 421 if (!pmf_device_register(self, atabus_suspend, atabus_resume)) 422 aprint_error_dev(self, "couldn't establish power handler\n"); 423 } 424 425 /* 426 * atabus_activate: 427 * 428 * Autoconfiguration activation routine. 429 */ 430 static int 431 atabus_activate(struct device *self, enum devact act) 432 { 433 struct atabus_softc *sc = (void *) self; 434 struct ata_channel *chp = sc->sc_chan; 435 struct device *dev = NULL; 436 int s, i, error = 0; 437 438 s = splbio(); 439 switch (act) { 440 case DVACT_ACTIVATE: 441 error = EOPNOTSUPP; 442 break; 443 444 case DVACT_DEACTIVATE: 445 /* 446 * We might deactivate the children of atapibus twice 447 * (once bia atapibus, once directly), but since the 448 * generic autoconfiguration code maintains the DVF_ACTIVE 449 * flag, it's safe. 450 */ 451 if ((dev = chp->atapibus) != NULL) { 452 error = config_deactivate(dev); 453 if (error) 454 goto out; 455 } 456 457 for (i = 0; i < chp->ch_ndrive; i++) { 458 if ((dev = chp->ch_drive[i].drv_softc) != NULL) { 459 ATADEBUG_PRINT(("atabus_activate: %s: " 460 "deactivating %s\n", sc->sc_dev.dv_xname, 461 dev->dv_xname), 462 DEBUG_DETACH); 463 error = config_deactivate(dev); 464 if (error) 465 goto out; 466 } 467 } 468 break; 469 } 470 out: 471 splx(s); 472 473 #ifdef ATADEBUG 474 if (dev != NULL && error != 0) 475 ATADEBUG_PRINT(("atabus_activate: %s: " 476 "error %d deactivating %s\n", sc->sc_dev.dv_xname, 477 error, dev->dv_xname), DEBUG_DETACH); 478 #endif /* ATADEBUG */ 479 480 return (error); 481 } 482 483 /* 484 * atabus_detach: 485 * 486 * Autoconfiguration detach routine. 487 */ 488 static int 489 atabus_detach(struct device *self, int flags) 490 { 491 struct atabus_softc *sc = (void *) self; 492 struct ata_channel *chp = sc->sc_chan; 493 struct device *dev = NULL; 494 int s, i, error = 0; 495 496 /* Shutdown the channel. */ 497 s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */ 498 chp->ch_flags |= ATACH_SHUTDOWN; 499 splx(s); 500 wakeup(&chp->ch_thread); 501 while (chp->ch_thread != NULL) 502 (void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 503 504 /* 505 * Detach atapibus and its children. 506 */ 507 if ((dev = chp->atapibus) != NULL) { 508 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 509 sc->sc_dev.dv_xname, dev->dv_xname), DEBUG_DETACH); 510 error = config_detach(dev, flags); 511 if (error) 512 goto out; 513 } 514 515 /* 516 * Detach our other children. 517 */ 518 for (i = 0; i < chp->ch_ndrive; i++) { 519 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 520 continue; 521 if ((dev = chp->ch_drive[i].drv_softc) != NULL) { 522 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n", 523 sc->sc_dev.dv_xname, dev->dv_xname), 524 DEBUG_DETACH); 525 error = config_detach(dev, flags); 526 if (error) 527 goto out; 528 } 529 } 530 531 out: 532 #ifdef ATADEBUG 533 if (dev != NULL && error != 0) 534 ATADEBUG_PRINT(("atabus_detach: %s: error %d detaching %s\n", 535 sc->sc_dev.dv_xname, error, dev->dv_xname), 536 DEBUG_DETACH); 537 #endif /* ATADEBUG */ 538 539 return (error); 540 } 541 542 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 543 atabus_match, atabus_attach, atabus_detach, atabus_activate); 544 545 /***************************************************************************** 546 * Common ATA bus operations. 547 *****************************************************************************/ 548 549 /* Get the disk's parameters */ 550 int 551 ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags, 552 struct ataparams *prms) 553 { 554 struct ata_command ata_c; 555 struct ata_channel *chp = drvp->chnl_softc; 556 struct atac_softc *atac = chp->ch_atac; 557 char *tb; 558 int i, rv; 559 u_int16_t *p; 560 561 ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS); 562 563 tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP); 564 memset(prms, 0, sizeof(struct ataparams)); 565 memset(&ata_c, 0, sizeof(struct ata_command)); 566 567 if (drvp->drive_flags & DRIVE_ATA) { 568 ata_c.r_command = WDCC_IDENTIFY; 569 ata_c.r_st_bmask = WDCS_DRDY; 570 ata_c.r_st_pmask = WDCS_DRQ; 571 ata_c.timeout = 3000; /* 3s */ 572 } else if (drvp->drive_flags & DRIVE_ATAPI) { 573 ata_c.r_command = ATAPI_IDENTIFY_DEVICE; 574 ata_c.r_st_bmask = 0; 575 ata_c.r_st_pmask = WDCS_DRQ; 576 ata_c.timeout = 10000; /* 10s */ 577 } else { 578 ATADEBUG_PRINT(("ata_get_parms: no disks\n"), 579 DEBUG_FUNCS|DEBUG_PROBE); 580 rv = CMD_ERR; 581 goto out; 582 } 583 ata_c.flags = AT_READ | flags; 584 ata_c.data = tb; 585 ata_c.bcount = DEV_BSIZE; 586 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 587 &ata_c) != ATACMD_COMPLETE) { 588 ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"), 589 DEBUG_FUNCS|DEBUG_PROBE); 590 rv = CMD_AGAIN; 591 goto out; 592 } 593 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 594 ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n", 595 ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE); 596 rv = CMD_ERR; 597 goto out; 598 } 599 /* if we didn't read any data something is wrong */ 600 if ((ata_c.flags & AT_XFDONE) == 0) { 601 rv = CMD_ERR; 602 goto out; 603 } 604 605 /* Read in parameter block. */ 606 memcpy(prms, tb, sizeof(struct ataparams)); 607 608 /* 609 * Shuffle string byte order. 610 * ATAPI NEC, Mitsumi and Pioneer drives and 611 * old ATA TDK CompactFlash cards 612 * have different byte order. 613 */ 614 #if BYTE_ORDER == BIG_ENDIAN 615 # define M(n) prms->atap_model[(n) ^ 1] 616 #else 617 # define M(n) prms->atap_model[n] 618 #endif 619 if ( 620 #if BYTE_ORDER == BIG_ENDIAN 621 ! 622 #endif 623 ((drvp->drive_flags & DRIVE_ATAPI) ? 624 ((M(0) == 'N' && M(1) == 'E') || 625 (M(0) == 'F' && M(1) == 'X') || 626 (M(0) == 'P' && M(1) == 'i')) : 627 ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) { 628 rv = CMD_OK; 629 goto out; 630 } 631 #undef M 632 for (i = 0; i < sizeof(prms->atap_model); i += 2) { 633 p = (u_int16_t *)(prms->atap_model + i); 634 *p = bswap16(*p); 635 } 636 for (i = 0; i < sizeof(prms->atap_serial); i += 2) { 637 p = (u_int16_t *)(prms->atap_serial + i); 638 *p = bswap16(*p); 639 } 640 for (i = 0; i < sizeof(prms->atap_revision); i += 2) { 641 p = (u_int16_t *)(prms->atap_revision + i); 642 *p = bswap16(*p); 643 } 644 645 rv = CMD_OK; 646 out: 647 kmem_free(tb, DEV_BSIZE); 648 return rv; 649 } 650 651 int 652 ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags) 653 { 654 struct ata_command ata_c; 655 struct ata_channel *chp = drvp->chnl_softc; 656 struct atac_softc *atac = chp->ch_atac; 657 658 ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS); 659 memset(&ata_c, 0, sizeof(struct ata_command)); 660 661 ata_c.r_command = SET_FEATURES; 662 ata_c.r_st_bmask = 0; 663 ata_c.r_st_pmask = 0; 664 ata_c.r_features = WDSF_SET_MODE; 665 ata_c.r_count = mode; 666 ata_c.flags = flags; 667 ata_c.timeout = 1000; /* 1s */ 668 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp, 669 &ata_c) != ATACMD_COMPLETE) 670 return CMD_AGAIN; 671 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 672 return CMD_ERR; 673 } 674 return CMD_OK; 675 } 676 677 #if NATA_DMA 678 void 679 ata_dmaerr(struct ata_drive_datas *drvp, int flags) 680 { 681 /* 682 * Downgrade decision: if we get NERRS_MAX in NXFER. 683 * We start with n_dmaerrs set to NERRS_MAX-1 so that the 684 * first error within the first NXFER ops will immediatly trigger 685 * a downgrade. 686 * If we got an error and n_xfers is bigger than NXFER reset counters. 687 */ 688 drvp->n_dmaerrs++; 689 if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) { 690 ata_downgrade_mode(drvp, flags); 691 drvp->n_dmaerrs = NERRS_MAX-1; 692 drvp->n_xfers = 0; 693 return; 694 } 695 if (drvp->n_xfers > NXFER) { 696 drvp->n_dmaerrs = 1; /* just got an error */ 697 drvp->n_xfers = 1; /* restart counting from this error */ 698 } 699 } 700 #endif /* NATA_DMA */ 701 702 /* 703 * freeze the queue and wait for the controller to be idle. Caller has to 704 * unfreeze/restart the queue 705 */ 706 void 707 ata_queue_idle(struct ata_queue *queue) 708 { 709 int s = splbio(); 710 queue->queue_freeze++; 711 while (queue->active_xfer != NULL) { 712 queue->queue_flags |= QF_IDLE_WAIT; 713 tsleep(&queue->queue_flags, PRIBIO, "qidl", 0); 714 } 715 splx(s); 716 } 717 718 /* 719 * Add a command to the queue and start controller. 720 * 721 * MUST BE CALLED AT splbio()! 722 */ 723 void 724 ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 725 { 726 727 ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer, 728 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 729 730 /* complete xfer setup */ 731 xfer->c_chp = chp; 732 733 /* insert at the end of command list */ 734 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 735 ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n", 736 chp->ch_flags), DEBUG_XFERS); 737 /* 738 * if polling and can sleep, wait for the xfer to be at head of queue 739 */ 740 if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) { 741 while (chp->ch_queue->active_xfer != NULL || 742 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) { 743 xfer->c_flags |= C_WAITACT; 744 tsleep(xfer, PRIBIO, "ataact", 0); 745 xfer->c_flags &= ~C_WAITACT; 746 if (xfer->c_flags & C_FREE) { 747 ata_free_xfer(chp, xfer); 748 return; 749 } 750 } 751 } 752 atastart(chp); 753 } 754 755 /* 756 * Start I/O on a controller, for the given channel. 757 * The first xfer may be not for our channel if the channel queues 758 * are shared. 759 * 760 * MUST BE CALLED AT splbio()! 761 */ 762 void 763 atastart(struct ata_channel *chp) 764 { 765 struct atac_softc *atac = chp->ch_atac; 766 struct ata_xfer *xfer; 767 768 #ifdef ATA_DEBUG 769 int spl1, spl2; 770 771 spl1 = splbio(); 772 spl2 = splbio(); 773 if (spl2 != spl1) { 774 printf("atastart: not at splbio()\n"); 775 panic("atastart"); 776 } 777 splx(spl2); 778 splx(spl1); 779 #endif /* ATA_DEBUG */ 780 781 /* is there a xfer ? */ 782 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 783 return; 784 785 /* adjust chp, in case we have a shared queue */ 786 chp = xfer->c_chp; 787 788 if (chp->ch_queue->active_xfer != NULL) { 789 return; /* channel aleady active */ 790 } 791 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 792 if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) { 793 chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT; 794 wakeup(&chp->ch_queue->queue_flags); 795 } 796 return; /* queue frozen */ 797 } 798 /* 799 * if someone is waiting for the command to be active, wake it up 800 * and let it process the command 801 */ 802 if (xfer->c_flags & C_WAITACT) { 803 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d " 804 "wait active\n", xfer, chp->ch_channel, xfer->c_drive), 805 DEBUG_XFERS); 806 wakeup(xfer); 807 return; 808 } 809 #ifdef DIAGNOSTIC 810 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) 811 panic("atastart: channel waiting for irq"); 812 #endif 813 if (atac->atac_claim_hw) 814 if (!(*atac->atac_claim_hw)(chp, 0)) 815 return; 816 817 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer, 818 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 819 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 820 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 821 chp->ch_drive[xfer->c_drive].state = 0; 822 } 823 chp->ch_queue->active_xfer = xfer; 824 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 825 826 if (atac->atac_cap & ATAC_CAP_NOIRQ) 827 KASSERT(xfer->c_flags & C_POLL); 828 829 xfer->c_start(chp, xfer); 830 } 831 832 struct ata_xfer * 833 ata_get_xfer(int flags) 834 { 835 struct ata_xfer *xfer; 836 int s; 837 838 s = splbio(); 839 xfer = pool_get(&ata_xfer_pool, 840 ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 841 splx(s); 842 if (xfer != NULL) { 843 memset(xfer, 0, sizeof(struct ata_xfer)); 844 } 845 return xfer; 846 } 847 848 void 849 ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer) 850 { 851 struct atac_softc *atac = chp->ch_atac; 852 int s; 853 854 if (xfer->c_flags & C_WAITACT) { 855 /* Someone is waiting for this xfer, so we can't free now */ 856 xfer->c_flags |= C_FREE; 857 wakeup(xfer); 858 return; 859 } 860 861 #if NATA_PIOBM /* XXX wdc dependent code */ 862 if (xfer->c_flags & C_PIOBM) { 863 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 864 865 /* finish the busmastering PIO */ 866 (*wdc->piobm_done)(wdc->dma_arg, 867 chp->ch_channel, xfer->c_drive); 868 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT); 869 } 870 #endif 871 872 if (atac->atac_free_hw) 873 (*atac->atac_free_hw)(chp); 874 s = splbio(); 875 pool_put(&ata_xfer_pool, xfer); 876 splx(s); 877 } 878 879 /* 880 * Kill off all pending xfers for a ata_channel. 881 * 882 * Must be called at splbio(). 883 */ 884 void 885 ata_kill_pending(struct ata_drive_datas *drvp) 886 { 887 struct ata_channel *chp = drvp->chnl_softc; 888 struct ata_xfer *xfer, *next_xfer; 889 int s = splbio(); 890 891 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 892 xfer != NULL; xfer = next_xfer) { 893 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 894 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 895 continue; 896 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 897 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 898 } 899 900 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 901 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 902 drvp->drive_flags |= DRIVE_WAITDRAIN; 903 (void) tsleep(&chp->ch_queue->active_xfer, 904 PRIBIO, "atdrn", 0); 905 } else { 906 /* no more xfer for us */ 907 break; 908 } 909 } 910 splx(s); 911 } 912 913 /* 914 * ata_reset_channel: 915 * 916 * Reset and ATA channel. 917 * 918 * MUST BE CALLED AT splbio()! 919 */ 920 void 921 ata_reset_channel(struct ata_channel *chp, int flags) 922 { 923 struct atac_softc *atac = chp->ch_atac; 924 int drive; 925 926 #ifdef ATA_DEBUG 927 int spl1, spl2; 928 929 spl1 = splbio(); 930 spl2 = splbio(); 931 if (spl2 != spl1) { 932 printf("ata_reset_channel: not at splbio()\n"); 933 panic("ata_reset_channel"); 934 } 935 splx(spl2); 936 splx(spl1); 937 #endif /* ATA_DEBUG */ 938 939 chp->ch_queue->queue_freeze++; 940 941 /* 942 * If we can poll or wait it's OK, otherwise wake up the 943 * kernel thread to do it for us. 944 */ 945 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 946 if (chp->ch_flags & ATACH_TH_RESET) { 947 /* No need to schedule a reset more than one time. */ 948 chp->ch_queue->queue_freeze--; 949 return; 950 } 951 chp->ch_flags |= ATACH_TH_RESET; 952 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 953 wakeup(&chp->ch_thread); 954 return; 955 } 956 957 (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags); 958 959 for (drive = 0; drive < chp->ch_ndrive; drive++) 960 chp->ch_drive[drive].state = 0; 961 962 chp->ch_flags &= ~ATACH_TH_RESET; 963 if ((flags & AT_RST_EMERG) == 0) { 964 chp->ch_queue->queue_freeze--; 965 atastart(chp); 966 } else { 967 /* make sure that we can use polled commands */ 968 TAILQ_INIT(&chp->ch_queue->queue_xfer); 969 chp->ch_queue->queue_freeze = 0; 970 chp->ch_queue->active_xfer = NULL; 971 } 972 } 973 974 int 975 ata_addref(struct ata_channel *chp) 976 { 977 struct atac_softc *atac = chp->ch_atac; 978 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 979 int s, error = 0; 980 981 s = splbio(); 982 if (adapt->adapt_refcnt++ == 0 && 983 adapt->adapt_enable != NULL) { 984 error = (*adapt->adapt_enable)(&atac->atac_dev, 1); 985 if (error) 986 adapt->adapt_refcnt--; 987 } 988 splx(s); 989 return (error); 990 } 991 992 void 993 ata_delref(struct ata_channel *chp) 994 { 995 struct atac_softc *atac = chp->ch_atac; 996 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 997 int s; 998 999 s = splbio(); 1000 if (adapt->adapt_refcnt-- == 1 && 1001 adapt->adapt_enable != NULL) 1002 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 1003 splx(s); 1004 } 1005 1006 void 1007 ata_print_modes(struct ata_channel *chp) 1008 { 1009 struct atac_softc *atac = chp->ch_atac; 1010 int drive; 1011 struct ata_drive_datas *drvp; 1012 1013 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1014 drvp = &chp->ch_drive[drive]; 1015 if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL) 1016 continue; 1017 aprint_verbose("%s(%s:%d:%d): using PIO mode %d", 1018 drvp->drv_softc->dv_xname, 1019 atac->atac_dev.dv_xname, 1020 chp->ch_channel, drvp->drive, drvp->PIO_mode); 1021 #if NATA_DMA 1022 if (drvp->drive_flags & DRIVE_DMA) 1023 aprint_verbose(", DMA mode %d", drvp->DMA_mode); 1024 #if NATA_UDMA 1025 if (drvp->drive_flags & DRIVE_UDMA) { 1026 aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode); 1027 if (drvp->UDMA_mode == 2) 1028 aprint_verbose(" (Ultra/33)"); 1029 else if (drvp->UDMA_mode == 4) 1030 aprint_verbose(" (Ultra/66)"); 1031 else if (drvp->UDMA_mode == 5) 1032 aprint_verbose(" (Ultra/100)"); 1033 else if (drvp->UDMA_mode == 6) 1034 aprint_verbose(" (Ultra/133)"); 1035 } 1036 #endif /* NATA_UDMA */ 1037 #endif /* NATA_DMA */ 1038 #if NATA_DMA || NATA_PIOBM 1039 if (0 1040 #if NATA_DMA 1041 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1042 #endif 1043 #if NATA_PIOBM 1044 /* PIOBM capable controllers use DMA for PIO commands */ 1045 || (atac->atac_cap & ATAC_CAP_PIOBM) 1046 #endif 1047 ) 1048 aprint_verbose(" (using DMA)"); 1049 #endif /* NATA_DMA || NATA_PIOBM */ 1050 aprint_verbose("\n"); 1051 } 1052 } 1053 1054 #if NATA_DMA 1055 /* 1056 * downgrade the transfer mode of a drive after an error. return 1 if 1057 * downgrade was possible, 0 otherwise. 1058 * 1059 * MUST BE CALLED AT splbio()! 1060 */ 1061 int 1062 ata_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1063 { 1064 struct ata_channel *chp = drvp->chnl_softc; 1065 struct atac_softc *atac = chp->ch_atac; 1066 struct device *drv_dev = drvp->drv_softc; 1067 int cf_flags = device_cfdata(drv_dev)->cf_flags; 1068 1069 /* if drive or controller don't know its mode, we can't do much */ 1070 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1071 (atac->atac_set_modes == NULL)) 1072 return 0; 1073 /* current drive mode was set by a config flag, let it this way */ 1074 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1075 (cf_flags & ATA_CONFIG_DMA_SET) || 1076 (cf_flags & ATA_CONFIG_UDMA_SET)) 1077 return 0; 1078 1079 #if NATA_UDMA 1080 /* 1081 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1082 */ 1083 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1084 drvp->UDMA_mode--; 1085 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1086 drv_dev->dv_xname, drvp->UDMA_mode); 1087 } 1088 #endif 1089 1090 /* 1091 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1092 */ 1093 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1094 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1095 drvp->PIO_mode = drvp->PIO_cap; 1096 printf("%s: transfer error, downgrading to PIO mode %d\n", 1097 drv_dev->dv_xname, drvp->PIO_mode); 1098 } else /* already using PIO, can't downgrade */ 1099 return 0; 1100 1101 (*atac->atac_set_modes)(chp); 1102 ata_print_modes(chp); 1103 /* reset the channel, which will schedule all drives for setup */ 1104 ata_reset_channel(chp, flags | AT_RST_NOCMD); 1105 return 1; 1106 } 1107 #endif /* NATA_DMA */ 1108 1109 /* 1110 * Probe drive's capabilities, for use by the controller later 1111 * Assumes drvp points to an existing drive. 1112 */ 1113 void 1114 ata_probe_caps(struct ata_drive_datas *drvp) 1115 { 1116 struct ataparams params, params2; 1117 struct ata_channel *chp = drvp->chnl_softc; 1118 struct atac_softc *atac = chp->ch_atac; 1119 struct device *drv_dev = drvp->drv_softc; 1120 int i, printed, s; 1121 const char *sep = ""; 1122 int cf_flags; 1123 1124 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1125 /* IDENTIFY failed. Can't tell more about the device */ 1126 return; 1127 } 1128 if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == 1129 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 1130 /* 1131 * Controller claims 16 and 32 bit transfers. 1132 * Re-do an IDENTIFY with 32-bit transfers, 1133 * and compare results. 1134 */ 1135 s = splbio(); 1136 drvp->drive_flags |= DRIVE_CAP32; 1137 splx(s); 1138 ata_get_params(drvp, AT_WAIT, ¶ms2); 1139 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1140 /* Not good. fall back to 16bits */ 1141 s = splbio(); 1142 drvp->drive_flags &= ~DRIVE_CAP32; 1143 splx(s); 1144 } else { 1145 aprint_verbose("%s: 32-bit data port\n", 1146 drv_dev->dv_xname); 1147 } 1148 } 1149 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1150 if (params.atap_ata_major > 0x01 && 1151 params.atap_ata_major != 0xffff) { 1152 for (i = 14; i > 0; i--) { 1153 if (params.atap_ata_major & (1 << i)) { 1154 aprint_verbose("%s: ATA version %d\n", 1155 drv_dev->dv_xname, i); 1156 drvp->ata_vers = i; 1157 break; 1158 } 1159 } 1160 } 1161 #endif 1162 1163 /* An ATAPI device is at last PIO mode 3 */ 1164 if (drvp->drive_flags & DRIVE_ATAPI) 1165 drvp->PIO_mode = 3; 1166 1167 /* 1168 * It's not in the specs, but it seems that some drive 1169 * returns 0xffff in atap_extensions when this field is invalid 1170 */ 1171 if (params.atap_extensions != 0xffff && 1172 (params.atap_extensions & WDC_EXT_MODES)) { 1173 printed = 0; 1174 /* 1175 * XXX some drives report something wrong here (they claim to 1176 * support PIO mode 8 !). As mode is coded on 3 bits in 1177 * SET FEATURE, limit it to 7 (so limit i to 4). 1178 * If higher mode than 7 is found, abort. 1179 */ 1180 for (i = 7; i >= 0; i--) { 1181 if ((params.atap_piomode_supp & (1 << i)) == 0) 1182 continue; 1183 if (i > 4) 1184 return; 1185 /* 1186 * See if mode is accepted. 1187 * If the controller can't set its PIO mode, 1188 * assume the defaults are good, so don't try 1189 * to set it 1190 */ 1191 if (atac->atac_set_modes) 1192 /* 1193 * It's OK to pool here, it's fast enouth 1194 * to not bother waiting for interrupt 1195 */ 1196 if (ata_set_mode(drvp, 0x08 | (i + 3), 1197 AT_WAIT) != CMD_OK) 1198 continue; 1199 if (!printed) { 1200 aprint_verbose("%s: drive supports PIO mode %d", 1201 drv_dev->dv_xname, i + 3); 1202 sep = ","; 1203 printed = 1; 1204 } 1205 /* 1206 * If controller's driver can't set its PIO mode, 1207 * get the highter one for the drive. 1208 */ 1209 if (atac->atac_set_modes == NULL || 1210 atac->atac_pio_cap >= i + 3) { 1211 drvp->PIO_mode = i + 3; 1212 drvp->PIO_cap = i + 3; 1213 break; 1214 } 1215 } 1216 if (!printed) { 1217 /* 1218 * We didn't find a valid PIO mode. 1219 * Assume the values returned for DMA are buggy too 1220 */ 1221 return; 1222 } 1223 s = splbio(); 1224 drvp->drive_flags |= DRIVE_MODE; 1225 splx(s); 1226 printed = 0; 1227 for (i = 7; i >= 0; i--) { 1228 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1229 continue; 1230 #if NATA_DMA 1231 if ((atac->atac_cap & ATAC_CAP_DMA) && 1232 atac->atac_set_modes != NULL) 1233 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1234 != CMD_OK) 1235 continue; 1236 #endif 1237 if (!printed) { 1238 aprint_verbose("%s DMA mode %d", sep, i); 1239 sep = ","; 1240 printed = 1; 1241 } 1242 #if NATA_DMA 1243 if (atac->atac_cap & ATAC_CAP_DMA) { 1244 if (atac->atac_set_modes != NULL && 1245 atac->atac_dma_cap < i) 1246 continue; 1247 drvp->DMA_mode = i; 1248 drvp->DMA_cap = i; 1249 s = splbio(); 1250 drvp->drive_flags |= DRIVE_DMA; 1251 splx(s); 1252 } 1253 #endif 1254 break; 1255 } 1256 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1257 printed = 0; 1258 for (i = 7; i >= 0; i--) { 1259 if ((params.atap_udmamode_supp & (1 << i)) 1260 == 0) 1261 continue; 1262 #if NATA_UDMA 1263 if (atac->atac_set_modes != NULL && 1264 (atac->atac_cap & ATAC_CAP_UDMA)) 1265 if (ata_set_mode(drvp, 0x40 | i, 1266 AT_WAIT) != CMD_OK) 1267 continue; 1268 #endif 1269 if (!printed) { 1270 aprint_verbose("%s Ultra-DMA mode %d", 1271 sep, i); 1272 if (i == 2) 1273 aprint_verbose(" (Ultra/33)"); 1274 else if (i == 4) 1275 aprint_verbose(" (Ultra/66)"); 1276 else if (i == 5) 1277 aprint_verbose(" (Ultra/100)"); 1278 else if (i == 6) 1279 aprint_verbose(" (Ultra/133)"); 1280 sep = ","; 1281 printed = 1; 1282 } 1283 #if NATA_UDMA 1284 if (atac->atac_cap & ATAC_CAP_UDMA) { 1285 if (atac->atac_set_modes != NULL && 1286 atac->atac_udma_cap < i) 1287 continue; 1288 drvp->UDMA_mode = i; 1289 drvp->UDMA_cap = i; 1290 s = splbio(); 1291 drvp->drive_flags |= DRIVE_UDMA; 1292 splx(s); 1293 } 1294 #endif 1295 break; 1296 } 1297 } 1298 aprint_verbose("\n"); 1299 } 1300 1301 s = splbio(); 1302 drvp->drive_flags &= ~DRIVE_NOSTREAM; 1303 if (drvp->drive_flags & DRIVE_ATAPI) { 1304 if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM) 1305 drvp->drive_flags |= DRIVE_NOSTREAM; 1306 } else { 1307 if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM) 1308 drvp->drive_flags |= DRIVE_NOSTREAM; 1309 } 1310 splx(s); 1311 1312 /* Try to guess ATA version here, if it didn't get reported */ 1313 if (drvp->ata_vers == 0) { 1314 #if NATA_UDMA 1315 if (drvp->drive_flags & DRIVE_UDMA) 1316 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1317 else 1318 #endif 1319 if (drvp->PIO_cap > 2) 1320 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1321 } 1322 cf_flags = device_cfdata(drv_dev)->cf_flags; 1323 if (cf_flags & ATA_CONFIG_PIO_SET) { 1324 s = splbio(); 1325 drvp->PIO_mode = 1326 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1327 drvp->drive_flags |= DRIVE_MODE; 1328 splx(s); 1329 } 1330 #if NATA_DMA 1331 if ((atac->atac_cap & ATAC_CAP_DMA) == 0) { 1332 /* don't care about DMA modes */ 1333 return; 1334 } 1335 if (cf_flags & ATA_CONFIG_DMA_SET) { 1336 s = splbio(); 1337 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1338 ATA_CONFIG_DMA_DISABLE) { 1339 drvp->drive_flags &= ~DRIVE_DMA; 1340 } else { 1341 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1342 ATA_CONFIG_DMA_OFF; 1343 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1344 } 1345 splx(s); 1346 } 1347 #if NATA_UDMA 1348 if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) { 1349 /* don't care about UDMA modes */ 1350 return; 1351 } 1352 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1353 s = splbio(); 1354 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1355 ATA_CONFIG_UDMA_DISABLE) { 1356 drvp->drive_flags &= ~DRIVE_UDMA; 1357 } else { 1358 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1359 ATA_CONFIG_UDMA_OFF; 1360 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1361 } 1362 splx(s); 1363 } 1364 #endif /* NATA_UDMA */ 1365 #endif /* NATA_DMA */ 1366 } 1367 1368 /* management of the /dev/atabus* devices */ 1369 int 1370 atabusopen(dev_t dev, int flag, int fmt, 1371 struct lwp *l) 1372 { 1373 struct atabus_softc *sc; 1374 int error, unit = minor(dev); 1375 1376 if (unit >= atabus_cd.cd_ndevs || 1377 (sc = atabus_cd.cd_devs[unit]) == NULL) 1378 return (ENXIO); 1379 1380 if (sc->sc_flags & ATABUSCF_OPEN) 1381 return (EBUSY); 1382 1383 if ((error = ata_addref(sc->sc_chan)) != 0) 1384 return (error); 1385 1386 sc->sc_flags |= ATABUSCF_OPEN; 1387 1388 return (0); 1389 } 1390 1391 1392 int 1393 atabusclose(dev_t dev, int flag, int fmt, 1394 struct lwp *l) 1395 { 1396 struct atabus_softc *sc = atabus_cd.cd_devs[minor(dev)]; 1397 1398 ata_delref(sc->sc_chan); 1399 1400 sc->sc_flags &= ~ATABUSCF_OPEN; 1401 1402 return (0); 1403 } 1404 1405 int 1406 atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, 1407 struct lwp *l) 1408 { 1409 struct atabus_softc *sc = atabus_cd.cd_devs[minor(dev)]; 1410 struct ata_channel *chp = sc->sc_chan; 1411 int min_drive, max_drive, drive; 1412 int error; 1413 int s; 1414 1415 /* 1416 * Enforce write permission for ioctls that change the 1417 * state of the bus. Host adapter specific ioctls must 1418 * be checked by the adapter driver. 1419 */ 1420 switch (cmd) { 1421 case ATABUSIOSCAN: 1422 case ATABUSIODETACH: 1423 case ATABUSIORESET: 1424 if ((flag & FWRITE) == 0) 1425 return (EBADF); 1426 } 1427 1428 switch (cmd) { 1429 case ATABUSIORESET: 1430 s = splbio(); 1431 ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL); 1432 splx(s); 1433 error = 0; 1434 break; 1435 case ATABUSIOSCAN: 1436 { 1437 #if 0 1438 struct atabusioscan_args *a= 1439 (struct atabusioscan_args *)addr; 1440 #endif 1441 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1442 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1443 return (EOPNOTSUPP); 1444 return (EOPNOTSUPP); 1445 } 1446 case ATABUSIODETACH: 1447 { 1448 struct atabusioscan_args *a= 1449 (struct atabusioscan_args *)addr; 1450 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) || 1451 (chp->ch_drive[1].drive_flags & DRIVE_OLD)) 1452 return (EOPNOTSUPP); 1453 switch (a->at_dev) { 1454 case -1: 1455 min_drive = 0; 1456 max_drive = 1; 1457 break; 1458 case 0: 1459 case 1: 1460 min_drive = max_drive = a->at_dev; 1461 break; 1462 default: 1463 return (EINVAL); 1464 } 1465 for (drive = min_drive; drive <= max_drive; drive++) { 1466 if (chp->ch_drive[drive].drv_softc != NULL) { 1467 error = config_detach( 1468 chp->ch_drive[drive].drv_softc, 0); 1469 if (error) 1470 return (error); 1471 chp->ch_drive[drive].drv_softc = NULL; 1472 } 1473 } 1474 error = 0; 1475 break; 1476 } 1477 default: 1478 error = ENOTTY; 1479 } 1480 return (error); 1481 }; 1482 1483 static bool 1484 atabus_suspend(device_t dv) 1485 { 1486 struct atabus_softc *sc = device_private(dv); 1487 struct ata_channel *chp = sc->sc_chan; 1488 1489 ata_queue_idle(chp->ch_queue); 1490 1491 return true; 1492 } 1493 1494 static bool 1495 atabus_resume(device_t dv) 1496 { 1497 struct atabus_softc *sc = device_private(dv); 1498 struct ata_channel *chp = sc->sc_chan; 1499 int s; 1500 1501 /* 1502 * XXX joerg: with wdc, the first channel unfreezes the controler. 1503 * Move this the reset and queue idling into wdc. 1504 */ 1505 s = splbio(); 1506 if (chp->ch_queue->queue_freeze == 0) { 1507 splx(s); 1508 return true; 1509 } 1510 KASSERT(chp->ch_queue->queue_freeze > 0); 1511 /* unfreeze the queue and reset drives */ 1512 chp->ch_queue->queue_freeze--; 1513 ata_reset_channel(chp, AT_WAIT); 1514 splx(s); 1515 1516 return true; 1517 } 1518
Indexes created Wed Sep 24 22:09:59 GMT 2025