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ata_wdc.c revision 1.39.2.10
      1  1.39.2.10     skrll /*	$NetBSD: ata_wdc.c,v 1.39.2.10 2005/11/10 14:03:54 skrll Exp $	*/
      2        1.2    bouyer 
      3        1.2    bouyer /*
      4   1.39.2.1     skrll  * Copyright (c) 1998, 2001, 2003 Manuel Bouyer.
      5        1.2    bouyer  *
      6        1.2    bouyer  * Redistribution and use in source and binary forms, with or without
      7        1.2    bouyer  * modification, are permitted provided that the following conditions
      8        1.2    bouyer  * are met:
      9        1.2    bouyer  * 1. Redistributions of source code must retain the above copyright
     10        1.2    bouyer  *    notice, this list of conditions and the following disclaimer.
     11        1.2    bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     12        1.2    bouyer  *    notice, this list of conditions and the following disclaimer in the
     13        1.2    bouyer  *    documentation and/or other materials provided with the distribution.
     14        1.2    bouyer  * 3. All advertising materials mentioning features or use of this software
     15        1.2    bouyer  *    must display the following acknowledgement:
     16       1.36    bouyer  *	This product includes software developed by Manuel Bouyer.
     17   1.39.2.1     skrll  * 4. The name of the author may not be used to endorse or promote products
     18   1.39.2.1     skrll  *    derived from this software without specific prior written permission.
     19        1.2    bouyer  *
     20       1.27    bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21       1.27    bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22       1.27    bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23   1.39.2.9     skrll  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24       1.27    bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25       1.27    bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26       1.27    bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27       1.27    bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28       1.27    bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29       1.27    bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30        1.2    bouyer  */
     31        1.2    bouyer 
     32        1.2    bouyer /*-
     33   1.39.2.1     skrll  * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc.
     34        1.2    bouyer  * All rights reserved.
     35        1.2    bouyer  *
     36        1.2    bouyer  * This code is derived from software contributed to The NetBSD Foundation
     37        1.2    bouyer  * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
     38        1.2    bouyer  *
     39        1.2    bouyer  * Redistribution and use in source and binary forms, with or without
     40        1.2    bouyer  * modification, are permitted provided that the following conditions
     41        1.2    bouyer  * are met:
     42        1.2    bouyer  * 1. Redistributions of source code must retain the above copyright
     43        1.2    bouyer  *    notice, this list of conditions and the following disclaimer.
     44        1.2    bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     45        1.2    bouyer  *    notice, this list of conditions and the following disclaimer in the
     46        1.2    bouyer  *    documentation and/or other materials provided with the distribution.
     47        1.2    bouyer  * 3. All advertising materials mentioning features or use of this software
     48        1.2    bouyer  *    must display the following acknowledgement:
     49        1.2    bouyer  *        This product includes software developed by the NetBSD
     50        1.2    bouyer  *        Foundation, Inc. and its contributors.
     51        1.2    bouyer  * 4. Neither the name of The NetBSD Foundation nor the names of its
     52        1.2    bouyer  *    contributors may be used to endorse or promote products derived
     53        1.2    bouyer  *    from this software without specific prior written permission.
     54        1.2    bouyer  *
     55        1.2    bouyer  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     56        1.2    bouyer  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     57        1.2    bouyer  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     58        1.2    bouyer  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     59        1.2    bouyer  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     60        1.2    bouyer  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     61        1.2    bouyer  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     62        1.2    bouyer  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     63        1.2    bouyer  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     64        1.2    bouyer  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     65        1.2    bouyer  * POSSIBILITY OF SUCH DAMAGE.
     66        1.2    bouyer  */
     67       1.31     lukem 
     68       1.31     lukem #include <sys/cdefs.h>
     69  1.39.2.10     skrll __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.39.2.10 2005/11/10 14:03:54 skrll Exp $");
     70        1.2    bouyer 
     71   1.39.2.3     skrll #ifndef ATADEBUG
     72   1.39.2.3     skrll #define ATADEBUG
     73   1.39.2.3     skrll #endif /* ATADEBUG */
     74        1.2    bouyer 
     75        1.2    bouyer #include <sys/param.h>
     76        1.2    bouyer #include <sys/systm.h>
     77        1.2    bouyer #include <sys/kernel.h>
     78        1.2    bouyer #include <sys/file.h>
     79        1.2    bouyer #include <sys/stat.h>
     80        1.2    bouyer #include <sys/buf.h>
     81   1.39.2.6     skrll #include <sys/bufq.h>
     82        1.2    bouyer #include <sys/malloc.h>
     83        1.2    bouyer #include <sys/device.h>
     84        1.2    bouyer #include <sys/disklabel.h>
     85        1.2    bouyer #include <sys/syslog.h>
     86        1.2    bouyer #include <sys/proc.h>
     87        1.2    bouyer 
     88        1.2    bouyer #include <machine/intr.h>
     89        1.2    bouyer #include <machine/bus.h>
     90        1.2    bouyer #ifndef __BUS_SPACE_HAS_STREAM_METHODS
     91        1.2    bouyer #define    bus_space_write_multi_stream_2    bus_space_write_multi_2
     92        1.2    bouyer #define    bus_space_write_multi_stream_4    bus_space_write_multi_4
     93        1.2    bouyer #define    bus_space_read_multi_stream_2    bus_space_read_multi_2
     94        1.2    bouyer #define    bus_space_read_multi_stream_4    bus_space_read_multi_4
     95        1.2    bouyer #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
     96        1.2    bouyer 
     97        1.2    bouyer #include <dev/ata/atareg.h>
     98        1.2    bouyer #include <dev/ata/atavar.h>
     99        1.2    bouyer #include <dev/ic/wdcreg.h>
    100        1.2    bouyer #include <dev/ic/wdcvar.h>
    101        1.2    bouyer 
    102        1.2    bouyer #define DEBUG_INTR   0x01
    103        1.2    bouyer #define DEBUG_XFERS  0x02
    104        1.2    bouyer #define DEBUG_STATUS 0x04
    105        1.2    bouyer #define DEBUG_FUNCS  0x08
    106        1.2    bouyer #define DEBUG_PROBE  0x10
    107   1.39.2.3     skrll #ifdef ATADEBUG
    108   1.39.2.1     skrll extern int wdcdebug_wd_mask; /* inited in wd.c */
    109   1.39.2.3     skrll #define ATADEBUG_PRINT(args, level) \
    110        1.2    bouyer 	if (wdcdebug_wd_mask & (level)) \
    111        1.2    bouyer 		printf args
    112        1.2    bouyer #else
    113   1.39.2.3     skrll #define ATADEBUG_PRINT(args, level)
    114        1.2    bouyer #endif
    115        1.2    bouyer 
    116       1.17    bouyer #define ATA_DELAY 10000 /* 10s for a drive I/O */
    117        1.2    bouyer 
    118   1.39.2.1     skrll static int	wdc_ata_bio(struct ata_drive_datas*, struct ata_bio*);
    119   1.39.2.3     skrll static void	wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *);
    120   1.39.2.3     skrll static void	_wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *);
    121   1.39.2.3     skrll static int	wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *,
    122   1.39.2.1     skrll 				 int);
    123   1.39.2.3     skrll static void	wdc_ata_bio_kill_xfer(struct ata_channel *,
    124   1.39.2.1     skrll 				      struct ata_xfer *, int);
    125   1.39.2.9     skrll static void	wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *);
    126   1.39.2.1     skrll static int	wdc_ata_err(struct ata_drive_datas *, struct ata_bio *);
    127        1.2    bouyer #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */
    128        1.2    bouyer #define WDC_ATA_RECOV 0x01 /* There was a recovered error */
    129        1.2    bouyer #define WDC_ATA_ERR   0x02 /* Drive reports an error */
    130   1.39.2.1     skrll static int	wdc_ata_addref(struct ata_drive_datas *);
    131   1.39.2.1     skrll static void	wdc_ata_delref(struct ata_drive_datas *);
    132       1.32    bouyer 
    133       1.32    bouyer const struct ata_bustype wdc_ata_bustype = {
    134       1.32    bouyer 	SCSIPI_BUSTYPE_ATA,
    135       1.32    bouyer 	wdc_ata_bio,
    136   1.39.2.1     skrll 	wdc_reset_drive,
    137   1.39.2.3     skrll 	wdc_reset_channel,
    138       1.32    bouyer 	wdc_exec_command,
    139       1.32    bouyer 	ata_get_params,
    140       1.32    bouyer 	wdc_ata_addref,
    141       1.32    bouyer 	wdc_ata_delref,
    142   1.39.2.3     skrll 	ata_kill_pending,
    143       1.32    bouyer };
    144       1.32    bouyer 
    145        1.2    bouyer /*
    146   1.39.2.2     skrll  * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or
    147   1.39.2.2     skrll  * ATACMD_TRY_AGAIN. Must be called at splbio().
    148        1.2    bouyer  */
    149   1.39.2.1     skrll static int
    150   1.39.2.1     skrll wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
    151        1.2    bouyer {
    152   1.39.2.1     skrll 	struct ata_xfer *xfer;
    153   1.39.2.3     skrll 	struct ata_channel *chp = drvp->chnl_softc;
    154   1.39.2.3     skrll 	struct atac_softc *atac = chp->ch_atac;
    155        1.2    bouyer 
    156   1.39.2.3     skrll 	xfer = ata_get_xfer(ATAXF_NOSLEEP);
    157        1.2    bouyer 	if (xfer == NULL)
    158   1.39.2.2     skrll 		return ATACMD_TRY_AGAIN;
    159   1.39.2.3     skrll 	if (atac->atac_cap & ATAC_CAP_NOIRQ)
    160       1.30     bjh21 		ata_bio->flags |= ATA_POLL;
    161        1.2    bouyer 	if (ata_bio->flags & ATA_POLL)
    162        1.2    bouyer 		xfer->c_flags |= C_POLL;
    163        1.2    bouyer 	if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) &&
    164        1.2    bouyer 	    (ata_bio->flags & ATA_SINGLE) == 0)
    165        1.2    bouyer 		xfer->c_flags |= C_DMA;
    166   1.39.2.1     skrll 	xfer->c_drive = drvp->drive;
    167   1.39.2.1     skrll 	xfer->c_cmd = ata_bio;
    168   1.39.2.1     skrll 	xfer->c_databuf = ata_bio->databuf;
    169        1.2    bouyer 	xfer->c_bcount = ata_bio->bcount;
    170        1.2    bouyer 	xfer->c_start = wdc_ata_bio_start;
    171        1.2    bouyer 	xfer->c_intr = wdc_ata_bio_intr;
    172       1.22     enami 	xfer->c_kill_xfer = wdc_ata_bio_kill_xfer;
    173   1.39.2.3     skrll 	ata_exec_xfer(chp, xfer);
    174   1.39.2.2     skrll 	return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
    175        1.2    bouyer }
    176        1.2    bouyer 
    177   1.39.2.1     skrll static void
    178   1.39.2.3     skrll wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
    179        1.2    bouyer {
    180   1.39.2.3     skrll 	struct atac_softc *atac = chp->ch_atac;
    181   1.39.2.3     skrll 	struct wdc_softc *wdc = CHAN_TO_WDC(chp);
    182   1.39.2.3     skrll 	struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
    183   1.39.2.1     skrll 	struct ata_bio *ata_bio = xfer->c_cmd;
    184   1.39.2.1     skrll 	struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
    185   1.39.2.1     skrll 	int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
    186  1.39.2.10     skrll 	const char *errstring;
    187   1.39.2.1     skrll 
    188   1.39.2.3     skrll 	ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n",
    189   1.39.2.3     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive),
    190       1.20    bouyer 	    DEBUG_XFERS);
    191       1.20    bouyer 
    192   1.39.2.1     skrll 	/* Do control operations specially. */
    193   1.39.2.1     skrll 	if (__predict_false(drvp->state < READY)) {
    194   1.39.2.1     skrll 		/*
    195   1.39.2.1     skrll 		 * Actually, we want to be careful not to mess with the control
    196   1.39.2.1     skrll 		 * state if the device is currently busy, but we can assume
    197   1.39.2.1     skrll 		 * that we never get to this point if that's the case.
    198   1.39.2.1     skrll 		 */
    199  1.39.2.10     skrll 		/* If it's not a polled command, we need the kernel thread */
    200   1.39.2.1     skrll 		if ((xfer->c_flags & C_POLL) == 0 &&
    201   1.39.2.3     skrll 		    (chp->ch_flags & ATACH_TH_RUN) == 0) {
    202   1.39.2.1     skrll 			chp->ch_queue->queue_freeze++;
    203   1.39.2.1     skrll 			wakeup(&chp->ch_thread);
    204   1.39.2.1     skrll 			return;
    205   1.39.2.1     skrll 		}
    206   1.39.2.1     skrll 		/*
    207   1.39.2.1     skrll 		 * disable interrupts, all commands here should be quick
    208   1.39.2.1     skrll 		 * enouth to be able to poll, and we don't go here that often
    209   1.39.2.1     skrll 		 */
    210   1.39.2.3     skrll 		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
    211   1.39.2.1     skrll 		    WDCTL_4BIT | WDCTL_IDS);
    212   1.39.2.3     skrll 		if (wdc->select)
    213   1.39.2.1     skrll 			wdc->select(chp, xfer->c_drive);
    214   1.39.2.3     skrll 		bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
    215   1.39.2.1     skrll 		    WDSD_IBM | (xfer->c_drive << 4));
    216   1.39.2.1     skrll 		DELAY(10);
    217   1.39.2.1     skrll 		errstring = "wait";
    218   1.39.2.1     skrll 		if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags))
    219   1.39.2.1     skrll 			goto ctrltimeout;
    220   1.39.2.1     skrll 		wdccommandshort(chp, xfer->c_drive, WDCC_RECAL);
    221   1.39.2.1     skrll 		/* Wait for at last 400ns for status bit to be valid */
    222   1.39.2.1     skrll 		DELAY(1);
    223   1.39.2.1     skrll 		errstring = "recal";
    224   1.39.2.1     skrll 		if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags))
    225   1.39.2.1     skrll 			goto ctrltimeout;
    226   1.39.2.1     skrll 		if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
    227   1.39.2.1     skrll 			goto ctrlerror;
    228   1.39.2.1     skrll 		/* Don't try to set modes if controller can't be adjusted */
    229   1.39.2.3     skrll 		if (atac->atac_set_modes == NULL)
    230   1.39.2.1     skrll 			goto geometry;
    231   1.39.2.1     skrll 		/* Also don't try if the drive didn't report its mode */
    232   1.39.2.1     skrll 		if ((drvp->drive_flags & DRIVE_MODE) == 0)
    233   1.39.2.1     skrll 			goto geometry;
    234   1.39.2.1     skrll 		wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
    235   1.39.2.1     skrll 		    0x08 | drvp->PIO_mode, WDSF_SET_MODE);
    236   1.39.2.1     skrll 		errstring = "piomode";
    237   1.39.2.1     skrll 		if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags))
    238   1.39.2.1     skrll 			goto ctrltimeout;
    239   1.39.2.1     skrll 		if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
    240   1.39.2.1     skrll 			goto ctrlerror;
    241   1.39.2.1     skrll 		if (drvp->drive_flags & DRIVE_UDMA) {
    242   1.39.2.1     skrll 			wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
    243   1.39.2.1     skrll 			    0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
    244   1.39.2.1     skrll 		} else if (drvp->drive_flags & DRIVE_DMA) {
    245   1.39.2.1     skrll 			wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
    246   1.39.2.1     skrll 			    0x20 | drvp->DMA_mode, WDSF_SET_MODE);
    247   1.39.2.1     skrll 		} else {
    248   1.39.2.1     skrll 			goto geometry;
    249   1.39.2.9     skrll 		}
    250   1.39.2.1     skrll 		errstring = "dmamode";
    251   1.39.2.1     skrll 		if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags))
    252   1.39.2.1     skrll 			goto ctrltimeout;
    253   1.39.2.1     skrll 		if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
    254   1.39.2.1     skrll 			goto ctrlerror;
    255   1.39.2.1     skrll geometry:
    256   1.39.2.1     skrll 		if (ata_bio->flags & ATA_LBA)
    257   1.39.2.1     skrll 			goto multimode;
    258   1.39.2.1     skrll 		wdccommand(chp, xfer->c_drive, WDCC_IDP,
    259   1.39.2.1     skrll 		    ata_bio->lp->d_ncylinders,
    260   1.39.2.1     skrll 		    ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors,
    261   1.39.2.1     skrll 		    (ata_bio->lp->d_type == DTYPE_ST506) ?
    262   1.39.2.1     skrll 			ata_bio->lp->d_precompcyl / 4 : 0);
    263   1.39.2.1     skrll 		errstring = "geometry";
    264   1.39.2.1     skrll 		if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags))
    265   1.39.2.1     skrll 			goto ctrltimeout;
    266   1.39.2.1     skrll 		if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
    267   1.39.2.1     skrll 			goto ctrlerror;
    268   1.39.2.1     skrll multimode:
    269   1.39.2.1     skrll 		if (ata_bio->multi == 1)
    270   1.39.2.1     skrll 			goto ready;
    271   1.39.2.1     skrll 		wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0,
    272   1.39.2.1     skrll 		    ata_bio->multi, 0);
    273   1.39.2.1     skrll 		errstring = "setmulti";
    274   1.39.2.1     skrll 		if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags))
    275   1.39.2.1     skrll 			goto ctrltimeout;
    276   1.39.2.1     skrll 		if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
    277   1.39.2.1     skrll 			goto ctrlerror;
    278   1.39.2.1     skrll ready:
    279   1.39.2.1     skrll 		drvp->state = READY;
    280   1.39.2.1     skrll 		/*
    281   1.39.2.1     skrll 		 * The drive is usable now
    282   1.39.2.1     skrll 		 */
    283   1.39.2.3     skrll 		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
    284   1.39.2.1     skrll 		    WDCTL_4BIT);
    285   1.39.2.1     skrll 		delay(10); /* some drives need a little delay here */
    286   1.39.2.1     skrll 	}
    287   1.39.2.1     skrll 
    288       1.20    bouyer 	_wdc_ata_bio_start(chp, xfer);
    289   1.39.2.1     skrll 	return;
    290   1.39.2.1     skrll ctrltimeout:
    291   1.39.2.1     skrll 	printf("%s:%d:%d: %s timed out\n",
    292   1.39.2.3     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
    293   1.39.2.1     skrll 	    errstring);
    294   1.39.2.1     skrll 	ata_bio->error = TIMEOUT;
    295   1.39.2.1     skrll 	goto ctrldone;
    296   1.39.2.1     skrll ctrlerror:
    297   1.39.2.1     skrll 	printf("%s:%d:%d: %s ",
    298   1.39.2.3     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
    299   1.39.2.1     skrll 	    errstring);
    300   1.39.2.1     skrll 	if (chp->ch_status & WDCS_DWF) {
    301   1.39.2.1     skrll 		printf("drive fault\n");
    302   1.39.2.1     skrll 		ata_bio->error = ERR_DF;
    303   1.39.2.1     skrll 	} else {
    304   1.39.2.1     skrll 		printf("error (%x)\n", chp->ch_error);
    305   1.39.2.1     skrll 		ata_bio->r_error = chp->ch_error;
    306   1.39.2.1     skrll 		ata_bio->error = ERROR;
    307   1.39.2.1     skrll 	}
    308   1.39.2.1     skrll ctrldone:
    309   1.39.2.1     skrll 	drvp->state = 0;
    310   1.39.2.1     skrll 	wdc_ata_bio_done(chp, xfer);
    311   1.39.2.3     skrll 	bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
    312   1.39.2.1     skrll 	return;
    313       1.20    bouyer }
    314       1.20    bouyer 
    315   1.39.2.1     skrll static void
    316   1.39.2.3     skrll _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
    317       1.20    bouyer {
    318   1.39.2.3     skrll 	struct atac_softc *atac = chp->ch_atac;
    319   1.39.2.3     skrll 	struct wdc_softc *wdc = CHAN_TO_WDC(chp);
    320   1.39.2.3     skrll 	struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
    321   1.39.2.1     skrll 	struct ata_bio *ata_bio = xfer->c_cmd;
    322   1.39.2.1     skrll 	struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
    323   1.39.2.1     skrll 	int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
    324        1.2    bouyer 	u_int16_t cyl;
    325        1.2    bouyer 	u_int8_t head, sect, cmd = 0;
    326  1.39.2.10     skrll 	int nblks, error;
    327        1.2    bouyer 	int dma_flags = 0;
    328        1.2    bouyer 
    329   1.39.2.3     skrll 	ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n",
    330   1.39.2.3     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive),
    331       1.20    bouyer 	    DEBUG_INTR | DEBUG_XFERS);
    332        1.2    bouyer 
    333        1.2    bouyer 	if (xfer->c_flags & C_DMA) {
    334       1.23    bouyer 		if (drvp->n_xfers <= NXFER)
    335       1.23    bouyer 			drvp->n_xfers++;
    336        1.2    bouyer 		dma_flags = (ata_bio->flags & ATA_READ) ?  WDC_DMA_READ : 0;
    337       1.39  nakayama 		if (ata_bio->flags & ATA_LBA48)
    338       1.39  nakayama 			dma_flags |= WDC_DMA_LBA48;
    339        1.2    bouyer 	}
    340        1.2    bouyer again:
    341        1.2    bouyer 	/*
    342        1.2    bouyer 	 *
    343        1.2    bouyer 	 * When starting a multi-sector transfer, or doing single-sector
    344        1.2    bouyer 	 * transfers...
    345        1.2    bouyer 	 */
    346        1.2    bouyer 	if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) {
    347        1.2    bouyer 		if (ata_bio->flags & ATA_SINGLE)
    348        1.2    bouyer 			nblks = 1;
    349   1.39.2.9     skrll 		else
    350        1.2    bouyer 			nblks = xfer->c_bcount / ata_bio->lp->d_secsize;
    351        1.2    bouyer 		/* Check for bad sectors and adjust transfer, if necessary. */
    352        1.2    bouyer 		if ((ata_bio->lp->d_flags & D_BADSECT) != 0) {
    353        1.2    bouyer 			long blkdiff;
    354        1.2    bouyer 			int i;
    355        1.2    bouyer 			for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1;
    356        1.2    bouyer 			    i++) {
    357        1.2    bouyer 				blkdiff -= ata_bio->blkno;
    358        1.2    bouyer 				if (blkdiff < 0)
    359        1.2    bouyer 					continue;
    360        1.2    bouyer 				if (blkdiff == 0) {
    361        1.2    bouyer 					/* Replace current block of transfer. */
    362        1.2    bouyer 					ata_bio->blkno =
    363        1.2    bouyer 					    ata_bio->lp->d_secperunit -
    364        1.2    bouyer 					    ata_bio->lp->d_nsectors - i - 1;
    365        1.2    bouyer 				}
    366        1.2    bouyer 				if (blkdiff < nblks) {
    367        1.2    bouyer 					/* Bad block inside transfer. */
    368        1.2    bouyer 					ata_bio->flags |= ATA_SINGLE;
    369        1.2    bouyer 					nblks = 1;
    370        1.2    bouyer 				}
    371        1.2    bouyer 				break;
    372        1.2    bouyer 			}
    373        1.2    bouyer 		/* Transfer is okay now. */
    374        1.2    bouyer 		}
    375       1.34  christos 		if (ata_bio->flags & ATA_LBA48) {
    376       1.34  christos 			sect = 0;
    377       1.34  christos 			cyl =  0;
    378       1.34  christos 			head = 0;
    379       1.34  christos 		} else if (ata_bio->flags & ATA_LBA) {
    380        1.2    bouyer 			sect = (ata_bio->blkno >> 0) & 0xff;
    381        1.2    bouyer 			cyl = (ata_bio->blkno >> 8) & 0xffff;
    382        1.2    bouyer 			head = (ata_bio->blkno >> 24) & 0x0f;
    383        1.2    bouyer 			head |= WDSD_LBA;
    384        1.2    bouyer 		} else {
    385        1.2    bouyer 			int blkno = ata_bio->blkno;
    386        1.2    bouyer 			sect = blkno % ata_bio->lp->d_nsectors;
    387        1.2    bouyer 			sect++;    /* Sectors begin with 1, not 0. */
    388        1.2    bouyer 			blkno /= ata_bio->lp->d_nsectors;
    389        1.2    bouyer 			head = blkno % ata_bio->lp->d_ntracks;
    390        1.2    bouyer 			blkno /= ata_bio->lp->d_ntracks;
    391        1.2    bouyer 			cyl = blkno;
    392        1.2    bouyer 			head |= WDSD_CHS;
    393        1.2    bouyer 		}
    394        1.2    bouyer 		if (xfer->c_flags & C_DMA) {
    395        1.2    bouyer 			ata_bio->nblks = nblks;
    396        1.2    bouyer 			ata_bio->nbytes = xfer->c_bcount;
    397        1.2    bouyer 			cmd = (ata_bio->flags & ATA_READ) ?
    398        1.2    bouyer 			    WDCC_READDMA : WDCC_WRITEDMA;
    399        1.2    bouyer 	    		/* Init the DMA channel. */
    400  1.39.2.10     skrll 			error = (*wdc->dma_init)(wdc->dma_arg,
    401   1.39.2.1     skrll 			    chp->ch_channel, xfer->c_drive,
    402   1.39.2.9     skrll 			    (char *)xfer->c_databuf + xfer->c_skip,
    403  1.39.2.10     skrll 			    ata_bio->nbytes, dma_flags);
    404  1.39.2.10     skrll 			if (error) {
    405  1.39.2.10     skrll 				if (error == EINVAL) {
    406  1.39.2.10     skrll 					/*
    407  1.39.2.10     skrll 					 * We can't do DMA on this transfer
    408  1.39.2.10     skrll 					 * for some reason.  Fall back to
    409  1.39.2.10     skrll 					 * PIO.
    410  1.39.2.10     skrll 					 */
    411  1.39.2.10     skrll 					xfer->c_flags &= ~C_DMA;
    412  1.39.2.10     skrll 					error = 0;
    413  1.39.2.10     skrll 					goto do_pio;
    414  1.39.2.10     skrll 				}
    415        1.2    bouyer 				ata_bio->error = ERR_DMA;
    416        1.2    bouyer 				ata_bio->r_error = 0;
    417        1.2    bouyer 				wdc_ata_bio_done(chp, xfer);
    418        1.2    bouyer 				return;
    419        1.2    bouyer 			}
    420        1.2    bouyer 			/* Initiate command */
    421   1.39.2.3     skrll 			if (wdc->select)
    422   1.39.2.1     skrll 				wdc->select(chp, xfer->c_drive);
    423   1.39.2.3     skrll 			bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
    424   1.39.2.1     skrll 			    0, WDSD_IBM | (xfer->c_drive << 4));
    425   1.39.2.1     skrll 			switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) {
    426   1.39.2.1     skrll 			case WDCWAIT_OK:
    427   1.39.2.9     skrll 				break;
    428   1.39.2.1     skrll 			case WDCWAIT_TOUT:
    429        1.2    bouyer 				goto timeout;
    430   1.39.2.1     skrll 			case WDCWAIT_THR:
    431   1.39.2.1     skrll 				return;
    432   1.39.2.1     skrll 			}
    433       1.34  christos 			if (ata_bio->flags & ATA_LBA48) {
    434   1.39.2.3     skrll 			    wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd),
    435       1.34  christos 				(u_int64_t)ata_bio->blkno, nblks);
    436       1.34  christos 			} else {
    437   1.39.2.1     skrll 			    wdccommand(chp, xfer->c_drive, cmd, cyl,
    438       1.34  christos 				head, sect, nblks, 0);
    439       1.34  christos 			}
    440        1.2    bouyer 			/* start the DMA channel */
    441   1.39.2.1     skrll 			(*wdc->dma_start)(wdc->dma_arg,
    442   1.39.2.1     skrll 			    chp->ch_channel, xfer->c_drive);
    443   1.39.2.3     skrll 			chp->ch_flags |= ATACH_DMA_WAIT;
    444   1.39.2.1     skrll 			/* start timeout machinery */
    445   1.39.2.1     skrll 			if ((xfer->c_flags & C_POLL) == 0)
    446   1.39.2.1     skrll 				callout_reset(&chp->ch_callout,
    447   1.39.2.1     skrll 				    ATA_DELAY / 1000 * hz, wdctimeout, chp);
    448        1.2    bouyer 			/* wait for irq */
    449        1.2    bouyer 			goto intr;
    450        1.2    bouyer 		} /* else not DMA */
    451  1.39.2.10     skrll  do_pio:
    452        1.2    bouyer 		ata_bio->nblks = min(nblks, ata_bio->multi);
    453        1.2    bouyer 		ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize;
    454   1.39.2.1     skrll 		KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0);
    455   1.39.2.1     skrll 		if (ata_bio->nblks > 1) {
    456        1.2    bouyer 			cmd = (ata_bio->flags & ATA_READ) ?
    457        1.2    bouyer 			    WDCC_READMULTI : WDCC_WRITEMULTI;
    458        1.2    bouyer 		} else {
    459        1.2    bouyer 			cmd = (ata_bio->flags & ATA_READ) ?
    460        1.2    bouyer 			    WDCC_READ : WDCC_WRITE;
    461        1.2    bouyer 		}
    462        1.2    bouyer 		/* Initiate command! */
    463   1.39.2.3     skrll 		if (wdc->select)
    464   1.39.2.1     skrll 			wdc->select(chp, xfer->c_drive);
    465   1.39.2.3     skrll 		bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
    466   1.39.2.1     skrll 		    WDSD_IBM | (xfer->c_drive << 4));
    467   1.39.2.1     skrll 		switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) {
    468   1.39.2.1     skrll 		case WDCWAIT_OK:
    469   1.39.2.1     skrll 			break;
    470   1.39.2.1     skrll 		case WDCWAIT_TOUT:
    471        1.2    bouyer 			goto timeout;
    472   1.39.2.1     skrll 		case WDCWAIT_THR:
    473   1.39.2.1     skrll 			return;
    474   1.39.2.1     skrll 		}
    475       1.34  christos 		if (ata_bio->flags & ATA_LBA48) {
    476   1.39.2.3     skrll 		    wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd),
    477       1.34  christos 			(u_int64_t) ata_bio->blkno, nblks);
    478       1.34  christos 		} else {
    479   1.39.2.1     skrll 		    wdccommand(chp, xfer->c_drive, cmd, cyl,
    480       1.34  christos 			head, sect, nblks,
    481       1.34  christos 			(ata_bio->lp->d_type == DTYPE_ST506) ?
    482       1.34  christos 			ata_bio->lp->d_precompcyl / 4 : 0);
    483       1.34  christos 		}
    484   1.39.2.1     skrll 		/* start timeout machinery */
    485   1.39.2.1     skrll 		if ((xfer->c_flags & C_POLL) == 0)
    486   1.39.2.1     skrll 			callout_reset(&chp->ch_callout,
    487   1.39.2.1     skrll 			    ATA_DELAY / 1000 * hz, wdctimeout, chp);
    488        1.2    bouyer 	} else if (ata_bio->nblks > 1) {
    489        1.2    bouyer 		/* The number of blocks in the last stretch may be smaller. */
    490        1.2    bouyer 		nblks = xfer->c_bcount / ata_bio->lp->d_secsize;
    491        1.2    bouyer 		if (ata_bio->nblks > nblks) {
    492        1.2    bouyer 		ata_bio->nblks = nblks;
    493        1.2    bouyer 		ata_bio->nbytes = xfer->c_bcount;
    494        1.2    bouyer 		}
    495        1.2    bouyer 	}
    496        1.2    bouyer 	/* If this was a write and not using DMA, push the data. */
    497        1.2    bouyer 	if ((ata_bio->flags & ATA_READ) == 0) {
    498   1.39.2.1     skrll 		/*
    499   1.39.2.1     skrll 		 * we have to busy-wait here, we can't rely on running in
    500   1.39.2.1     skrll 		 * thread context.
    501   1.39.2.1     skrll 		 */
    502   1.39.2.1     skrll 		if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) {
    503        1.2    bouyer 			printf("%s:%d:%d: timeout waiting for DRQ, "
    504        1.2    bouyer 			    "st=0x%02x, err=0x%02x\n",
    505   1.39.2.3     skrll 			    atac->atac_dev.dv_xname, chp->ch_channel,
    506   1.39.2.1     skrll 			    xfer->c_drive, chp->ch_status, chp->ch_error);
    507       1.16    bouyer 			if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR)
    508        1.2    bouyer 				ata_bio->error = TIMEOUT;
    509        1.2    bouyer 			wdc_ata_bio_done(chp, xfer);
    510        1.2    bouyer 			return;
    511        1.2    bouyer 		}
    512       1.16    bouyer 		if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) {
    513        1.2    bouyer 			wdc_ata_bio_done(chp, xfer);
    514        1.2    bouyer 			return;
    515        1.2    bouyer 		}
    516   1.39.2.2     skrll 		wdc->dataout_pio(chp, drvp->drive_flags,
    517   1.39.2.2     skrll 		    (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes);
    518        1.2    bouyer 	}
    519        1.2    bouyer 
    520        1.2    bouyer intr:	/* Wait for IRQ (either real or polled) */
    521        1.2    bouyer 	if ((ata_bio->flags & ATA_POLL) == 0) {
    522   1.39.2.3     skrll 		chp->ch_flags |= ATACH_IRQ_WAIT;
    523        1.2    bouyer 	} else {
    524        1.2    bouyer 		/* Wait for at last 400ns for status bit to be valid */
    525        1.2    bouyer 		delay(1);
    526   1.39.2.3     skrll 		if (chp->ch_flags & ATACH_DMA_WAIT) {
    527       1.26    bouyer 			wdc_dmawait(chp, xfer, ATA_DELAY);
    528   1.39.2.3     skrll 			chp->ch_flags &= ~ATACH_DMA_WAIT;
    529       1.26    bouyer 		}
    530       1.19    bouyer 		wdc_ata_bio_intr(chp, xfer, 0);
    531        1.2    bouyer 		if ((ata_bio->flags & ATA_ITSDONE) == 0)
    532        1.2    bouyer 			goto again;
    533        1.2    bouyer 	}
    534        1.2    bouyer 	return;
    535        1.2    bouyer timeout:
    536        1.2    bouyer 	printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n",
    537   1.39.2.3     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
    538        1.2    bouyer 	    chp->ch_status, chp->ch_error);
    539       1.16    bouyer 	if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR)
    540        1.2    bouyer 		ata_bio->error = TIMEOUT;
    541        1.2    bouyer 	wdc_ata_bio_done(chp, xfer);
    542        1.2    bouyer 	return;
    543        1.2    bouyer }
    544        1.2    bouyer 
    545   1.39.2.1     skrll static int
    546   1.39.2.3     skrll wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
    547        1.2    bouyer {
    548   1.39.2.3     skrll 	struct atac_softc *atac = chp->ch_atac;
    549   1.39.2.3     skrll 	struct wdc_softc *wdc = CHAN_TO_WDC(chp);
    550   1.39.2.1     skrll 	struct ata_bio *ata_bio = xfer->c_cmd;
    551   1.39.2.1     skrll 	struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
    552        1.2    bouyer 	int drv_err;
    553        1.2    bouyer 
    554   1.39.2.3     skrll 	ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n",
    555   1.39.2.3     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive),
    556        1.2    bouyer 	    DEBUG_INTR | DEBUG_XFERS);
    557        1.2    bouyer 
    558        1.2    bouyer 
    559        1.2    bouyer 	/* Is it not a transfer, but a control operation? */
    560        1.2    bouyer 	if (drvp->state < READY) {
    561        1.2    bouyer 		printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n",
    562   1.39.2.3     skrll 		    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
    563        1.2    bouyer 		    drvp->state);
    564       1.38    provos 		panic("wdc_ata_bio_intr: bad state");
    565        1.2    bouyer 	}
    566        1.2    bouyer 
    567       1.20    bouyer 	/*
    568       1.20    bouyer 	 * if we missed an interrupt in a PIO transfer, reset and restart.
    569       1.20    bouyer 	 * Don't try to continue transfer, we may have missed cycles.
    570       1.20    bouyer 	 */
    571       1.20    bouyer 	if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) {
    572       1.20    bouyer 		ata_bio->error = TIMEOUT;
    573       1.20    bouyer 		wdc_ata_bio_done(chp, xfer);
    574       1.20    bouyer 		return 1;
    575       1.20    bouyer 	}
    576       1.20    bouyer 
    577   1.39.2.1     skrll 	/* Ack interrupt done by wdc_wait_for_unbusy */
    578   1.39.2.1     skrll 	if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) {
    579       1.19    bouyer 		if (irq && (xfer->c_flags & C_TIMEOU) == 0)
    580       1.18    bouyer 			return 0; /* IRQ was not for us */
    581        1.2    bouyer 		printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n",
    582   1.39.2.3     skrll 		    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
    583        1.2    bouyer 		    xfer->c_bcount, xfer->c_skip);
    584        1.2    bouyer 		ata_bio->error = TIMEOUT;
    585        1.2    bouyer 		wdc_ata_bio_done(chp, xfer);
    586        1.2    bouyer 		return 1;
    587        1.2    bouyer 	}
    588   1.39.2.3     skrll 	if (wdc->irqack)
    589   1.39.2.1     skrll 		wdc->irqack(chp);
    590   1.39.2.9     skrll 
    591       1.16    bouyer 	drv_err = wdc_ata_err(drvp, ata_bio);
    592        1.2    bouyer 
    593        1.2    bouyer 	/* If we were using DMA, Turn off the DMA channel and check for error */
    594        1.2    bouyer 	if (xfer->c_flags & C_DMA) {
    595        1.2    bouyer 		if (ata_bio->flags & ATA_POLL) {
    596        1.2    bouyer 			/*
    597       1.13    bouyer 			 * IDE drives deassert WDCS_BSY before transfer is
    598        1.2    bouyer 			 * complete when using DMA. Polling for DRQ to deassert
    599       1.37       wiz 			 * is not enough DRQ is not required to be
    600        1.7    bouyer 			 * asserted for DMA transfers, so poll for DRDY.
    601        1.2    bouyer 			 */
    602        1.2    bouyer 			if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY,
    603   1.39.2.1     skrll 			    ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) {
    604        1.7    bouyer 				printf("%s:%d:%d: polled transfer timed out "
    605   1.39.2.3     skrll 				    "(st=0x%x)\n", atac->atac_dev.dv_xname,
    606   1.39.2.1     skrll 				    chp->ch_channel, xfer->c_drive,
    607   1.39.2.1     skrll 				    chp->ch_status);
    608        1.2    bouyer 				ata_bio->error = TIMEOUT;
    609       1.10    bouyer 				drv_err = WDC_ATA_ERR;
    610       1.10    bouyer 			}
    611       1.10    bouyer 		}
    612   1.39.2.1     skrll 		if (wdc->dma_status != 0) {
    613       1.10    bouyer 			if (drv_err != WDC_ATA_ERR) {
    614       1.10    bouyer 				ata_bio->error = ERR_DMA;
    615       1.10    bouyer 				drv_err = WDC_ATA_ERR;
    616        1.2    bouyer 			}
    617        1.2    bouyer 		}
    618        1.2    bouyer 		if (chp->ch_status & WDCS_DRQ) {
    619        1.2    bouyer 			if (drv_err != WDC_ATA_ERR) {
    620        1.2    bouyer 				printf("%s:%d:%d: intr with DRQ (st=0x%x)\n",
    621   1.39.2.3     skrll 				    atac->atac_dev.dv_xname, chp->ch_channel,
    622   1.39.2.1     skrll 				    xfer->c_drive, chp->ch_status);
    623        1.2    bouyer 				ata_bio->error = TIMEOUT;
    624        1.2    bouyer 				drv_err = WDC_ATA_ERR;
    625        1.2    bouyer 			}
    626        1.2    bouyer 		}
    627        1.2    bouyer 		if (drv_err != WDC_ATA_ERR)
    628        1.2    bouyer 			goto end;
    629   1.39.2.8     skrll 		if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA)
    630   1.39.2.7     skrll 			ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0);
    631        1.2    bouyer 	}
    632        1.2    bouyer 
    633        1.2    bouyer 	/* if we had an error, end */
    634        1.2    bouyer 	if (drv_err == WDC_ATA_ERR) {
    635        1.2    bouyer 		wdc_ata_bio_done(chp, xfer);
    636        1.2    bouyer 		return 1;
    637        1.2    bouyer 	}
    638        1.2    bouyer 
    639        1.2    bouyer 	/* If this was a read and not using DMA, fetch the data. */
    640        1.2    bouyer 	if ((ata_bio->flags & ATA_READ) != 0) {
    641       1.14    bouyer 		if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) {
    642        1.2    bouyer 			printf("%s:%d:%d: read intr before drq\n",
    643   1.39.2.3     skrll 			    atac->atac_dev.dv_xname, chp->ch_channel,
    644   1.39.2.1     skrll 			    xfer->c_drive);
    645        1.2    bouyer 			ata_bio->error = TIMEOUT;
    646        1.2    bouyer 			wdc_ata_bio_done(chp, xfer);
    647        1.2    bouyer 			return 1;
    648        1.2    bouyer 		}
    649   1.39.2.2     skrll 		wdc->datain_pio(chp, drvp->drive_flags,
    650   1.39.2.2     skrll 		    (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes);
    651        1.2    bouyer 	}
    652        1.2    bouyer 
    653        1.2    bouyer end:
    654        1.2    bouyer 	ata_bio->blkno += ata_bio->nblks;
    655        1.2    bouyer 	ata_bio->blkdone += ata_bio->nblks;
    656        1.2    bouyer 	xfer->c_skip += ata_bio->nbytes;
    657        1.2    bouyer 	xfer->c_bcount -= ata_bio->nbytes;
    658        1.2    bouyer 	/* See if this transfer is complete. */
    659        1.2    bouyer 	if (xfer->c_bcount > 0) {
    660        1.2    bouyer 		if ((ata_bio->flags & ATA_POLL) == 0) {
    661        1.2    bouyer 			/* Start the next operation */
    662       1.20    bouyer 			_wdc_ata_bio_start(chp, xfer);
    663        1.2    bouyer 		} else {
    664       1.20    bouyer 			/* Let _wdc_ata_bio_start do the loop */
    665        1.2    bouyer 			return 1;
    666        1.2    bouyer 		}
    667        1.2    bouyer 	} else { /* Done with this transfer */
    668        1.2    bouyer 		ata_bio->error = NOERROR;
    669        1.2    bouyer 		wdc_ata_bio_done(chp, xfer);
    670        1.2    bouyer 	}
    671        1.2    bouyer 	return 1;
    672       1.22     enami }
    673       1.22     enami 
    674   1.39.2.1     skrll static void
    675   1.39.2.3     skrll wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer,
    676   1.39.2.1     skrll     int reason)
    677       1.22     enami {
    678   1.39.2.1     skrll 	struct ata_bio *ata_bio = xfer->c_cmd;
    679   1.39.2.1     skrll 	int drive = xfer->c_drive;
    680       1.22     enami 
    681   1.39.2.3     skrll 	ata_free_xfer(chp, xfer);
    682       1.22     enami 
    683       1.22     enami 	ata_bio->flags |= ATA_ITSDONE;
    684   1.39.2.1     skrll 	switch (reason) {
    685   1.39.2.1     skrll 	case KILL_GONE:
    686   1.39.2.1     skrll 		ata_bio->error = ERR_NODEV;
    687   1.39.2.1     skrll 		break;
    688   1.39.2.1     skrll 	case KILL_RESET:
    689   1.39.2.1     skrll 		ata_bio->error = ERR_RESET;
    690   1.39.2.1     skrll 		break;
    691   1.39.2.1     skrll 	default:
    692   1.39.2.1     skrll 		printf("wdc_ata_bio_kill_xfer: unknown reason %d\n",
    693   1.39.2.1     skrll 		    reason);
    694   1.39.2.1     skrll 		panic("wdc_ata_bio_kill_xfer");
    695   1.39.2.1     skrll 	}
    696       1.22     enami 	ata_bio->r_error = WDCE_ABRT;
    697   1.39.2.3     skrll 	ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS);
    698   1.39.2.1     skrll 	(*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
    699        1.2    bouyer }
    700        1.2    bouyer 
    701   1.39.2.1     skrll static void
    702   1.39.2.3     skrll wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer)
    703        1.2    bouyer {
    704   1.39.2.3     skrll 	struct atac_softc *atac = chp->ch_atac;
    705   1.39.2.1     skrll 	struct ata_bio *ata_bio = xfer->c_cmd;
    706   1.39.2.1     skrll 	int drive = xfer->c_drive;
    707        1.2    bouyer 
    708   1.39.2.3     skrll 	ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n",
    709   1.39.2.9     skrll 	    atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
    710        1.5    bouyer 	    (u_int)xfer->c_flags),
    711        1.4    bouyer 	    DEBUG_XFERS);
    712       1.10    bouyer 
    713       1.24   thorpej 	callout_stop(&chp->ch_callout);
    714        1.2    bouyer 
    715        1.2    bouyer 	/* feed back residual bcount to our caller */
    716        1.2    bouyer 	ata_bio->bcount = xfer->c_bcount;
    717        1.2    bouyer 
    718   1.39.2.2     skrll 	/* mark controller inactive and free xfer */
    719   1.39.2.2     skrll 	chp->ch_queue->active_xfer = NULL;
    720   1.39.2.3     skrll 	ata_free_xfer(chp, xfer);
    721        1.2    bouyer 
    722   1.39.2.2     skrll 	if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) {
    723   1.39.2.2     skrll 		ata_bio->error = ERR_NODEV;
    724   1.39.2.2     skrll 		chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN;
    725   1.39.2.2     skrll 		wakeup(&chp->ch_queue->active_xfer);
    726   1.39.2.2     skrll 	}
    727        1.2    bouyer 	ata_bio->flags |= ATA_ITSDONE;
    728   1.39.2.3     skrll 	ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS);
    729   1.39.2.1     skrll 	(*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
    730   1.39.2.3     skrll 	ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n",
    731        1.4    bouyer 	    chp->ch_flags), DEBUG_XFERS);
    732   1.39.2.3     skrll 	atastart(chp);
    733        1.2    bouyer }
    734        1.2    bouyer 
    735   1.39.2.1     skrll static int
    736   1.39.2.1     skrll wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
    737        1.2    bouyer {
    738   1.39.2.3     skrll 	struct ata_channel *chp = drvp->chnl_softc;
    739        1.2    bouyer 	ata_bio->error = 0;
    740        1.2    bouyer 	if (chp->ch_status & WDCS_BSY) {
    741        1.2    bouyer 		ata_bio->error = TIMEOUT;
    742        1.2    bouyer 		return WDC_ATA_ERR;
    743        1.2    bouyer 	}
    744        1.2    bouyer 
    745        1.2    bouyer 	if (chp->ch_status & WDCS_DWF) {
    746        1.2    bouyer 		ata_bio->error = ERR_DF;
    747        1.2    bouyer 		return WDC_ATA_ERR;
    748        1.2    bouyer 	}
    749        1.2    bouyer 
    750        1.2    bouyer 	if (chp->ch_status & WDCS_ERR) {
    751        1.2    bouyer 		ata_bio->error = ERROR;
    752        1.2    bouyer 		ata_bio->r_error = chp->ch_error;
    753        1.2    bouyer 		if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF |
    754        1.2    bouyer 		    WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF))
    755        1.2    bouyer 			return WDC_ATA_ERR;
    756        1.2    bouyer 		return WDC_ATA_NOERR;
    757        1.2    bouyer 	}
    758        1.2    bouyer 
    759        1.2    bouyer 	if (chp->ch_status & WDCS_CORR)
    760        1.2    bouyer 		ata_bio->flags |= ATA_CORR;
    761        1.2    bouyer 	return WDC_ATA_NOERR;
    762        1.8   thorpej }
    763        1.8   thorpej 
    764   1.39.2.1     skrll static int
    765   1.39.2.1     skrll wdc_ata_addref(struct ata_drive_datas *drvp)
    766        1.8   thorpej {
    767   1.39.2.3     skrll 	struct ata_channel *chp = drvp->chnl_softc;
    768        1.8   thorpej 
    769   1.39.2.3     skrll 	return (ata_addref(chp));
    770        1.8   thorpej }
    771        1.8   thorpej 
    772   1.39.2.1     skrll static void
    773   1.39.2.1     skrll wdc_ata_delref(struct ata_drive_datas *drvp)
    774        1.8   thorpej {
    775   1.39.2.3     skrll 	struct ata_channel *chp = drvp->chnl_softc;
    776        1.8   thorpej 
    777   1.39.2.3     skrll 	ata_delref(chp);
    778        1.2    bouyer }
    779